JP2000113019A - Circuit designing method and design supporting device - Google Patents

Abstract

(57) [Summary] [Problem] It is not necessary to change a logic circuit description or a netlist.
Provided is a circuit design method capable of efficiently performing circuit change and correction in a short time even in a large-scale and complicated circuit, and appropriately performing high-speed optimization of the entire circuit by logic synthesis. A first logic synthesis unit performs logic synthesis for estimating circuit performance using only logic description circuit information, clock constraint data, and a mapping cell library. Based on the logic synthesis result,
The constraint condition determination unit 27 extracts all paths in the circuit, calculates a delay time, selects a path whose delay time exceeds the operation cycle, and performs timing constraint, load capacity constraint, and mapping for the path. Constraints are determined from the viewpoint of cell use restrictions, and constraint data 28 is generated.
Based on the constraint data 28, logic synthesis is performed in the second logic synthesis unit 29, and a netlist 30 optimized at high speed is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitable for use in, for example, the design of a circuit housed in a semiconductor device. The present invention relates to a circuit design method that can be performed and a design support device that supports such circuit design.

[0002]

2. Description of the Related Art In recent years, when designing a desired circuit realized as a semiconductor integrated circuit, a designer uses a hardware description language (HDL) to register a logic circuit at a register transfer level (RT).
L), and this is read as input data of a logic synthesis tool (hereinafter sometimes referred to as CAD) together with a mapping cell library, and gated (cell mapping) by logic synthesis is mainly used. It has become. However, with the increase in circuit scale and complexity, it has become difficult to realize all of the processing by CAD alone. For parts that cannot be processed by CAD, the designer must use data before and after processing ( HDL, netlist, etc.) must be separately modified or changed. In particular, such a situation is more likely to occur when designing a logic circuit that operates at high speed.

[0003] In the conventional high-speed processing using logic synthesis, logic synthesis is performed by giving a clock cycle and a delay value between registers as constraint conditions in the form of timing constraints, and the result is subjected to timing analysis. It is to determine whether or not to operate with a desired operation clock. However, as circuits become faster, designers have to determine timing constraints only by the maximum delay value of the path, and it becomes difficult to satisfy the constraints only by adding such timing conditions. Have been. Therefore, designers can manually insert latches (flip-flops) manually between registers that do not satisfy the constraints from the netlist of logic synthesis words, or return to the initial level of the design and identify critical parts in the logic circuit description. Work such as dividing the circuit was repeated to achieve higher speed.

Recently, in order to cope with such a problem, a method of calculating a delay time between registers from a logical description and optimizing a circuit in consideration of a load and a driving ability in addition to a timing constraint has been proposed. Proposed. For example, Japanese Patent Laid-Open No. 7-7142 discloses that a path delay time is calculated from a logical description, and a path is separated and extracted according to the delay time.
A method of performing net analysis of an extracted path and optimizing a circuit is disclosed. As the optimization method, the drive capacity is improved by changing the insertion position of the buffer inside the circuit to the optimum position, and the logical relationship based on the cells in the path to be optimized is maintained A method is shown in which a cell is duplicated to a path that is not targeted for optimization while the cell is not optimized.

[0005]

However, in the conventional circuit optimizing method as described above, the logic description is changed in the course of the optimizing process, or the applied circuit has a specific data path system. There is a problem that the circuit is limited to the above. In large-scale and complicated circuits such as system LSI development, the number of changed parts is expected to increase.
There is also a problem that an optimizing process such as a circuit change or correction takes a long time. Further, there is a disadvantage in that the reusability of circuit data in RTL is lost due to a change in a logic circuit description, a netlist, or the like.

Accordingly, it is an object of the present invention to make it possible to efficiently and quickly change and modify a large-scale and complicated circuit without having to change the description of the logic circuit or the netlist, and to achieve high-speed optimization of the entire circuit. An object of the present invention is to provide a circuit design method that can be appropriately performed by synthesis. Another object of the present invention is to eliminate the need to change a logic circuit description or a netlist, to efficiently and quickly change or modify a large-scale and complicated circuit, and to achieve high-speed optimization of the entire circuit by logic synthesis. It is an object of the present invention to provide a design support device that can perform the program more appropriately.

[0007]

In order to solve the above-mentioned problems, a circuit design method according to the present invention generates a desired circuit by performing logic synthesis on an inputted logic circuit description, More specifically, a path for each section in which signal processing is to be performed within one cycle is extracted, a characteristic of the generated circuit including a processing time for each extracted path is detected, and a determination is made based on a result of the detection. Based on the conditions at the time of the logic synthesis, the logic circuit description is again subjected to logic synthesis to generate a circuit having desired characteristics.

Preferably, the detection of the characteristic of the circuit includes a process of detecting, from the extracted paths, a path whose processing time of the path is longer than the operation cycle of the path, and the logical synthesis again is performed. The processing is performed based on conditions set so that the processing time of the detected path is within the operation cycle of the path. Specifically, the condition at the time of the second logic synthesis is a condition including designation of a load capacity of a cell and designation of a cell to be used.

Further, the design support apparatus of the present invention comprises: a first logic synthesizing means for performing logic synthesis on an input logic circuit description to generate a desired circuit; Path extracting means for extracting a path for each section in which signal processing is to be performed, characteristic detecting means for detecting the characteristic of the generated circuit including a processing time for each extracted path, and a result of the detection And a second logic synthesizing unit that performs logic synthesis again on the logic circuit description based on the logic synthesis condition determined and input based on the logic synthesis to generate a circuit having desired characteristics.

Preferably, the characteristic detecting means detects, from the extracted paths, a path in which the processing time of the path is longer than the operation cycle of the path, and the second logic synthesizing means detects the path. The processing is performed based on the conditions set so that the processing time of the given path falls within the operation cycle of the path. Specifically, the condition at the time of the second logic synthesis is a condition including designation of a load capacity of a cell and designation of a cell to be used. Preferably, the first logic synthesis means performs logic synthesis on the input logic circuit description based only on a condition based on an operation clock with reference to a cell library prepared in advance.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS. First, a general configuration of a circuit to be designed will be described from the viewpoint of speeding up the circuit. FIG. 1 is a diagram showing a general configuration of a circuit to be designed. In a general logic circuit, as shown in FIG.
It exists between (path). This is referred to as RTL (register transfer level) in the upstream design method, and is treated as a basic circuit configuration.

In such a circuit, data first enters the input register 11 in synchronization with a clock signal. Then, the signal processing of the combinational logic 12 is performed within the clock cycle time (Tc), and is input to the register 13 on the receiving side. At this time, the time required for data processing (Td)
Cannot perform desired processing unless the time is shorter than the clock cycle time (Tc), and data does not properly propagate between registers (paths). That is, a relationship such as Equation 1 is required between the clock cycle time (Tc) and the data processing time (Td).

[0013]

## EQU1 ## Clock cycle time (Tc)> Data processing time (Td)

In order for such a logic circuit to operate at high speed, the clock cycle time (Tc) must be shortened. Further, from the above description, the data processing time (Td) between the registers is reduced by the clock cycle. You will have to spend less time.

Next, a design support system according to the present embodiment will be described. FIG. 2 is a block diagram illustrating a configuration and a processing flow of the design support system according to the present embodiment.
The design support system 20 includes a first logic synthesis unit 24, a constraint condition determination unit 27, and a second logic synthesis unit 29 as processing units.

The first logic synthesizing section 24 receives the input HD
The circuit information 21 logically described by L is logically synthesized with reference to the mapping cell library 23, and an analysis netlist 25 and a logical synthesis result report 26 are output. At this time, the first logic synthesis unit 24 performs logic synthesis using only information based on the operation clock provided as the clock constraint data 22 as constraint information.

The constraint condition determination unit 27 analyzes the analysis netlist 25 and the logic synthesis result report 26 generated by the first logic synthesis unit 24 and performs logic synthesis on a circuit that operates at a desired operation speed. The constraint condition to be generated is determined by the formula (1), and is output as the constraint condition data 28.

The processing in the constraint condition determining section 27 will be described in detail with reference to FIG. FIG. 3 is a flowchart for explaining a method of determining the constraint condition of the path in the constraint condition determination unit 27. Constraint condition determining unit 27
First, all paths in the circuit are extracted from the analysis netlist 25 generated by the logic synthesis in the first logic synthesis unit 24 and the result report 26, and the delay time is calculated (step S271). ). Next, since the operation speed of the circuit becomes the design target value of the delay time of the path, the path is separated for each circuit having the same operation speed (step S272). Thus, the paths existing in the same clock system can be clarified, so that the range in which the constraint condition is given can be limited, and the application accuracy of the constraint condition at the time of logic synthesis is improved.

Next, a path whose delay time exceeds the operation cycle defined by the operation speed is selected, and the mapping state of the cells in the path, the delay time, and the processing time required for the logical operation of each cell are analyzed. (Step S27)
3). Based on the analysis result, the constraint condition in the logic synthesis is determined from the viewpoint of the timing constraint, the load capacity constraint, and the use restriction of the mapping cell (step S274). Similar processing is sequentially performed on other paths that do not satisfy the conditions, and the paths are added to the constraint conditions (step S275). Then, when the processing is performed on all the circuits to which the high-speed optimization that does not satisfy the condition is applied, the path constraint condition data is output, and the processing ends (step S276).

The second logic synthesizing unit 29 performs logic synthesis of the logic description circuit information 21 with reference to the mapping cell library 23, similarly to the first logic synthesis unit 24, and outputs a netlist 30 and a logic synthesis result report. 26 is output. At this time, the second logic synthesizing unit 29
The logic synthesis is performed using the constraint data 28 generated by the above as constraint information. The algorithm and method of the logic synthesis of the second logic synthesis unit 29 are the same as those of the first logic synthesis unit 24.
Is the same as

Next, the operation of the design support system 20 and the flow of circuit design processing using the design support system 20 will be described with reference to specific examples. First, the first logic synthesis unit 24 performs logic synthesis for estimating circuit performance. In this logic synthesis, logic description circuit information 2
1. This is performed using only the clock constraint data 22 and the mapping cell library 23. The clock constraint data 22 at this time is only the setting of the cycle time of the clock indicating the operating frequency, and does not include anything that restricts the circuit characteristics. Based on the result of the logic synthesis in the first logic synthesis unit 24, the basic operation performance of the generated circuit can be grasped. In other words, from this estimation result, how much operating frequency can be obtained,
It is possible to know how much delay value should be set for that purpose.

Therefore, in the constraint condition determining unit 27,
First, in step S272, the first logic synthesis unit 2
4, all paths in the circuit are extracted from the analysis netlist 25 generated by the logic synthesis and the result report 26, and the delay time is calculated. The delay time of the path of the generated circuit can be represented by a distribution as shown in FIG. 4, for example. This circuit is operated by two clocks, and T1 and T2 indicate the operation speed, that is, the operation target time.

In the distribution shown in FIG. 4, the delay time of the path is distributed in a form where two clock systems are mixed. In this state, even if constraints are imposed on the delay times of these paths, the optimal constraints will not be obtained. Therefore, in step S272, this is decomposed into a group of paths for each operation target time (clock cycle). As a result, the two clock systems can be classified and displayed as shown in FIG. By looking at this, it is possible to clarify which path has not reached the operation target. That is, as shown in FIG. 5A, for the target time of T1, PATH3, 7, 11, 12, 13, and 14 do not satisfy the delay time condition, and it is necessary to reduce the processing time of the path. Considering T2 in the same way, from FIG.
It can be seen that ATHs 1, 2, 5, 8, 16, and 19 violate constraints. Note that if the path delay time is within the operation target time, it is not a target of high-speed optimization.

If the path can be decomposed for each clock, in step S273, a path whose delay time exceeds the operation cycle defined by the operation speed is selected, and what kind of cell constitutes the path is determined. Also, what is the delay time of each cell?
Analyze more. For example, FIG. 6 shows the result of analyzing a certain path. The delay time of this path is 18.9
0 nsec, and the operation target is 15.00 nsec.

Next, as step S274, based on the result of the analysis, a constraint condition in logic synthesis is determined from the viewpoint of a timing constraint, a load capacity constraint, and a limitation on the use of a mapping cell. First, as shown in FIG. 1, the timing constraint sets the data processing time (Td) of the path as the maximum delay value so as to be shorter than the clock cycle (Tc). Then, the maximum delay value is determined based on the result of the logic synthesis performed by the first logic synthesis unit 24 for estimation so that the processing of the path becomes the shortest. For example, for the path illustrated in FIG. 6, 15 nsec is given as a constraint.

The load capacity constraint estimates the load delay and the driving capacity from the processing time of each cell and gives the processing time to be minimized. FIG. 7 shows an example of a circuit when a load capacity constraint condition is given. In this circuit, as shown in FIG. 7A, the output Q of the register (REG) R0 branches to four nodes, and the four logic circuits (Logic) L
0, L1, L2, L3, respectively, and the fan-out is 4. Therefore, the load capacity of R0 is 4
It is divided into two nodes, and the drive capacity is １ ／ of the output drive of the register R0.

In such a case, with respect to the output of the register R0, the restriction of the load capacity so that the fan-out becomes 1 is specified. If such designation is made, FIG. 7 (B)
As shown in the figure, a buffer (BU) is provided at the output of the register R0 so that the output of the register R0 becomes the fan-out 1.
F) is inserted. In this way, the register R0 can drive the buffer BUF at a sufficiently high speed, and the buffer is selected to have an appropriate drive capacity, but is usually at least higher than the output drive of the register R0. Since the drive capability is high, the output to each logic circuit is also speeded up. Also, the registers R0 to R01, the registers R0 to R11, the registers R0 to R21, the registers R0 to R3
Since the most strict timing constraints are given to the path between 1 in advance, if the drive capacity is enhanced,
The speed of the logic circuit of FIG. 7 is further increased.

In the present embodiment, the restriction on the use of the mapping cell is intended to further increase the speed of optimization in addition to the constraints when optimization cannot be realized even with the constraints given so far. . The restriction on the use of the mapping cells imposes restrictions sequentially from cells having a large ratio to the delay time. When such a constraint is added, in the logic synthesis processing, in order to maintain the equivalent logic, an attempt is made to replace and map a cell with a short processing time or to map an equivalent logical structure with another cell. As a result, since the timing constraint and the load capacity constraint are also given at the same time, the inside of the path is entirely constituted by high-speed cells.

The determination method will be specifically described.
In FIG. 6, a cell having a select function of SL1204 is indicated by an underline, and a cell having a buffer function of VF1003 is indicated by an asterisk. FIG. 8 shows cells arranged in the path shown in FIG. 6 arranged in descending order of delay time. FIG. 9 shows the sum of the delay times of the paths calculated for each cell based on FIG. As can be seen from FIGS. 8 and 9, SL1204 and VF1
It can be seen that the cell 003 accounts for a large proportion of the delay time in the path shown in FIG. Therefore, a mapping restriction constraint that prohibits use of such two cells is given.

The determination of such constraints is repeatedly examined until the constraints satisfy all the paths to be optimized. However, there are cases where it is difficult to satisfy the condition even if the same constraint is given to all the paths. In this case, the constraint may be valid only for the designated path. By performing the optimization process on all the paths that need to be performed, the constraint condition determination process in the constraint condition determination unit 27 ends, and the constraint data 28 is generated.

The constraint data 28 is stored in the second
Given at the time of logic synthesis in the logic synthesis unit 29 of
A high-speed optimized netlist 30 can be obtained. FIG. 10 shows the result of performing logic synthesis on the path shown in FIG. 6 with the various restrictions described above.
As shown in FIG. 10, the SL 1204 has been reconfigured with another cell, and the VF 1003 has VF 1004, VF 100
6. It can be seen that the high-speed cell of the VF 1008 is replaced and mapped in the path. In addition, due to these restrictions, as a result, the path delay time is reduced to 14.04 nsec, which satisfies the design target of 15.00 nsec, indicating that high-speed optimization has been performed.

The correction of the delay value and the like may be performed by adjusting the constraint condition data 28 with reference to the logic synthesis result report 31 output together with the netlist 30.

As described above, in the design support system 20 according to the present embodiment, the high-speed processing which has conventionally been performed in the logic synthesis and the correction of the logic circuit data before and after the logic synthesis is performed.
Eventually, it could be handled only by logic synthesis processing. Therefore, the man-hours spent for this correction work in the design process can be significantly reduced. In addition, manual processing is not required, human error is eliminated, and circuit quality can be improved. Further, the circuit data generated by the design support system 20 is CAD
, The design data can be capitalized. For example, it can be used for other designs. In addition, the design support system 20 can increase the speed of a circuit which is large and whose speed has been difficult to increase. In addition to the speed-up processing, the approach by the design support system 20 can be applied to the optimization processing of the timing constraint that took the most work time in the logic synthesis process, and the man-hour required for the timing optimization in the design process is reduced. It is also effective for shortening.

Note that the present invention is not limited to the present embodiment, and various suitable modifications are possible. For example, the configuration of the design support system 20 may be configured by software on a general-purpose computer system such as an ordinary workstation, or may be configured by dedicated hardware. Further, a specific method of logic synthesis, an algorithm, or the like may be an arbitrary method. A generally used logic synthesis tool may be used.

The contents of the circuit to be designed are not limited at all, and can be applied to the design of an arbitrary circuit. Further, it does not depend on the manufacturing conditions such as the design rule of the semiconductor integrated circuit to be manufactured. By using a mapping cell library prepared based on the manufacturing conditions and the like, it can be applied to the design of an arbitrary semiconductor integrated circuit.

[0036]

As described above, according to the present invention, there is no need to change the logic circuit description or the netlist, and even in a large-scale and complicated circuit, the circuit can be changed and modified efficiently in a short time.
It is possible to provide a circuit design method and a design support device capable of appropriately performing high-speed optimization of an entire circuit by logic synthesis.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a basic configuration of a logic circuit.

FIG. 2 is a block diagram illustrating a configuration and a processing flow of the design support system according to the embodiment of the present invention;

FIG. 3 is a flowchart for explaining a method of determining a constraint condition in a constraint condition determining unit of the design support system shown in FIG. 2;

FIG. 4 is a first view of the design support system shown in FIG. 2;
FIG. 10 is a diagram illustrating a distribution of delay times of paths as a result of logic synthesis in the logic synthesis unit of FIG.

FIG. 5 is a diagram showing the distribution of delay times of the path shown in FIG. 4 for each operating frequency.

FIG. 6 is a first view of the design support system shown in FIG. 2;
3 is a diagram showing a path structure of a path having a result of logic synthesis in a logic synthesis unit of FIG.

FIG. 7 is a diagram illustrating an example of a circuit for explaining assignment of a load capacity constraint condition when determining the constraint condition illustrated in FIG. 3;

FIG. 8 shows cells existing in the path shown in FIG. 6;
It is a figure shown in order from the thing with a large delay time.

FIG. 9 is a diagram illustrating a sum of delay times of paths for each cell based on FIG. 8 for cells existing on the path illustrated in FIG. 6;

FIG. 10 is a diagram illustrating a path structure after optimizing the path illustrated in FIG. 6 and a delay time thereof.

[Explanation of symbols]

11 ... input stage register, 12 ... combinational logic, 13 ...
Output stage register, 20 design support system, 21 logic description circuit information, 22 clock constraint data, 23 mapping cell library, 24 first logic synthesis unit, 25
... Analysis netlist, 26 ... Logic synthesis result report,
27 ... constraint condition determination unit, 28 ... constraint condition data, 29 ...
Second logic synthesis unit, 30 ... net list, 31 ... logic synthesis result report

Claims (7)

[Claims] 1. A logic circuit is synthesized with respect to an input logic circuit description to generate a desired circuit, and a path for each section in which signal processing is to be performed within one cycle is extracted from the generated circuit. Detecting the characteristic of the generated circuit including the processing time for each extracted path, based on the condition at the time of logic synthesis determined based on the result of the detection, A circuit design method for performing logic synthesis to generate a circuit having desired characteristics. 2. The method according to claim 1, wherein detecting the characteristic of the circuit includes detecting, from the extracted path, a path whose processing time of the path is longer than the operation cycle of the path. 2. The circuit design method according to claim 1, wherein the processing is performed based on a condition set so that a processing time of the detected path is within an operation cycle of the path. 3. The circuit design method according to claim 2, wherein the condition at the time of the second logic synthesis is a condition including designation of a load capacity of a cell and designation of a cell to be used. 4. A first logic synthesis means for performing logic synthesis on an input logic circuit description to generate a desired circuit, and a section in which signal processing is to be performed within one cycle by the generated circuit. Path extraction means for extracting a path for each path; characteristic detection means for detecting a characteristic of the generated circuit including a processing time for each of the extracted paths; determined and input based on a result of the detection A second logic synthesis means for performing logic synthesis on the logic circuit description again based on a condition at the time of logic synthesis to generate a circuit having desired characteristics. 5. The characteristic detecting means detects, from the extracted paths, a path in which the processing time of the path is longer than the operation cycle of the path, and the second logic synthesizing means detects the detected path. The design support apparatus according to claim 4, wherein the processing is performed based on a condition set so that a processing time of the path is within an operation cycle of the path. 6. The design support apparatus according to claim 5, wherein the condition at the time of the second logic synthesis is a condition including designation of a load capacity of a cell and designation of a cell to be used. 7. The logic synthesis means according to claim 4, wherein the first logic synthesis means refers to a cell library prepared in advance and performs logic synthesis on the input logic circuit description based only on a condition based on an operation clock. 3. The design support device according to 1.