JP2000112835A - Memory device, data recording / reproducing device, and computer system - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reduce the trouble of managing a list of a data buffer memory, etc., and even in a case where an HDD fails and data cannot be read correctly, the data buffer memory is normally read. Access that is equivalent to SOLUTION: An interconnect I / F circuit 11, a memory array 14 divided into a data memory 14D and a parity memory 14P, and an address mapping setting unit 1 for mapping the array 14 into a plurality of individual address spaces.
3, a memory access control unit 12 for controlling access to the array 14 based on the setting, a data / parity ratio setting unit 15 for setting a data-parity ratio, and a parity operation for calculating a parity based on the ratio. A unit 16 is provided to write-access the parity to the memory 14P after writing data to the memory 14D. Further, a parity memory mapping setting unit 17 is provided to improve the efficiency at the time of data reconstruction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to, for example, a plurality of HDs.
The present invention relates to a memory device suitable for a disk array device or the like configured in parallel with D (hard disk drive), a data recording / reproducing device using the memory device, and a computer system.

[0002]

2. Description of the Related Art Conventionally, as a technique for improving the speed and reliability of a disk I / O, for example, a disk array device having a plurality of HDDs in a parallel redundant configuration has been known.

[0003] A systematic classification of the disk array devices according to the configuration method is described in a paper "A Case for Redundant" by Patterson et al. Of the University of California, Berkeley.
Arrays of Inexpensive Disks (RAID) [csd-87-391] ”. That is, according to this paper, RAI of 1 to 5
D level is defined.

[0004] RAID-1 enables mirroring by combining two disks, writes the same data on two disks by the mirroring, and enables continuation of processing even if one of the disks fails. . Even if one disk fails, normal data remains on the other disk.

[0005] In RAID-2, ECC data based on a Hamming code is recorded on another N disks, so that not only disk failures but also data errors can be corrected. I have.

[0006] RAID-3 has one parity disk for N data disks instead of completely duplexing by mirroring, so that the processing can be continued even if one drive fails. It is made possible. Striping is performed in units of 1 bit or 1 byte. Even if one of the data disks fails, the parity can be decomposed from the other drives to generate the original data, so that the processing can be continued without losing the data. Of course, even if the parity disk fails, there is no problem in data access as long as the data disk is normal. However, although the configuration is simpler than that of RAID-5, it lacks access symmetry, for example, access concentrates on the parity disk in writing.

In RAID-4, the striping unit smaller than that of RAID-3 is set to a sector or more, and this RAID-4 is also collectively referred to as RAID-4.
-3, and the expression RAID-4 is rarely used.

In RAID-5, N data and one parity are not fixedly allocated to N + 1 data disks, but parity is equally distributed (parity is allocated to each disk). This enables simultaneous rewriting at two or more locations. RAID
In -3, the disk access is concentrated on the parity disk, and the parity disk is distributed so that the disk access is distributed to improve the throughput.

[0009] There are various mounting methods for implementing the above-mentioned RAID, but a parity memory is used when hardware is supported. With respect to this parity memory, an apparatus for generating a parity block is disclosed in Japanese Patent Application Laid-Open No. 10-105476. That is, the parity block generation device described in this publication generates parity data from a plurality of data words.
A first parity memory, a second parity memory, and a memory configured to receive the plurality of data words and coupled to the first parity memory and the second parity memory to generate the parity data And a parity and control unit (disk array controller) for selectively storing therein and selectively loading therefrom.

[0010]

Here, RA is representatively used.
The flow of the control operation by the disk array controller of the conventional disk array device will be described by taking, as an example, the case where ID-3 is applied and the number of HDDs constituting the disk array is N + 1. This RAID-3
Although not shown, the basic configuration of the disk array device is at least a single buffer memory for input / output, a disk array controller for controlling the whole, a plurality of HDDs, and a plurality of HDDs. An HDD I / F controller for controlling data transmission and reception between the
It has a buffer memory for DD write / read data and a parity memory for parity data.

FIG. 18 shows a flowchart of the write operation in the conventional RAID-3 disk array device.

In FIG. 18, first, in step S101, the disk array controller converts the input data input to and accumulated in a single buffer memory into N data of a stripe unit size in response to a write request. And read them out.

In step S102, the disk array controller creates a stripe window of a stripe unit size in the parity memory. In step S103, the disk array controller creates a parity buffer in the data buffer memory and the parity memory for writing N data. Associate with a window.

Next, at step S104, the disk array controller writes the N pieces of data into the data buffer memory and, at the same time, generates parity data and writes it into the parity window on the parity memory.

Thereafter, the disk array controller:
In step S105, the data is read from the data buffer memory, the parity data is extracted from the parity window of the parity memory, and the HDDI /
Send to F controller. Then, the HDD I / F controller writes the N data from the data buffer memory and the parity data from the parity memory to each HDD.

As described above, when data is written in a conventional disk array device of RAID-3, the disk array controller calculates the parity using the parity memory, so that the data requested to be written is divided by 1 /. It is necessary to divide the data into N and write data to a data buffer memory that operates in conjunction with the parity memory.
Therefore, a data structure for managing N data buffers is required.

FIG. 19 is a flowchart showing a read operation in the conventional RAID-3 disk array device.

In FIG. 19, in step S111, the HDD I / F controller reads the N data from each of the HDDs to which the N data has been written and also writes the parity data to the HDD.
From the parity data.

Next, in the disk array controller,
In step S111, at the same time as reading (writing) these N pieces of data into the data buffer memory, an exclusive OR (XOR) operation using the parity data is executed in the parity window of the parity memory.

Here, the disk array controller is:
In step S113, it is determined whether or not the HDD is broken.
If it is not broken, the process proceeds to step S115.

When the disk array controller determines that one HDD is broken in step S113,
N-1 from the HDD not broken in step S114
The data and parity data are read (written) into a single buffer memory, and the data is reconstructed.

On the other hand, when the disk array controller determines in step S113 that the HDDs are not damaged, the disk array controller reads (writes) the N data from the non-damaged HDDs into a single buffer in step S115. Reconstruct the data.

As described with reference to FIG.
When reading data in the conventional disk array device of No.-3, the disk array controller reads data read from N + 1 HDDs into N + 1 data buffer memories including a parity memory in the same manner as when writing data. ) Later, the data is combined into one using the data structure managing the N data buffer memories.

Further, when, for example, one of the HDDs fails, the lost data can be recovered by using the parity data held in the parity memory. Needs to access the corresponding parity memory every time instead of the data buffer memory that contains the data from the failed HDD, and therefore manages the data buffer memory in addition to the read operation when there is no failure. You need to change the data structure you are using.

Therefore, the present invention has been made in view of such a situation, and can reduce the trouble of managing the data buffer memory list and the like. It is an object of the present invention to provide a memory device capable of performing equivalent access to a parity memory as usual, and a data recording / reproducing device and a computer system using the memory device.

[0026]

A memory device according to the present invention comprises:
Interconnect connection means connected to one or more interconnects, a memory array as a physical memory, mapping setting means for mapping the memory array to a plurality of individual address spaces, and access to the memory array based on the setting of the mapping. By having the memory access control means for controlling, the above-mentioned problem is solved.

Further, the memory device of the present invention comprises an interconnect connection means connected to a single or a plurality of interconnects, a memory array as a physical memory, and a sub memory array formed of a part of the memory array or a separate sub memory. The above-mentioned problem is solved by using an array and having a sub memory array mapping setting means for converting an arbitrary unit access to the memory array into an access to a corresponding sub memory array by setting.

Here, the memory device of the present invention uses the memory array by dividing it into a data memory and a parity memory, or uses a sub memory array that is a part of the memory array or a separate sub memory array as a parity memory. Data / parity ratio setting means for setting a data / parity ratio, and calculating parity for any continuous N unit write accesses from one address space based on the setting of the data / parity ratio The above-described problem is solved by providing a parity operation unit that performs write access to the parity memory after writing data to the data memory.

Next, a data recording / reproducing apparatus according to the present invention comprises a memory device according to the present invention, a recording medium array including a plurality of recording media, recording medium array control means for controlling the recording medium array, and a recording medium array. The recording medium array interface means for controlling data transmission and reception between the recording medium array control means and the recording medium array control means, wherein the recording medium array control means and the recording medium array interface means use different address spaces; Solve.

Further, a computer system according to the present invention includes the memory device according to the present invention and the data recording / reproducing device according to the present invention, and is configured by connecting the memory device and the data recording / reproducing device via an interconnect. The above-mentioned problem is solved.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a first configuration example of a system to which the memory device 1 according to the embodiment of the present invention is applied.

The system shown in FIG. 1 has a CPU 2, a host / PCI (Peripheral Component Interconnect).
A configuration incorporated in a normal computer having a bridge unit 3, a main memory 4, an input / output device 5, etc., a disk array controller 6, a memory device 1, an HDDI /
The configuration of a disk array device, which is a data recording / reproducing device having an F controller 7 and a plurality of HDDs 8 and the like, is a computer system in which each is connected by a PCI bus.

The CPU 2 controls the operation of the entire system,
The host / PCI bridge unit 3 exchanges data between the PCI bus and the CPU 2 and also includes a function of a memory controller that controls the main memory 4. The input / output device 5 includes an operation input device such as a keyboard and a mouse, a display device such as a display, various connectors connected to external devices, and the like.

The disk array controller 6 including a CPU and the like includes a PCI bridge unit, and transfers data received from a host computer to a plurality of H devices via a memory device 1 and an HDD I / F controller 7 described later.
Data is written to the DD 8, and data read from the HDD 8 and transmitted through the HDD I / F computer 7 and the memory device 1 is sent to the host computer.

The HDD I / F controller 7 has a plurality of H
It controls the management of the DD 8 and the recording / reproduction of data, and sends and receives data to and from the disk array controller 6 and the memory device 1.

The memory device 1 is a main part of the present invention, and its configuration and operation will be described below.

FIG. 2 shows a schematic configuration of the memory device 1 according to the first embodiment of the present invention.

The memory device 1 according to the first embodiment includes:
It is connected to a single or a plurality of interconnects via an interconnect I / F circuit 11, can be mapped to a plurality of address spaces, and sets how to map a physical memory to each address space. It is characterized by having an address mapping setting unit 13 that can be used, a memory access control unit 12 that operates based on the settings made by the address mapping setting unit 13, and a memory array 14 that is a physical memory.

That is, since the memory device 1 according to the first embodiment is connected to a certain interconnect, the memory device 1 includes an interconnect I / F circuit 11 as an interface circuit to the interconnect, and the memory array 14 A memory access control unit 12 for memory access is provided.

The memory device 1 according to the first embodiment has a certain range of address space, and can freely enter the address space from the interconnect side via the interface I / F circuit 11 and the memory control circuit 12. Access has been made possible.

The address mapping setting section 13 is a mechanism for mapping a continuous memory space on the memory array 14 to an arbitrary memory access. The setting here is notified to the memory access control unit 12 and is reflected at the time of memory access.

For example, when the address space in the memory device 1 is divided into two spaces, A space and B space. For example, when the memory array 14 is regarded as a 4 × 4 array, the access from the A space is Address 0 Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 7 Address 8 Address 9 Address 10 Address 11 Address 12 Address 13 Address 14 Address 15 0 Address 4 Address 8 Address 12 Address 1 Address 5 Address 9 Address 13 Address 2 Address 6 Address 10 Address 14 Address 3 Address 7 Address 11 Address 15

As described above, according to the present invention, two consecutive accesses to the same memory area can have different results. In the present invention, using this function,
The operation efficiency of the disk array controller is improved.

Next, FIG. 3 shows a schematic configuration of a memory device 1 according to a second embodiment of the present invention. 3 having the same functions as those of FIG. 2 are designated by the same reference numerals and the description thereof will be omitted.

The memory device 1 according to the second embodiment comprises:
The memory array 14 is divided into a data memory 14D and a parity memory 14P, and further used is a data / parity ratio setting unit 15 for setting a data / parity ratio (setting an integer N of N: 1). A parity operation unit 16 for calculating a parity for an arbitrary continuous N unit write accesses from a certain address space based on the setting of the data / parity ratio. It is characterized in that write access is made to 14P. Therefore,
The memory access control unit 12 also controls access to the parity memory 14P.

The example of FIG. 3 shows a case where the data / parity ratio is, for example, 4: 1. In this case, FIG.
HDDs 8 are at least four HDDs for data and one HDD for parity.

The specific operation of the memory device 1 according to the second embodiment is as follows.

Here, a unit of data transmitted on an interconnect such as a PCI bus is usually a word unit. Therefore, the write data sent from the host computer to the disk array controller 6 is, for example, data D0 and data D0 shown in FIG.
Assuming that the data is sent as a burst transfer of unit data (data in units of words), such as 1, data D2 and data D3, the memory device 1 according to the second embodiment operates in the following procedure. I do.

That is, if the data memory 14D of the memory array 14 is regarded as a 4 × 4 array and the access from the host computer to the memory device 1 follows the access order from the space A, first, 1
In the initial state, there is no data on the data memory 14D No data No data No data No data No data No data No data No data No data No data No data No data No data No data No data There is no data, and the parity operation unit 16 is cleared (0).

Next, as a second step, the data D is transmitted from the host computer to the disk array controller 6.
When write data of 0 is sent, the data memory 14
Data D0 is stored in the area of address 0, such as data D0 No data No data No data No data No data No data No data No data No data No data No data No data No data No data No data Further, the parity operation unit 16 performs an exclusive OR operation of the initial value 0 and the data D0 in the first step.

Next, as a third step, the data D is transmitted from the host computer to the disk array controller 6.
When the 1 write data is sent, the data memory 14
On D, data D1 is stored in the area of address 1, such as Data D0 Data D1 No data No data No data No data No data No data No data No data No data No data No data No data No data In addition, the parity operation unit 16 outputs data D0 and data D1.
And the exclusive OR operation is performed.

Next, as a fourth step, the data D is transmitted from the host computer to the disk array controller 6.
2 write data, the data memory 14
On data D, data D2 is stored in the area of address 2 like data D0 data D1 data D2 no data no data no data no data no data no data no data no data no data no data no data no data In addition, the parity operation unit 16 outputs data D0 and data D1.
And the data D2 are subjected to an exclusive OR operation.

Next, as a fifth step, the data D is transmitted from the host computer to the disk array controller 6.
3 is sent, the data memory 14
On D, data D3 is stored in the area of address 3, such as Data D0 Data D1 Data D2 Data D3 No data No data No data No data No data No data No data No data No data No data No data In addition, the parity operation unit 16 outputs data D0 and data D1.
The exclusive OR operation of data D2 and data D3 is performed. Thus, the parity calculation is completed, and the obtained parity data is written to the parity memory 14P.

Thereafter, subsequently, data D4, data D5,
When data D6,... Are supplied, the operation returns to the operation of the first step, and the same operation as described above is repeated. However, in this case, the data D0 supplied earlier is stored in the first row of the memory array 14 (data memory 14D).
Since the data D3 have already been stored, the data after the data D4 are stored in the second and subsequent rows of the data memory 14D.

According to the above-described method, a parity operation can be performed without performing a so-called read modify write operation during a write operation. The read-modify-write operation is
This is an operation of reading data of one memory cell within the same memory cycle, and further revising and rewriting the data.

After the write operation to the memory array 14 is completed in this way, each of the data D0 to D3 (data D4 and subsequent data) stored in the data memory 14D of the memory array 14 is accessed by, for example, accessing from the B space. If you also store data, that data is also read)
The data is distributed to four HDDs 8 via the HDD I / F controller 7 and recorded. The parity memory 14P
Is also read out at the same time,
HD for parity via HDD I / F controller 7
Recorded in D8. Although not shown, the five HDDs 8 are referred to as HDDs 80 and 8 for convenience of explanation.
1, the HDD 82, the HDD 83, and the HDD 8P, the HDD 80 records, for example, the first column of data from the left side of the data memory 14D, and the HDD 81 stores the data of, for example, the second column from the left side of the data memory 14D. For example, data in the third column from the left of the data memory 14D is recorded in the HDD 83, and data in the parity memory 14P is recorded in the HDD 8P. As described above, the operation of writing data to the disk array device in the case of the second embodiment is completed.

Next, FIG. 4 shows a schematic configuration of a memory device 1 according to a third embodiment of the present invention. 4 having the same functions as those in FIGS. 2 and 3 are denoted by the same reference numerals, and description thereof is omitted.

The memory device 1 according to the third embodiment makes it possible to use an arbitrary part of the memory array 14 as a sub memory array and to set the mapping of the sub memory array. It is characterized in that an arbitrary unit access to the memory array 14 can be converted into an access to a corresponding sub memory array by setting the mapping of the array. That is, in the third embodiment, the sub memory array can be mapped to an arbitrary area in the memory array 14 by setting the mapping of the memory array. Note that the sub memory array may be provided separately from the memory array 14.

FIG. 4 shows an example in which the parity memory 14P is used as a sub memory array. Therefore, a parity memory mapping setting unit 17 is provided as a sub memory array mapping setting means. The unit (sub memory array mapping setting unit) 17 can convert an arbitrary unit access to the memory array 14 into an access to the corresponding parity memory (sub memory array) 14P. The memory access control unit 12 operates based on the settings by the address mapping setting unit 13 and the parity memory mapping setting unit (sub memory array mapping setting unit) 17.

Incidentally, instead of using the parity memory 14P as the sub memory array as described above, an arbitrary area in the data memory 14D can be used as the sub memory array. The example of FIG. 4 shows a case where the data / parity ratio is, for example, 4: 1. The HDDs 8 in this case are four HDDs for data and one HDD for parity data.

The specific operation when the memory device 1 according to the third embodiment is used in a disk array device is as follows. Although not shown, the above five H
DD8 is replaced by HDD80, HDD81, HDD82, HD
When represented as D83 and HDD8P, the HDD 80 records the data of the first column from the left side of the data memory 14D, the HDD 81 stores the data of the second column from the left side of the data memory 14D, and the HDD 82 stores the data of the data column 14D.
, The HDD 8P records data in the parity memory 14P.

Consider a case where data recorded in a disk array composed of these five HDDs 8 (80 to 8P) is read (read).

The data read from the HDDs 8 (80 to 8P) are written to the memory array 14 in the B space access order. Therefore, for example, data read from the HDD 80 is written to the first column from the left of the data memory 14D, and data read from the HDD 81 is read from the HDD 82 to the second column from the left of the data memory 14D. Data stored in data memory 1
The data is written in the third column from the left of 4D.

Here, consider the case where the HDD 81 breaks down, for example. Thus, when the HDD 81 fails, correct data is not written in the second column from the left of the data memory 14D. In this state, if the disk array controller 6 reads the data in the data memory 14D according to the access order of the space A and passes it to the host computer, incorrect data will be transmitted to the host computer.

It is to be noted that some general disk array controllers include a parity when writing data from a plurality of data HDDs to a data buffer memory in order to correct data on the fly. By performing a read-modify-write operation on the buffer memory for parity, even if one HDD fails, the data recorded in the failed HDD is reproduced in the buffer memory for parity. Existing. However, in such a system, the buffer memory for data and the buffer memory for parity are treated as different things, so that complete data cannot be obtained unless the data of the failed HDD is copied to another area once.

On the other hand, in the memory device 1 according to the third embodiment of the present invention, the parity memory (sub memory array) 14P is set by the setting of the parity memory mapping setting section (sub memory array mapping setting section) 17. Can be mapped to a portion of the memory array 14 corresponding to the HDD 81 (failed HDD), so that the setting is performed only once and the memory (sub-memory array) can be accessed in the same manner as in the case where the HDD has not failed. For example, correct data can be read. That is,
Since the contents of the parity memory 14P appear to be mapped to the incorrect data portion of the memory array 14 via the memory access control unit 12, the disk array controller 6 of FIG. 1 performs the same access as when the HDD has not failed. can do.

Next, FIG. 5 shows the above-described first to first embodiments of the present invention.
A rough block configuration in the case where the memory device 1 according to any one of the third embodiments is mounted on an actual circuit board and connected to PCI is shown.

In FIG. 5, an SRAM (static RAM) 46 in the figure corresponds to the data memory 14D of the memory array 14. The SRAMs 44 and 45 correspond to the parity memory 14P.
5 performs a bank operation. Two PLDs (Programmable Logic Devices) connected to the SRAMs 44 and 45, respectively.
e) 42 and 43 are controllers of the parity memory,
A parity arithmetic unit for performing a read-modify-write operation and a RAID assist circuit for accessing the B space are built in. PLD 41 connected to PCI bus
Is a parity calculator that does not involve a read-modify-write operation.
It incorporates a PCII / F circuit connected to the bus and a RAID assist circuit for accessing the A space. PC
The II / F circuit operates at, for example, 64 bits and 33 MHz. As described above, in the memory device 1 according to the embodiment of the present invention, the data memory 14D and the parity memory 1
An SRAM capable of high-speed operation is used for the 4P, and access can be performed without useless latency regardless of the row (row) direction and the column (column) direction of the address.

The memory used in the present embodiment is not limited to the above SRAM, but may be a DRAM, an SDRAM,
It is also possible to use RDRAM or the like.

Next, FIG. 6 shows an example of an address map of the memory device according to the present embodiment.

In FIG. 6, access to the A space and the B space is the same as that described in FIG. In the PLD to be mounted, the size of the memory array 14 and the data / parity ratio are settable parameters.

FIGS. 7 to 10 show an example of mapping of the physical memory (memory array 14), and show how to implement hardware. In this method, the hardware implementation is simple, but the data parity ratio is limited to a power of two.

In the mapping of the memory array 14, mapping is performed so that the row (row) address and the column (column) address shown in FIG. 7 are exchanged, and the mounting of RAID is assisted.

For access from the A space, address allocation is performed in the flow shown by the arrow in FIG. 8, and for access from the B space, the address allocation is performed as shown by the arrow in FIG. Address assignment.

The row (row) address and column (column)
If the bit length of the address is appropriately fixed, an image as shown in FIG. 10 is obtained.

Here, the write access to the A space with the parity calculation involves parity generation by the RAID assist circuit for the A space included in the PLD 41 in FIG. 5, and the write access to the parity memory after writing the data to the data memory. Occurs. Write access to the B space with parity calculation is performed by the PLD shown in FIG.
This involves parity generation by the RAID assist circuit for the B space included in 42 and 43.

The results of the read access to the A space and the A space with parity calculation at the time of the initial setting are equivalent, and the same applies to the B space and the read access to the B space with parity calculation.

Further, by appropriately setting the error address register corresponding to the sub memory array mapping setting unit, the read access to the address specified for the A space with parity calculation and the B space with parity calculation can be performed. Is converted to a read to the corresponding parity memory.

Next, the flow of control during writing and the flow of control during reading in the memory device 1 according to the embodiment of the present invention will be described. FIG. 11 shows a control flow at the time of writing, and FIG. 12 shows a control flow at the time of reading.

Before performing the write operation and the read operation, the disk array controller 6 uses the memory device 1, so that the base address and size of each address space and the unit size and column address which are parameters related to the address conversion are used. And the bit length of the row address.

Here, for convenience of explanation, the A space base address is set to 0x0000 0000, the A space base address with parity calculation is set to 0x1000 0000,
0x2000 0000 for B space base address, 0x3000 for B space base address with parity calculation
0000, parity memory base address is 0x400
0 0000, the memory size is 1 MB, the parity memory size is 256 KB, the unit size is 8 bytes, the column address length is 2 bits, and the row address length is 13 bits.

In the control at the time of writing shown in FIG. 11, first, in step S1, the disk array controller 6 sends the memory array 14 from the address 0x0000 0000 to 256K in the A space with parity calculation.
A data memory 14D of size B is secured and data is written. At the same time, since the column address length is 2 bits, parity data is calculated for every four unit sizes and written to the parity memory 14P.

Thereafter, as step S2, the HDDI /
The F controller 7 has an address 0x2000 in the B space.
Data is read out in block units of 0000 to 64 KB, that is, in stripe unit units, and the data in stripe unit units is written to separate HDDs. Similarly, parity data has an address of 0x4000 0000.
The data is read in units of 64 KB stripe units and written to the HDD for parity data.

As described above, the disk array controller 6 manages the memory array 14 in units of stripe units, and does not need to divide and write data in each memory area, and the HDD I / F controller 7 also has the A space. And the B space are known, so that four data HDDs and one parity HDD are read out from the address in the B space corresponding to the head address of the memory space in the A space with parity calculation in stripe unit units. HDD
It is possible to write data without contradiction.

The read operation may be exactly the reverse of the write operation.

That is, in the control at the time of reading shown in FIG. 12, first, in step S10, the HDD I / F controller 7 converts all data and parity data in units of stripe units to be read into parity data with parity calculation.
Write to the memory array 14 from the space address 0x30000000. At this time, the parity memory 14P stores an exclusive OR of the data blocks read from all HDDs in units of 64 KB stripe units, but does not relate to subsequent operations.

After that, in step S14 when it is determined NO in step S11 described later, the disk array controller 6 reads 256 KB of data from the address 0x1000 0000 in the A space with parity calculation. As described above, the disk array controller 6 only needs to read the single data memory 14D without gathering the memory areas of the distributed memory arrays.

On the other hand, in step S11, it is determined whether or not the HDD is broken. If the HDD has failed in step S11, the process proceeds to step S12.

Here, for example, at the stage where reading from all HDDs is completed in the state where one HDD has failed, A
If the data memory 14D is read by accessing the space, the area of the data to be read from the failed HDD must be incorrect.

Therefore, the disk array controller 6
Determines in step S12 whether or not a value corresponding to the failed HDD has already been set in the error address register. If it has been set, the process proceeds to step S14.
Proceeding to the process of No. 13, the error address register stores the fault H
After setting the value corresponding to DD, the process proceeds to step S14 to read from the A space with parity calculation. Thus, correct data can be obtained by exactly the same operation as in a normal read. Further, the setting to the error address register may be performed only when the failure of the HDD is detected first, and the subsequent access is the same as in the case where there is no failure.

If a failed HDD exists during the write operation, the operation flow is exactly the same as in the normal operation. Eventually HD
The only difference is that the DI / F controller 7 does not perform a write operation on the failed HDD.

In the above description, the mounting method is described in which the number of HDDs is restricted to the power of 2 for simplicity. However, in order to prevent the data parity ratio from being restricted to the power of 2, A more general address translation will be described below.

Here, as a specific example, as shown in FIG. 13, the block size BS of the memory array 14 is set to 48, the data parity ratio is set to 3: 1 (N = 3), and addresses 0 to 50 are accessed. In this case, address calculation is actually performed.

That is, the address calculation in this case is as follows: Base = (Addr / BS) × BS + [Addr / (BS / N)]
% N Offset = Addr% (BS / N) XferAddr = Base + N × Offset The block size BS
Is an integral multiple of N. These parameters are all integers, and the operations performed are all integer operations.

As an address conversion mechanism for realizing the above address calculation, a configuration as shown in FIG. 14 can be considered.

In FIG. 14, the input address
Addr is sent to the arithmetic unit 51. Further, the N value setting register 52 holds the value of N representing the data parity ratio, and the block size setting register 53 holds the block size BS of the memory array 14. The N value from the N value setting register 52 is sent to the arithmetic unit 51 and the N × offset arithmetic unit 56, and the block size setting register 53
Is sent to the arithmetic unit 51.

The computing unit 51 computes a base address Base and an offset Offset using the address Addr, the block size BS, and the N value. The base address Base is sent to the adder 57, and the offset Offset is sent to the N × offset calculator 56.

The N × offset calculator 56 multiplies the offset Offset by the N value and sends the multiplied result of the N × Offset value to the adder 57.

At the adder 57, the base addresses Base and N
Add the value of × Offset. Thereby, the converted address XferAddr is obtained.

FIG. 15 shows a correspondence table between the base address Base generated from the input address Addr, the offset Offset, and the converted address XferAddr by the address calculation in the configuration shown in FIG.

Next, FIG. 16 shows a second configuration example of a system to which the above-described memory device 1 of the present invention is applied. 16 having the same functions as those of FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

In FIG. 16, the disk array controller 3 is connected to a host computer via a PCI bus. Access from the host computer to the memory device 1 is access from the A space.

The HDD I / F controllers 7a to 7c are
Each has the same function as the HDD I / F controller 7 of FIG. 1, and a plurality of HDDs 8a, 8b, 8
c is connected. The access from the HDD I / F controllers 7a to 7c to the memory device 1 is an access from the B space.

Next, FIG. 17 shows a third configuration example of a system to which the memory device 1 according to the embodiment of the present invention is applied. FIG. 17 shows a configuration example in which the memory device 1 of the present embodiment is connected to a plurality of interconnects.
In the configuration example of FIG. 17, the memory device 1 has a configuration substantially similar to that of FIG. Note that FIG.
7, components having the same functions as those of the components in FIGS. 1 and 4 are denoted by the same reference numerals, and description thereof is omitted.

In the configuration of FIG. 17, PCI / Fs 11C and 11H are provided as necessary components when the memory device 1 is connected to a plurality of interconnects. The PCIII / F11C is connected to the PCI bus on the disk array controller 3 side, and the PCIII / F11H is
It is connected to the PCI bus on the DDI / F controller 7 side. Each of the PCII / Fs 11C and 11H includes a data / parity ratio setting block 15, a parity memory mapping setting block 17, and a memory access control unit 1.
2. Connected to the address mapping setting unit 13.

When the memory device 1 is connected to one interconnect as in the configuration examples of FIGS. 1 and 16, for example, the bandwidth of the interconnect is
If the bandwidth is smaller than the bandwidth of the memory device 1, the performance of the memory device 1 cannot be maximized. On the other hand, if the interconnects are divided into a plurality as shown in FIG. 17, the memory device 1 is used effectively. be able to. For example, a high bandwidth R such as a RAM bus DRAM
This is effective when AM is used for the memory array 14.

As described above, according to the memory device of the present embodiment, the same physical memory array 14 is mapped to a plurality of address spaces, and the disk array controller 6
When the HDD I / F controller 7 and the HDD I / F controller 7 use different address spaces, it is possible to reduce the trouble of managing the list of the memory array 14 and the like. Further, when data cannot be read correctly due to a failure of the HDD or the like, The parity memory 14P is mapped to an appropriate area so that an access equivalent to a normal time can be performed.

In the present embodiment, an example in which an HDD array is used has been described. However, the present invention is also applicable to a case in which, for example, a tape drive array having a tape-shaped recording medium is used.

[0110]

As apparent from the above description, in the memory device of the present invention, a memory array which is connected to a single or a plurality of interconnects and is a physical memory is mapped to a plurality of individual address spaces, and By controlling access to the memory array based on the setting of the mapping, it is possible to reduce the trouble of, for example, managing the list of the data buffer memory.

Further, the memory device of the present invention uses a sub memory array which is connected to a single or a plurality of interconnects and is a part of a memory array which is a physical memory or a separate sub memory array, and the memory array is set by setting. Is converted into an access to the corresponding sub-memory array, thereby reducing the trouble of, for example, managing the list of the data buffer memory.

Here, in the memory device of the present invention, the memory array is divided into a data memory and a parity memory and used, and N consecutive unit write operations from one address space are performed based on the ratio of data and parity. The parity is calculated for the access, and after the data is written to the data memory, the parity is written to the parity memory, so that the data cannot be read correctly due to a failure of a recording medium such as an HDD. Even if there is, it is possible to access the parity memory equivalent to the normal time.

The data recording / reproducing apparatus of the present invention includes a memory device of the present invention, a recording medium array control means for controlling a recording medium array comprising a plurality of recording media, a recording medium array and a recording medium array control. The use of a separate address space between the recording medium array interface means and the recording medium array interface means for controlling data transmission / reception between the means can reduce the trouble of, for example, managing a list in a data buffer memory. Therefore, even if data cannot be read correctly due to a failure in the parity memory or the like, it is possible to access the parity memory equivalent to a normal access.

Further, the computer system of the present invention includes the memory device of the present invention and the data recording / reproducing device of the present invention, and the memory device and the data recording / reproducing device are connected via an interconnect. It is possible to reduce the work of managing the list of the data buffer memory and the like, and even if the data cannot be read correctly due to, for example, a failure of the recording medium such as the HDD, access to the parity memory equivalent to the normal access is performed. It is possible to do.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a first configuration example of a system to which a memory device according to an embodiment of the present invention is applied;

FIG. 2 is a block circuit diagram illustrating a schematic configuration of the memory device according to the first embodiment of the present invention;

FIG. 3 is a block circuit diagram illustrating a schematic configuration of a memory device according to a second embodiment of the present invention;

FIG. 4 is a block circuit diagram illustrating a schematic configuration of a memory device according to a third embodiment of the present invention.

FIG. 5 is a block circuit diagram showing a rough configuration in a case where the memory device according to the present embodiment is mounted on an actual circuit board and connected to PCI;

FIG. 6 is a diagram illustrating an example of an address map of the memory device according to the present embodiment;

FIG. 7 is a diagram used to explain a row (row) address and a column (column) address of a memory array.

FIG. 8 is a diagram used to explain mapping of a memory array with respect to access from a space A;

FIG. 9 is a diagram used to explain mapping of a memory array with respect to access from a B space.

FIG. 10 is a diagram used to explain mapping of a memory array when the bit lengths of a row (row) address and a column (column) address are appropriately fixed.

FIG. 11 is a flowchart showing a control flow at the time of writing in the memory device of the present embodiment.

FIG. 12 is a flowchart showing a flow of control at the time of reading in the memory device of the present embodiment.

FIG. 13 is a diagram illustrating an example of a block size of a memory array and a flow of data from an interconnect.

FIG. 14 is a block circuit diagram illustrating a configuration example of an address translation mechanism that implements address calculation for more general address translation.

15 is a diagram showing a correspondence table between a base address Base, an offset Offset, and a converted address XferAddr generated from an input address Addr by the address calculation in the configuration of FIG. 14;

FIG. 16 is a block circuit diagram showing a second configuration example of a system to which the memory device according to the embodiment of the present invention is applied;

FIG. 17 is a block circuit diagram showing a third configuration example of a system to which the memory device according to the embodiment of the present invention is applied;

FIG. 18 is a flowchart of an operation at the time of writing in a conventional RAID-3 disk array device.

FIG. 19 is a flowchart of an operation at the time of reading in a conventional RAID-3 disk array device.

[Explanation of symbols]

1 memory device, 2 CPU, 3 host / PCI
Bridge unit 3, 4 main memory 4, 5 input / output device, 6 disk array controller, 7 HDDI
/ F controller, 8 HDD, 11 interconnect I / F circuit, 12 memory access control unit,
13 address mapping setting unit, 14 memory array, 14D data memory, 14P parity memory, 15 data / parity ratio setting unit, 16 parity operation unit, 17 parity memory mapping setting unit

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] November 12, 1998 (1998.11.
12)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0025

[Correction method] Change

[Correction contents]

Accordingly, the present invention has been made in view of such a situation, and can reduce the trouble of managing the list of the data buffer memory and the like. It is an object of the present invention to provide a memory device capable of performing an equivalent access to a data buffer memory as usual, and a data recording / reproducing device and a computer system using the memory device.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0067

[Correction method] Change

[Correction contents]

On the other hand, in the memory device 1 according to the third embodiment of the present invention, the parity memory (sub memory array) 14P is set by the setting of the parity memory mapping setting section (sub memory array mapping setting section) 17. Can be mapped to a portion of the memory array 14 corresponding to the HDD 81 (failed HDD), so that the setting is performed only once, and the memory (memory array) can be accessed as in the case where the HDD has not failed. It is possible to read correct data. That is, since the contents of the parity memory 14P appear to be mapped to the incorrect data portion of the memory array 14 via the memory access control unit 12, the disk array controller 6 of FIG. Can access.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0112

[Correction method] Change

[Correction contents]

Here, in the memory device of the present invention, the memory array is divided into a data memory and a parity memory and used, and N consecutive unit write operations from one address space are performed based on the ratio of data and parity. The parity is calculated for the access, and after the data is written to the data memory, the parity is written to the parity memory, so that the data cannot be read correctly due to a failure of a recording medium such as an HDD. Even if there is, it is possible to access the data buffer memory equivalent to the normal access.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name]

[Correction method] Change

[Correction contents]

Further, the data recording / reproducing apparatus of the present invention includes a memory device of the present invention, a recording medium array control means for controlling a recording medium array comprising a plurality of recording media, a recording medium array and a recording medium array control. The use of a separate address space between the recording medium array interface means and the recording medium array interface means for controlling data transmission / reception between the means can reduce the trouble of, for example, managing a list in a data buffer memory, and further, for example, a recording medium such as an HDD. Even if the data cannot be read correctly due to a failure in the data buffer, it is possible to access the data buffer memory equivalent to the normal access.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name]

[Correction method] Change

[Correction contents]

Further, the computer system of the present invention includes the memory device of the present invention and the data recording / reproducing device of the present invention, and the memory device and the data recording / reproducing device are connected via an interconnect. It is possible to reduce the trouble of managing the list of the data buffer memory, etc. Further, even if the data cannot be read correctly due to, for example, a failure of the recording medium such as the HDD, the equivalent access to the data buffer memory as usual is performed. It is possible to do.

Claims (15)

[Claims] 1. An interconnect connection means connected to one or a plurality of interconnects; a memory array as a physical memory; a mapping setting means for mapping the memory array to a plurality of individual address spaces; And a memory access control means for controlling access to the memory array based on the memory device. 2. A data / parity ratio setting means for setting a data / parity ratio using the memory array by dividing the data array into a data memory and a parity memory. A parity calculating means for calculating a parity for any continuous N unit write accesses from the address space; and after writing the data to the data memory, write the parity to the parity memory. The memory device according to claim 1, wherein: 3. A sub-memory array mapping setting means which uses the parity memory as a sub-memory array and converts an arbitrary unit access to the memory array by setting the mapping into an access to a corresponding sub-memory array. The memory device according to claim 2, wherein: 4. An interconnect connection means connected to one or a plurality of interconnects, a memory array which is a physical memory, and a setting using a sub memory array which is a part of the memory array or a separate sub memory array. And a sub memory array mapping setting means for converting an arbitrary unit access to the memory array into an access to a corresponding sub memory array. 5. A data / parity ratio setting means for setting a data / parity ratio using the sub memory array as a parity memory, and a data / parity ratio setting means for setting a data / parity ratio from one address space. 5. A parity calculating means for calculating a parity for any continuous N unit write accesses, wherein the parity is write-accessed to the parity memory after writing data. Memory device. 6. A memory means capable of mapping a memory array as a physical memory to a plurality of individual address spaces and controlling access to the memory array based on the setting of the mapping, and a plurality of recording media. A recording medium array, recording medium array control means for controlling the recording medium array, and recording medium array interface means for controlling data transmission and reception between the recording medium array and the recording medium array control means; A data recording / reproducing apparatus, wherein the recording medium array control means and the recording medium array interface means use different address spaces. 7. The memory means uses a memory array by dividing it into a data memory and a parity memory, and performs arbitrary N unit write accesses from one address space based on a ratio of data and parity. 7. The data recording / reproducing apparatus according to claim 6, wherein a parity is calculated for the parity memory, and after the data is written to the data memory, the parity is write-accessed to the parity memory. 8. The memory means, wherein the parity memory is used as a sub-memory array, and an arbitrary unit access to the memory array by setting the mapping is converted into an access to a corresponding sub-memory array. The data recording / reproducing apparatus according to claim 7, wherein 9. A sub memory array which is a part of a memory array as a physical memory or a separate sub memory array is used, and an arbitrary unit access to the memory array is converted into an access to a corresponding sub memory array by setting. Possible memory means, a recording medium array comprising a plurality of recording media, a recording medium array control means for controlling the recording medium array, and controlling data transmission and reception between the recording medium array and the recording medium array control means A data recording / reproducing apparatus, comprising: a recording medium array interface means for performing a recording operation, wherein the recording medium array control means and the recording medium array interface means use different address spaces. 10. The memory means uses the sub-memory array as a parity memory, and generates a parity for any continuous N unit write accesses from one address space based on a data / parity ratio. 10. The data recording / reproducing apparatus according to claim 9, wherein after calculating the data to the data memory, the parity is write-accessed to the parity memory. 11. A memory device for mapping a memory array as a physical memory to a plurality of individual address spaces and controlling access to the memory array based on the setting of the mapping, and a recording medium comprising a plurality of recording media Recording medium array control means for controlling an array, and recording medium array interface means for controlling data transmission and reception between the recording medium array and the recording medium array control means, wherein the recording medium array control means and the recording medium array A computer system comprising: an interface unit and a data recording / reproducing device that uses different address spaces; and the memory unit and the data recording / reproducing device are connected via an interconnect. 12. The memory device according to claim 1, wherein the memory array is divided into a data memory and a parity memory, and is used for an arbitrary number of consecutive unit write accesses from one address space based on a ratio of data and parity. 12. The computer system according to claim 11, wherein a parity is calculated for the parity, and after writing the data to the data memory, the parity is write-accessed to the parity memory. 13. The memory device, wherein the parity memory is used as a sub memory array, and an arbitrary unit access to the memory array by setting the mapping is converted into an access to a corresponding sub memory array. 13. The computer system according to claim 12, wherein 14. A sub memory array which is a part of a memory array which is a physical memory or a separate sub memory array, and an arbitrary unit access to the memory array is converted into an access to a corresponding sub memory array by setting. Possible memory means, recording medium array control means for controlling a recording medium array including a plurality of recording media, and recording medium array interface means for controlling data transmission and reception between the recording medium array and the recording medium array control means Wherein the recording medium array control means and the recording medium array interface means have a data recording / reproducing device using different address spaces, and the memory means and the data recording / reproducing device are connected via an interconnect. A computer system characterized in that: 15. The memory device according to claim 1, wherein the sub memory array is used as a parity memory, and a parity is provided for any continuous N unit write accesses from one address space based on a data / parity ratio. 15. The computer system according to claim 14, wherein is calculated, and after writing the data to the data memory, the parity is write-accessed to the parity memory.