JP2000105698A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microcomputer capable of speeding up the pipeline processing by shortening the delay time required at the time of a hazard occurrence and improving the increasing factor of clock cycle. SOLUTION: Instruction processings are parallelly executed for every pipeline stage of the microcomputer and a hazard processing stage HE is provided between a register fetch stage RF and instruction executing stage EX stored in the pipeline. Therefore, the information holding control of instruction fetch stage IF and executing stage EX can be processed for two cycles of clock from the generation of a hazard signal S241 discriminated on the register fetch stage within one cycle period by a hazard detector 241. Thus, the factor requiring the extension of clock cycle for the configuration of processing in one cycle can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer for performing pipeline processing, and more particularly to a microcomputer which divides an internal circuit in accordance with a processing procedure, adjusts the circuit scale of each circuit, and connects the registers by using pipeline registers. The present invention relates to a pipeline-controlled microcomputer that increases a clock frequency to be supplied and speeds up arithmetic processing.

[0002]

2. Description of the Related Art Although a conventional microcomputer for performing this kind of conventional pipeline processing is generally capable of high-speed operation processing of instructions, recently, instructions decoded for the operation are hard-coded such as information and registers. Means for detecting a hazard condition that occurs when an operation cannot be executed immediately due to a competition of wear resources, for example, and for stopping an operation processing operation of a subsequent instruction and canceling an operation of an instruction that caused a hazard factor. is necessary.

Completing the stop and cancel operations of the pipeline arithmetic processing within one stage from the determination of the hazard condition becomes a critical path on the device because the processing operation becomes complicated. Therefore, it is required to reduce the scale of the logic control that operates within the instruction decoding stage.

[0004] As a technique proposed to meet this demand, for example, one example is described in Japanese Patent Application Laid-Open No. 7-021022. In the arithmetic processing device described in the publication, a stage for instruction decoding and hazard processing execution is divided into a two-stage pipeline, instruction decoding and hazard detection are performed in a first stage pipeline, and a second stage pipeline is used. It has been proposed to perform a control operation of hazard processing for another stage.

Referring to FIG. 8 showing the configuration of the technique used in the prior art, this conventional pipeline arithmetic processing device comprises an instruction fetch stage (IF), a register fetch stage (RF), and an instruction execution stage (RF). EX),
This is a five-stage pipeline configuration including a data fetch stage (DF) and a write-back stage (WB).

In the instruction fetch stage (IF), the IF
A P register 100, an instruction memory 110, an adder 120 for increasing the output of the IFP register 100 by 1, and an adder 1
20 and a selector 130 which receives an output signal of the IFP register 100 and forms a program counter and a holding loop at the time of hazard.

[0007] The register fetch stage (RF)
FP register 200 and processing circuit 2 for inputting its output
10 and an instruction decoder 220, and a selector 230 which receives output signals of the instruction memory 110 and the RFP register 200 and forms a holding loop at the time of hazard.

[0008] The instruction execution stage (EX) includes an EXP register 300, an EXC register 320, and a calculator 310 for calculating the output of the EXP register 300 based on the output of the EXC register 320.

The data fetch stage (DF) has a DF
P register 400, DFC register 420, DFC
A data memory 400 for storing the output of the register 420 based on the output of the DFC register 420.

The write back stage (WB) is a WBP
The register 500 includes a register 500, a WBC register 520, and a register file 510 for filing the output of the WBP register 500 based on the output of the WBC register 520.

Referring to FIG. 9, which shows a transition diagram of a group of instructions executed by the conventional pipeline stage having the above-described configuration at each time, at time t2 during the pipeline operation, the instruction is executed at the register fetch stage (RF). 1 is processed by the processing circuit 210 and also decoded by the instruction decoder 200.

Decoded result and processing circuit 210
Of the instruction 1 proceeds to the instruction execution stage (EX), and at time t3
In the instruction 1, the instruction 1 is read into the EXP register 300,
At the same time, the decoding result of the instruction decoder 200 is also held in the EXC register 320.

According to the information in the EXC register 320,
The instruction 1 of the EXP register 300 is executed by the arithmetic unit 310 to execute a flag operation, memory resource reservation, and the like by arithmetic processing.

Immediately after that, when a branch instruction or the like is issued by the subsequent instruction 2 in the register fetch stage (RF) at the same time t3, the selector 130 selects the instruction 3 according to the decoding result of the instruction 2 and selects the instruction 3 Selects instruction 2 to store instruction 3 in IFP register 10
0, and the instruction 2 in the register fetch stage (RF) is also reserved in the RFP register 200.

At the next time t4, the instruction 1 proceeds to the data fetch stage (DF), and the instruction 2 is held by the loop of the RFP register 200 and the selector 230 in the EXP register 300 and the EXC register 320.
Is read, and the operation is executed.
The pipeline is stopped with the loop held by the P register 100 and the selector 130.

At the next time 5, the instruction 1 proceeds to the write-back stage (WB), the instruction 2 is processed in the instruction execution stage (EX), and the data is fetched (D).
To F), the instruction 3 proceeds to the register fetch stage (RF), and the instruction 4 is fetched to the instruction fetch stage (IF).

That is, the circuit up to the control of holding the instruction fetch stage (IF) and the holding of the REP register of the register fetch stage (RF) within the cycle of time t3, which are performed in the conventional pipeline configuration. Since the operation is involved, the circuit operation time is delayed.

Referring to FIG. 10 showing a transition diagram of a group of pipeline stages in which each instruction executes this operation every time, when the cycle from time t3 to time t4 shifts, the register fetch stage (RF) Instruction 2 is an instruction execution stage (EX) if it is in a normal state due to the occurrence of a hazard.
Information to be stored in the register fetch stage (RF)
And the subsequent instruction 3 passes through the holding loop selected by the selector 100 in response to the decode result signal S220 of the instruction decoder 220 until the time t5 when the execution suspension due to the hazard is released, at the instruction fetch stage (IF). By being held, the arithmetic processing of the instruction 3 at the time t6 can be continued.

At time t4, the instruction 2 stored in the EXP register 300 of the instruction execution stage (EX) is canceled, and then at time t5, the instruction 2 stored in the REP register 200 of the register fetch stage (RF) is canceled. The information is selected as an input to the EXP register 300 and the EXC register 320 of the instruction execution stage (EX), and the operation is executed.

In the procedure of the arithmetic processing after the instruction execution stage (EX), each instruction is executed every cycle.

As a result, the instruction 2 causing the hazard
In FIG. 9, the instruction 2 of the register fetch stage (RF) requiring the hazard processing performs the arithmetic processing in the instruction execution stage (EX) in the next first clock cycle. All of the instructions are processed from the hazard determination.

[0022]

In a conventional microcomputer having the above-described pipeline configuration, when a hazard factor is detected as a result of instruction decoding in the register fetch stage (RF), the microcomputer is operated in the register fetch stage (RF). Of the instruction that caused the hazard is issued, the information of the instruction fetch stage (IF) is retained during the same cycle of the occurrence of the hazard, and the input of the subsequent instruction to the pipeline arithmetic processing unit is suspended. Must be completed during the same cycle of the hazard occurrence.

Also, in the control of the execution cancellation of the instruction stored in the instruction execution stage (EX), it is necessary to complete the control operation during the same cycle period when the hazard occurs.

In this case, as compared with the case where no hazard occurs, the circuit scale operating within one clock cycle is large, and the delay time required for this hazard processing is long in all the operations including the other stages. There is a problem that the delay time limits the operation performance of the entire microcomputer.

It is considered that the use of a method in which the register fetch stage (RF) circuit that operates during the hazard processing is a two-stage pipeline reduces the delay of the circuit that operates within one clock cycle.

However, the instruction issuance to the instruction execution stage (EX) is delayed by one clock, which affects the processing of the branch instruction controlling the operation of the instruction fetch stage (IF) from the instruction execution stage (EX), and is performed for a certain period of time. A problem arises in that the performance of the throughput indicating the number of instructions that can be processed within the device is reduced.

Furthermore, an increase in the number of pipeline stages is caused by an increase in the number of pipeline registers constituting each stage, that is, a control circuit for performing hazard determination at the time of register fetch, and a pipe to each of the two pipeline stages. Since it is necessary to have a line register, the circuit scale of the entire device increases, and as a result, there is a problem that power consumption increases.

An object of the present invention has been made in view of the above-mentioned drawbacks of the related art, and does not affect continuous arithmetic processing, shortens a delay time necessary when a hazard occurs, and improves an increase factor of a clock cycle. Accordingly, it is an object of the present invention to provide a microcomputer that realizes faster pipeline processing.

[0029]

The microcomputer of the present invention is characterized by an instruction fetch stage (IF), a register fetch stage (RF), and an instruction execution stage (E).
X), data fetch stage (DF), write-back stage (WB), input / output information of at least one pipeline stage on the input side or output side of the pipeline stage for performing instruction arithmetic processing, or between pipeline stages Based on a basic configuration of a pipeline having a holding unit for temporarily storing, a pipeline-controlled microcomputer that executes desired instruction processing for each of the pipeline stages in parallel with the other stages. A hazard processing stage (HE) that operates as a part of the pipeline when detecting a factor of a hazard that occurs when an operation cannot be executed.
Is provided between the register fetch stage (RF) and the instruction execution stage (EX).

The instruction fetch stage (IF)
Instruction fetch means for fetching an instruction from a memory device, instruction decode means for decoding the fetched instruction in the register fetch stage (RF), and fetch means for a register provided for data requested by the instruction; Instruction execution stage (E
X) an instruction executing means for executing the decoded instruction, and data for reading or writing data from / to the memory device at an address calculated in the instruction execution stage (EX) in the data fetch stage (DF). Fetch means, and said data fetch stage (DF) in said write back stage (WB)
Write-back means for writing operand data obtained from the memory device or operand data processed in the instruction execution stage (EX) to a register, and the register of the register fetch stage (RF) in the hazard processing stage (HE) Hazard processing means for selecting whether to output the information output by the fetch means to the next stage or to retain the previous state can also be provided.

Further, a combination of an instruction decoded in the register fetch stage (RF) and an instruction previously processed in the instruction execution stage (EX), or an operating condition such as a device resource reservation. A determination is made and the register fetch stage (R
If it is determined that the normal processing of the instruction decoded in F) cannot be guaranteed, the hazard detector that generates a request to maintain the operation state for one clock cycle or more is controlled as a hazard by controlling the pipeline arithmetic processing. It may be provided inside the register fetch stage.

Further, the hazard processing stage (HE) has selection transfer means for holding the information of the register fetch stage (RF) and selectively transferring either the held information or the information. Is also good.

When the hazard does not occur, the selective transfer means outputs an instruction decoder of the register fetch stage (RF) in response to an inactive state of a hazard signal generated by the hazard detector. A first control signal for a pipeline operation holding request in the instruction fetch stage (IF) and the register fetch stage (RF) and an output of a first hazard register storing the signal; A first selector for selecting and transmitting a control signal; and a signal output by the instruction decoder, the signal being output from the instruction execution stage (E).
X) a second selector for selecting and transferring the second control signal from the second control signal for the pipeline operation holding request in X) and the output of the second hazard register storing the signal; Register fetch stage (RF)
And selecting and transferring the data signal among the signals output from the data processing circuit of the third embodiment, the data signal being passed to the pipeline register of the instruction execution stage (EX) and the output of the third hazard register storing the signal. A third selector for each of the hazard processing stages (HE)
You may have inside.

Further, the selective transfer means outputs, when the hazard occurs, an instruction decoder of the register fetch stage (RF) in response to an inactive state of the hazard signal generated by the hazard detector. A first hazard process for a stage control, which is a signal and holds information on a time point when a hazard occurs until the hazard is eliminated as a pipeline operation control signal for the instruction fetch stage (IF) and the register fetch stage (RF). A first selector that selects and propagates an output signal of a register; and a signal output by the instruction decoder, which is a pipeline operation control signal of the instruction execution stage (EX), until the hazard is released. The output signal of the second hazard processing register for controlling the stage that holds the information at the time of occurrence And a second selector for selecting and transmitting the hazard signal as a data signal output from a data processing circuit of the register fetch stage (RF) and passed to a pipeline register of the instruction execution stage (EX). And a third selector that selects and propagates an output signal of a third hazard processing register for retaining data that retains information at the time of occurrence of the hazard until is released.

Further, the first hazard processing register, the second hazard processing register, and the third hazard processing register in the hazard processing stage (HE) respectively hold the signals depending on the activation state of the hazard signal. The number of pipeline stages may be varied by selecting the information after the hazard detection.

The register fetch stage (R
The instruction stored in F) is redundantly stored in the hazard processing stage (HE) and the instruction execution stage (EX) in the next clock cycle. When the hazard is not detected, the hazard processing stage (HE) is executed. ), The first, second and third selectors can all select information on the register fetch stage (RF) side and invalidate the information stored in the hazard processing stage (HE). .

Further, the hazard detector can keep the hazard detection stage (HE) for an arbitrary number of clock cycles until the hazard state is released.

Further, the hazard detector can be provided in the register fetch stage (RF).

In the case where information to be stored in the pipeline register of the instruction execution stage (EX) is selected according to the result of the arithmetic processing in the register fetch stage (RF), after the occurrence of the hazard, the instruction execution stage (EX) executes the hazard execution. As means for transferring instructions of the processing stage (HE), the hazard processing stage (H)
E) a first selector for selecting one of two types of information output from a processing circuit including a register file of the register fetch stage (RF), a control signal from the processing circuit, and storing the control signal. And a second selector for selecting the control signal and the output of the register by a hazard signal and outputting a control signal of the first selector.
And the output of the first selector may be used as the input of the third selector of the hazard processing stage (HE).

Further, when the instruction which causes the hazard is decoded, the occurrence of the hazard is predicted, and the operation of the hazard processing stage (HE) is set as the prediction means. When an instruction that causes the hazard is decoded by the hazard detector, a hazard prediction is performed by the next instruction decode regardless of the presence or absence of the hazard, and the hazard processing stage (HE) is performed in the next clock cycle. The hazard detector may further include a prediction control signal for requesting the first, second, and third registers to hold the information.

Further, when the hazard does not occur, the operation of the hazard processing stage (HE) is stopped by stopping the operation of the hazard processing stage (HE) until the next instruction causing the hazard is decoded and a hazard prediction occurs. The hazard processing can be selectively operated only when an operation is necessary.

[0042]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the outline of the present invention will be described.
A microcomputer according to the present invention executes instruction processing in parallel for each pipeline stage in a microcomputer having a plurality of pipeline stages and processing information, and executes a register fetch stage and an instruction stored in a pipeline. A hazard processing stage is provided between the execution stages.

As will be apparent from the configuration of the microcomputer according to the present invention shown in FIG. 1 to be described later, the present invention is different from the conventional configuration in which the information of the register fetch stage (RF) is transferred to the instruction execution stage (EX). According to the present invention, a selector capable of holding information of the register fetch stage (RF) and selecting the transfer and holding of information is provided in the hazard processing stage (HE).

The hazard detection stage (HE) transfers instructions and information stored in the register fetch stage (RF) to the instruction execution stage (EX) in the next cycle when the hazard does not occur. In the case of a multi-cycle instruction, instruction holding processing including an instruction fetch stage (IF) is executed so that the next instruction is not taken into the pipeline.

When a hazard occurs, the hazard is determined by a hazard operation at the register fetch stage (RF) and a cancel operation for invalidating the information transferred to the instruction execution stage (EX). Complete one cycle.

In the next cycle, conditions such as a hazard operation and a branch instruction in the instruction fetch stage (IF) are determined.

At the time of execution of a multi-cycle instruction and occurrence of a hazard, information to be held in the execution stage is stored in a hazard detection register (HE) located at the input of the instruction execution stage (EX). By supplying from the hazard processing register, a multi-cycle instruction can be executed.

Therefore, within one cycle period, the control of information holding in the instruction fetch stage (IF) and the instruction execution stage (EX) is controlled by the occurrence of the hazard determined in the register fetch stage (IF). Processing can be performed over a period.
This is advantageous in that, when operating at a constant clock cycle, if the processing time of a circuit that becomes a bottle takes longer than the clock cycle, it causes malfunction and normal operation including that circuit is performed. Therefore, it is possible to improve a factor that requires a longer clock cycle in a configuration in which processing is performed in one cycle period, and it is an invention that the pipeline processing of the microcomputer can be speeded up.

Next, embodiments of the present invention will be described in more detail with reference to the drawings. FIG. 1 is a configuration diagram of a main part of a pipeline showing a microcomputer according to a first embodiment of the present invention. Referring to FIG. 1, the microcomputer of the present invention includes an instruction fetch stage (I
F), a pipeline fetch stage (RF), a hazard processing stage (HE), an instruction execution stage (EX), a data fetch stage (DF), and a write back stage (WB).

In the instruction fetch stage (IF), instruction fetch processing is performed, and instruction decoding and branch processing are performed in the register fetch stage (RF).

In FIG. 1, an instruction fetch stage (I
F), the pipeline register 101 (hereinafter, IFP)
Register 101), an instruction memory 111, and an adder 121 which adds one address to the instruction memory 111 every cycle to enable a loop with the IFP register 101 to form a program counter.
And a selector 131 for inputting an output signal of the IFP register 101 and the adder 121.

The register fetch stage (RF) includes a selector 231 and a pipeline register 201 (hereinafter referred to as R).
An FP register 201), a processing circuit (register file) 211, an instruction decoder 221, and a hazard detector 241 that determines the occurrence of a hazard from the decoded signal and the condition of the operation being executed in the pipeline. . It is assumed that this hazard detector detects a hazard in a certain clock cycle and outputs a hazard signal in the next clock cycle.

Further, a register fetch stage (R
A hazard processing stage (HE) newly provided in the present invention is provided next to F).

The hazard processing stage (HE) includes a pipeline register 601 (hereinafter referred to as a HOP register 60).
1), a pipeline register 621 (hereinafter referred to as HE).
C register 621), pipeline register 63
1 (hereinafter referred to as an HRC register 631) and a selector 6
11, 641, 651, and the HOP register 601, the HEC register 621,
The information stored in the HRC register 631 can be selected.

The instruction execution stage (EX) includes a pipeline register 301 (hereinafter referred to as an EXP register 301), a pipeline register 321 (hereinafter referred to as an EXC register 321), and a computing unit 311.
The EXP register 3 is controlled by the register 321.
Using the information of 01, the arithmetic unit 311 performs the arithmetic processing of the instruction.

The data fetch stage (DF) includes a pipeline register 401 (hereinafter, referred to as a DFP register 401).
), Pipeline register 421 (hereinafter referred to as DFC).
A register 421) and a data memory 411, and the information of the DFP register 401 is stored in the data memory 411 under the control of the DFC register 421.

The write back stage (WB) includes a pipeline register 501 (hereinafter, referred to as a WBP register 501), a pipeline register 521 (hereinafter, referred to as a WBC register 521), and a register file 511, and a WBC register 521. Control from WBP
The information of the register 501 is stored in the register file 511.

The operation of the microcomputer having the above configuration in the pipeline control will be described.

Referring to FIG. 1 again, the case where no hazard is detected will be described. In the following description, a code assigned to a signal line (for example, S221 assigned to an output line of the instruction decoder 221) is used as a signal name. Similarly to the arithmetic processing in the conventional pipeline, the instruction fetched into the IFP register 101 in the instruction fetch stage (IF) is stored in the instruction memory 111,
In the next cycle, the data is stored in the RFP register 201 of the register fetch stage (RF) via the selector 231.

The instruction S201 stored in the RFP register 201 is decoded by the instruction decoder 221 in the register fetch stage (RF), and the decoding result S
The presence / absence of a hazard is determined by the hazard detector 241 based on the H.221.

As a result of the determination, when the occurrence of a hazard is not detected and no request for holding an instruction in a multi-cycle is generated, the hazard detection signal S241 of the detection result is obtained.
Is deactivated, and the selectors 611, 641, 651 of the hazard processing stage (HE) are responded to this signal S241.
Selects information S211, S221, and S221 transferred from the register fetch stage (RF), respectively.

According to this selection, the pipeline of the register fetch stage (RF) sets the information S2 in the next cycle.
11, S221 is HO of hazard processing stage (HE)
At the same time as storing in the P register 601, the HEC register 621, and the HRC register 631, the selectors 611 and 641
The information S211 and S221 selected in step 3 are stored in the EXP register 301 and the EXC register 3 of the instruction execution stage (EX).
21 is also stored.

Therefore, the register fetch stage (R
The instruction stored in the instruction processing stage (E) is stored in the hazard processing stage (HE) and the instruction execution stage (E) in the next cycle.
X) is stored in duplicate.

However, under the condition that the hazard is not determined, the selector 611 of the hazard processing stage (HE),
641 and 651 select the information S211, S221, and S221 on the register fetch stage (RF) side as inputs, so that the HOP register 601, HEC register 621, and HRC of the hazard processing stage (HE) are selected.
The information stored in the register 631 becomes invalid.

The information stored in the instruction execution stage (EX) is controlled according to the instruction, and the information subjected to the arithmetic processing is
The processing is transmitted to the data fetch stage (DF) and the write back stage (WB) after the next cycle as necessary.

As a result, when the occurrence of a hazard is not detected, the arithmetic processing in the pipeline is executed in the same cycle as in the conventional circuit.

Next, the operation when the occurrence of a hazard is detected will be described. Referring to FIG. 2 showing a transition diagram of a group of instructions executed by each pipeline stage at each time when the occurrence of a hazard is detected, the register fetch is performed at time t2 during the pipeline operation. Instruction 1 is decoded at the stage (RF). The decoded instruction 1 is selected by the selectors 611 and 641 and proceeds to the instruction execution stage (EX) at time t3
At the same time, execution of a flag operation, securing of memory resources, and the like are performed by the arithmetic processing of the instruction execution stage (EX).

Immediately after that, when a branch instruction or the like is issued by the subsequent instruction 2 in the register fetch stage (RF) at the same time t3, a hazard detection signal S241 is output at the next time t4, and the instruction 2 To HOP register 601, HEC register 621, HRC
The instruction 2 is secured in the register 631, and at the same time, the instruction 2 is secured in the EXP register 301 and the EXC register 321.

On the other hand, in response to the hazard detection signal S241, the instruction 4 and the instruction 3 are executed by the selector 131 and the holding loop of the IFP register 101 and the holding loop of the selector 231 and the RFP register 201, respectively.
The instruction 4 is held in the register 101 and the RFP register 201, the instruction 4 is held in the IFP register 101, and the instruction 3 is held in the RFP register 201, and the pipeline stops.

At time t5, HOP register 601
And the instruction 2 secured in the HEC register 621 at the previous time cancels and rewrites the instruction 2 in the EXP register and the EXC register 321 via the selectors 611 and 641, and also replaces the instruction 3 held in the RFP register 201 with the HOP. The decoding result of the instruction 3 is secured in the register 601 and the HEC register 621 and the HRC register 631, respectively.

Since the instruction 3 decoded by the instruction decoder 221 at time t4 does not include a branch instruction or the like, the pipeline stop hazard detection signal S241 becomes inactive at time t5, so the IFP register 101 at time t6. And the instruction 4 are secured in the RFP register 201, respectively. At the same time, RFP at time t5
The instruction 3 held in the register 201 becomes H at time t6.
The OP register 601 and the EXP register 301 are secured, and the instruction 3 output of the instruction decoder 221 is also H
The arithmetic unit 311 is secured in the EC register 621 and the EXC register 321, and the arithmetic unit 311 executes an arithmetic operation using the information in the EXP register 301 under the control of the EXC register 321.

As described above, the hazard operation in the register fetch stage (RF) and the cancellation process for the information of the instruction 2 stored in the instruction execution stage (EX) at the time t4 are executed in the same cycle. The operation within one cycle period ends.

That is, the circuit operation up to the instruction fetch stage (IF) holding control and the register fetch stage (RF) REP register holding control in the cycle of the time t3 performed in the conventional pipeline configuration is performed. The circuit operation time is shortened by the absence.

FIG. 3 shows a transition diagram of a group of pipeline stages in which each instruction executes this operation at every time. Referring to FIG. 3, when the cycle from time t3 to time t4 shifts, the register fetch stage (RF) The instruction 2 saves information to be stored in the normal instruction execution stage (EX) to the hazard processing stage (HE) by detecting a hazard, and stores the subsequent instruction 3 from the instruction fetch stage (IF) to the register fetch stage (RF). Is done.

Until time t5 when the execution suspension due to the hazard is released, the control signal S631 of the instruction 3 selected in response to S241 activated by the hazard detection is selected, and the RFP register 201 is selected by the signal S651 of the selection result. Is stored in the register fetch stage (RF) through the holding loop selected by the selector 231, so that the arithmetic processing of the instruction 3 can be continued.

At time t4, the instruction 2 stored in the register 301 of the instruction execution stage (EX) is canceled, and thereafter, the instruction 2 stored in the HOP register 601 of the hazard processing stage (HE) at time t5.
Is selected as an input to the instruction execution stage (EX).

As for the procedure of the arithmetic processing after the instruction execution stage (EX), each instruction is executed every cycle as in the conventional pipeline configuration.

As a result, the instruction 2 that caused the hazard
Focusing on, by implementing a variable-length pipeline configuration in which the number of stages in the pipeline is increased by one in preparation for an increase in arithmetic processing, a function of dividing arithmetic processing within a stage during one cycle period can be realized. .

That is, in FIG. 2, the instruction 2 of the register fetch stage (RF) requiring the hazard processing is stored in the hazard processing stage (HE) in the next first clock cycle, and the instruction execution stage in the next second clock cycle. In order to perform the arithmetic processing in (EX), the processing amount is doubled even if the processing contents are the same, as compared with the conventional method of performing all of the instruction arithmetic processing from the hazard determination within one clock cycle. It can be distributed within each clock cycle.

As described above, according to the present invention,
Under normal conditions, the instruction fetch stage (I
F), a hazard factor is determined based on a basic configuration in which instruction arithmetic processing is performed in the order of a register fetch stage (RF), an instruction execution stage (EX), a data fetch stage (DF), and a write-back stage (WB). In this case, a variable length pipeline configuration is provided by having a hazard processing stage (HE) functioning as a part of the pipeline.

As a result, it is possible to improve the delay increase factor in one cycle period by dividing the operation causing the delay time increase in one cycle period into the operation process in two cycles. And a pipeline-controlled microprocessor realizing improved performance by accelerating arithmetic processing.

It should be noted that the present invention is not limited to the above-described embodiments, and that each embodiment can be appropriately modified within the scope of the technical idea of the present invention.

Therefore, as compared with the case where no hazard occurs, the circuit scale operating within one clock cycle is divided into two stages of pipelines, and the hazard processing is performed in all operations including other stages. It is possible to eliminate the problem that the required delay time is long and the delay time limits the operation performance of the entire microcomputer.

Further, in this embodiment, a hazard processing stage (HE) that operates only during this hazard processing is provided.
The instruction execution stage (EX) when the register fetch stage (RF) is simply pipelined into two stages without affecting the delay of a circuit operating within one clock cycle other than when a hazard occurs. It is also possible to avoid the performance degradation that delays the issue of the instruction to one clock.

As a result, it does not affect the processing of the branch instruction controlling the operation from the instruction execution stage (EX) to the instruction fetch stage (IF). Therefore, there is no problem that the performance of throughput as a measure indicating the number of instructions that can be processed within a certain time is reduced.

Further, since the number of pipeline stages for performing the pipeline operation processing does not increase except in the case of hazard processing, an increase in power consumption can be avoided by adding a prediction function of hazard detection. become.

As another embodiment of the present invention, the basic configuration is as described above, but input of information stored in the HOP register, HEC register, and HRC register of the hazard processing stage (HE) under a hazard condition is performed. The selection control is further devised.

Referring to FIG. 4 showing the configuration of the second embodiment, the difference from the pipeline configuration shown in FIG. 1 is that a hazard processing stage (HE) is used.
, An HCP register 662 for storing a control signal S212 by the processing circuit 212, and control signals S212 and H
A selector 682 that selects the output of the CP register 662 in response to the hazard detection signal S242 of the hazard detector 242, and outputs the selected signal as a selection signal S682.
And the processing circuit 21 of the register fetch stage (RF)
And a selector 672 for selecting one of the two sets of information consisting of the two outputs RFDATA1 and RFDATA2 in response to the selection signal S682. The output of the selector 672 is the output of the hazard processing stage (HE). HO
That is, a configuration for inputting to the P register 602 is provided.

As described above, the result of the arithmetic processing in the register fetch stage (RF) is the instruction execution stage (E
X) is stored in the EXP register 302.
Depending on the content of the instruction, E in the instruction execution stage (EX)
The information to be stored in the XP register 302 must be selected and stored according to the result of the arithmetic processing in the register fetch stage (RF), and the selection function may be required.

In this case, after the occurrence of the hazard, the instruction execution stage (EX) needs to transfer the instruction of the hazard processing stage (HE), and the selector 672 selects the processing circuit 212 of the register fetch stage (RF) before the occurrence of the hazard.
Processing stage (H
E) Based on the condition of the HCP register 662, the HOP
The input of the register 602 is used as the output RFDA of the processing circuit 212.
It is possible to select from TA1 and RFDATA2.

Referring to FIGS. 5 and 4 showing timing charts for explaining the operation at this time, the hazard factor is detected at time T2, the hazard detection signal S242 outputs a high level, and the two circuits of the processing circuit 212 Output is RF
DATA1 (X0, X1, X2, ‥‥‥) and RFD
ATA2 (Y0, Y1, Y2,...), An output signal S212 outputs a signal for selecting the state value of RFDATA1 until time t0, t1, and at time T2, the state value changes to RFDATA1. The signal for selecting the state value of is output.

At time t2 when the hazard occurs, the selector 682 selects the output of the HCP register 662.
This register stores the processing circuit 21 at the immediately preceding time t1.
The state value of the selection signal S212, which is two outputs, is held. In FIG. 4, despite the change at S212t2 and the change from RFDATA1 to RFDATA2 selection,
662 indicates that the state of the previous RFDATA1 is held until t3.

Therefore, until the end of the time t2, the selector 6
HEDATA1 which is the output of 72 outputs the status values X0, X1, X2,.
2 and subsequent values are Y3, Y4, and Y, which are the status values of RFDATA2.
5, ‥‥‥ is output.

HED which is the output of the HOP register 602
Since ATA2 outputs the previous state value at the next clock, the state value of RFDATA1 shifts by one clock and outputs X0, X1, X2,.
Thereafter, Y3, Y4, Y, which are the status values of RFDATA2,
5, ‥‥‥ is output.

The EXDATA input, which is the input to the EXP register 302 of the instruction execution stage (EX), is at the times t0, t
Up to 1, X0 and X1 are selected by a basic selection route, and at time t2, a hazard factor is detected.
X1 held in the OP register 602 is selected, and time t
From 3 onward, the hazard is released again, and the process returns to the basic selection route, and Y3, Y4Y5,... Of HEDATA2 are selected and input based on the signal S662.

Therefore, the selection signal S212 changes at time t2.
HCP register 6
It is possible to store the state value to be selected under the condition of the time t1 held in the HOP register, the HEC register, and the HRC register of the hazard processing stage (HE).

As a result, the register fetch stage (R
Even in a pipeline control device configured to transfer information from F) to the pipeline register of the instruction execution stage (EX) via the selector, the information held in the hazard processing stage (HE) under the hazard condition is correct. The processing circuit output signal of the register fetch stage (RF) can be selected.

That is, the RF stage control signal RFDA
This is because, when TA1 or RFDATA2 is selected and output to the EX stage, if the state of the selection signal is not held in the HE stage when a hazard occurs, the contents of the pipeline register HOP register 602 in the HE stage will be incorrect. .

In this method, when there are a plurality of systems to be transferred from the register fetch stage (RF) to the instruction execution stage (EX), and the system of the information to be transferred is selected from among them according to the state of the information itself, A pipeline register for holding all the selection information therein is provided in the hazard processing stage (HE), and the delay of the determination operation at the time of the hazard processing is reduced as compared with the case where the determination of the information selection state is performed again. be able to. Here, the re-execution of the state determination means that when a hazard occurs, the instruction once calculated in the EX stage must be canceled, and the instruction needs to be executed again after the next clock cycle. The operation content such as is the instruction at that time.

Further, in addition to the advantage that the delay of the judgment operation at the time of the hazard processing described above can be reduced, the output signal from the register fetch stage (RF) can be held by holding the selection signal and the selected signal, respectively. It is not necessary to hold all of them, and the amount of information to be held can be reduced. Therefore, it is advantageous for miniaturization and low power consumption of the microcomputer as compared with the case where all the information of the register fetch stage (RF) is held in the hazard processing stage (HE).

In the above-described embodiment, the operation and effect that the delay of the judgment operation at the time of the hazard processing of the microcomputer can be reduced is reduced by the register fetch stage (RF).
If there is a plurality of systems to be transferred to an instruction execution stage (EX) from among them, and a system of information to be transferred is selected from the plurality of systems according to the state of the information itself, a pipeline register for holding the selected information among the systems Is provided in the selector circuit of the hazard processing stage (HE).

On the other hand, since the occurrence of a hazard occurs in the continuous processing of a specific instruction, the occurrence of the hazard is predicted when the instruction which causes the hazard is decoded, and the operation of the hazard processing stage is set (technique). Thought) can also be obtained.

A configuration for this is shown as a third embodiment. Referring to FIG. 6, which shows a configuration diagram of a microcomputer according to a third embodiment of the present invention, the difference from the first embodiment described above is that the hazard detector 243 detects the time t
Hazard prediction signal S243B is newly generated during periods 3 and t4, and in response to this signal, HOP register 603 holds the output of processing circuit 213 and HEC register 623
, The decoding result of the instruction decoder 223 is held, and the decoding result of the instruction decoder 223 is also held in the HPC register 633. That is,
The above-mentioned three registers are used for hazard prediction signal S243B.
The holding operation is performed.

Referring to FIG. 7, which shows a transition diagram of a group of instructions executed by the pipeline stage every time for explaining the operation of the present embodiment, instruction 1 at time t1, instruction 2 at time t2, and time t3 Command 3 at time t4, command 4 at time t4
It is assumed that the instructions 5 are sequentially fetched in the instruction fetch stage (IF).

The H level of the hazard processing stage (HE)
The OP register 603, the HEC register 623, and the HRC register 633 are normally set to a stopped state by masking the clock, and when the hazard prediction signal is output, the mask is released and the instruction is stored in the register at the next clock. And

At time t2, instruction 1 is set to instruction decoder 2
23, and a hazard prediction signal S243 is generated from the decoding result.
At the next time t3, the hazard prediction signal S243 is output, and at the next time t4, the hazard prediction signal S24
In response to No. 3, information reading of the HOP register 603, the HEC register 623, and the HRC register 633 is performed.

Further, in response to the hazard detection signal S243 detected at time t4, the information of the instruction 2 is output from the HOP register 603, HEC register 623, HRC register 633 of the hazard processing stage (HE) to the selector 60.
3, 623, 633 and output to the instruction fetch stage (IF) and register fetch stage (RF) selectors 133 and 233, respectively, and the EXP register 603 and EXC of the instruction execution stage (EX).
It is also output to the register 303.

At the time t5, immediately after the instruction 2 read into the EXP register performs the operations such as the flag operation and the reservation of the memory resource by the arithmetic processing, the same time t5
3, when a branch instruction or the like is issued by the subsequent instruction 3 in the register fetch stage (RF), the hazard operation in the register fetch stage (RF) and the instruction 2 stored in the instruction execution stage (EX) at time t4
Is executed within the same cycle, and the operation within one cycle period ends.

As described above, in this microcomputer, when an instruction that causes a hazard is decoded by the hazard detector 243 of the register fetch stage (RF), whether or not a hazard has occurred in the next instruction decode result is determined. In the next cycle, the HOP register 603, the HEC register 623, and the HRC register 63 of the hazard processing stage (HE) are predicted.
3 has a function of making a request to hold information.

Therefore, the processing when a hazard is actually detected in the next cycle is the same as that in each of the above-described embodiments. However, when no hazard is generated, the instruction that causes the next hazard is decoded. Then, by stopping the operation of the hazard processing stage (HE) until the hazard prediction is generated, the operation and effect of reducing the delay of the judgment operation at the time of the hazard processing can be obtained, and the object of the present invention is achieved. Is done.

Further, in this embodiment, the hazard processing stage is operated only when the pipeline operation is required, so that it is more advantageous to reduce the power consumption of the microcomputer than in the case where the hazard processing stage (HE) is always operated. It has a synergistic effect.

[0112]

As described above, according to the present invention, under normal conditions, the instruction fetch stage (IF), the register fetch stage (RF), the instruction execution stage (EX), and the data fetch stage (D) are performed as in the conventional case.
F), based on a basic configuration in which instructions are processed in the order of the write-back stage (WB), functioning as a part of the pipeline in the next stage of the register fetch stage (RF) when a hazard factor is determined Conventionally, by employing a variable-length pipeline configuration having a hazard processing stage (HE), an operation that causes an increase in delay time within one cycle period is divided into two cycles to perform arithmetic processing. A pipeline-controlled microprocessor is provided, which can improve a factor that increases a delay in a cycle period and realizes performance improvement by speeding up arithmetic processing.

Therefore, as compared with the case where no hazard occurs, the circuit scale operating within one clock cycle is divided into two stages of pipelines, and this hazard processing is performed in all the operations including other stages. The problem that the delay time required for the microcomputer is long and the delay time limits the operation performance of the entire microcomputer can be eliminated.

By using the hazard processing stage (HE) that operates only during the hazard processing, the delay of the circuit that operates within one clock cycle other than when the hazard occurs is not affected, and the register fetch stage (HE) is not affected. (RF) is simply pipelined into two stages, so that it is possible to avoid a decrease in performance that delays instruction issuance to the instruction execution stage (EX) by one clock, and from the instruction execution stage (EX) to the instruction fetch stage (IF). Since this does not affect the processing of the branch instruction for controlling the operation of (1), the problem of lowering the throughput performance indicating the number of instructions that can be processed within a fixed time does not occur.

Further, since the number of pipeline stages that operate in the pipeline operation processing does not increase except in the case of hazard processing, an increase in power consumption can be avoided by adding a prediction function for hazard detection. There is also an effect.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of a pipeline of a microcomputer of the present invention.

FIG. 2 is a transition diagram of an instruction group executed by each pipeline stage of the first embodiment at each time.

FIG. 3 is a transition diagram of a group of pipeline stages that each instruction of the first embodiment executes every time.

FIG. 4 is a configuration diagram showing a second embodiment.

FIG. 5 is a timing chart for explaining the operation of the second embodiment.

FIG. 6 is a configuration diagram illustrating a third embodiment.

FIG. 7 is a transition diagram of a group of instructions executed by the pipeline stage of the third embodiment every time.

FIG. 8 is a configuration diagram showing a pipeline of a conventional microcomputer.

FIG. 9 is a transition diagram of a group of instructions executed by the conventional pipeline stage every time.

FIG. 10 is a transition diagram of a group of instructions executed by the conventional pipeline stage every time.

[Explanation of symbols]

 101 IFP register 111 Instruction memory 121 Adder 131, 231, 611, 641, 651 Selector 201 RFP register 211 Processing circuit 221 Instruction decoder 241 Hazard detector 301 EXP register 311 Operation unit 321 EXC register 401 DFP register 411 Data memory 421 DFC Register 501 WBP register 511 Register file 521 WBC register 601 HOP register 621 HEC register 631 HRC register DF Data fetch stage EX Instruction execution stage HE hazard processing stage IF Instruction fetch stage RF register fetch stage WB Write back stage

Claims (13)

[Claims] 1. An instruction fetch stage (IF), a register fetch stage (RF), and an instruction execution stage (E).
X), data fetch stage (DF), write-back stage (WB), input / output information of at least one pipeline stage on the input side or output side of the pipeline stage for performing instruction arithmetic processing, or between pipeline stages Based on a basic configuration of a pipeline having a holding unit for temporarily storing, a pipeline-controlled microcomputer that executes desired instruction processing for each of the pipeline stages in parallel with the other stages. A hazard processing stage (HE) that operates as a part of the pipeline when detecting a factor of a hazard that occurs when an operation cannot be executed.
Is provided between the register fetch stage (RF) and the instruction execution stage (EX). 2. An instruction fetch unit for fetching an instruction from a memory device in the instruction fetch stage (IF), an instruction decoding unit for decoding the fetched instruction in the register fetch stage (RF), and a request from the instruction. Fetch means for a register provided for data; instruction execution means for executing the decoded instruction in the instruction execution stage (EX); and operation performed in the instruction execution stage (EX) in the data fetch ratio (DF). A data fetch means for reading or writing data to or from the memory device at a given address; and a write-back stage (WB).
A write-back means for writing operand data obtained from the memory device in the data fetch stage (DF) or operand data processed in the instruction execution stage (EX) to a register, and the register in the hazard processing stage (HE). 2. A microcomputer according to claim 1, further comprising: hazard processing means for selecting whether to output the information output by said register fetch means of a fetch stage (RF) to a next stage or to retain a previous state. . 3. The register fetch stage (RF)
In the register fetch stage (RF), the combination of the instruction decoded in step (1) and the instruction that has been previously processed in the instruction execution stage (EX) or the operating condition by securing the resources of the device is determined. If it is determined that the normal processing of the decoded instruction cannot be guaranteed, the hazard detector that issues a request to hold the operation state for one clock cycle or more is controlled by the register fetch. 3. The microcomputer according to claim 2, wherein the microcomputer is provided inside the stage. 4. The hazard processing stage (HE)
3. The microcomputer according to claim 2, further comprising a selection transfer unit that holds information of the register fetch stage (RF) and selectively transfers either the held information or the information. 5. An instruction decoder of the register fetch stage (RF) outputs the selective transfer means in response to an inactive state of a hazard signal generated by the hazard detector when the hazard does not occur. A first control signal for a pipeline operation holding request in the instruction fetch stage (IF) and the register fetch stage (RF) and an output of a first hazard register storing the signal; A first selector for selecting and transferring a control signal; a second control signal for a pipeline operation holding request in the instruction execution stage (EX), which is a signal output by the instruction decoder; and a signal for storing the second control signal. A second selector for selecting and transferring the second control signal from the output of the second hazard register to be activated, A data signal which is output from a data processing circuit of a data fetch stage (RF) and which is passed to a pipeline register of the instruction execution stage (EX) and an output of a third hazard register which stores the signal; 5. The microcomputer according to claim 4, further comprising: a third selector for selecting and transferring the data in the hazard processing stage (HE). 6. The selective transfer means outputs an instruction decoder of the register fetch stage (RF) in response to an inactive state of a hazard signal generated by the hazard detector when the hazard occurs. A first hazard process for a stage control, which is a signal and holds information on a time point when a hazard occurs until the hazard is eliminated as a pipeline operation control signal for the instruction fetch stage (IF) and the register fetch stage (RF). A first selector for selecting and transmitting the output signal of the register;
A signal output from the instruction decoder, which is a pipeline operation control signal of the instruction execution stage (EX),
A second selector for selecting and propagating an output signal of a second hazard processing register for stage control which holds information on the time of occurrence of the hazard until the hazard is released, and data of the register fetch stage (RF) A third hazard process for retaining data, which is a signal output from the processing circuit and is a data signal to be passed to a pipeline register of the instruction execution stage (EX), and retains information on a point when the hazard occurs until the hazard is released. 5. The microcomputer according to claim 4, further comprising a third selector for selecting and transmitting an output signal of the register. 7. The first hazard processing register, the second hazard processing register, and the third hazard processing register in the hazard processing stage (HE) according to an active state of the hazard signal, respectively. 7. The microcomputer according to claim 6, wherein the number of pipeline stages is varied by selecting information after detecting the hazard. 8. The register fetch stage (RF)
Is stored in the hazard processing stage (HE) and the instruction execution stage (EX) in the next clock cycle, and when the hazard is not detected, the instruction is stored in the hazard processing stage (HE). 7. The method according to claim 6, wherein each of the first, second, and third selectors selects information on a register fetch stage (RF) side, and invalidates information stored in a hazard processing stage (HE). Microcomputer. 9. The hazard detector holds the hazard detection stage (HE) for an arbitrary number of clock cycles until the hazard state is released.
The microcomputer as described. 10. The microcomputer according to claim 3, wherein the hazard detector is provided in the register fetch stage (RF). 11. When information to be stored in a pipeline register of the instruction execution stage (EX) is selected based on a result of an arithmetic processing in a register fetch stage (RF), the instruction execution stage (E) is executed after the occurrence of the hazard.
X) is a means for transferring an instruction of the hazard processing stage (HE) as one of two systems of information output from a processing circuit including a register file of the register fetch stage (RF) in the hazard processing stage (HE). , A control signal by the processing circuit, a register for storing the control signal, and a control of the first selector by selecting the control signal and the output of the register by a hazard signal. 6. The microcomputer according to claim 5, further comprising a second selector that outputs a signal, wherein an output of the first selector is an input of the third selector of the hazard processing stage (HE). 12. A predicting means for predicting the occurrence of a hazard when an instruction causing the occurrence of the hazard is decoded, and setting the operation of the hazard processing stage (HE) as the prediction means. When an instruction that causes the hazard is decoded in the hazard detector, the next instruction decode performs a hazard prediction regardless of whether or not the hazard has occurred,
In the next clock cycle, the hazard processing stage (H
The microcomputer according to claim 5, wherein the hazard detector further includes a prediction control signal for requesting the first, second, and third registers of (E) to hold the information. 13. When there is no occurrence of the hazard,
The operation of the hazard processing stage (HE) is stopped until the next instruction that causes the hazard is decoded and a hazard prediction occurs, and the hazard processing is selectively operated only when pipeline operation is necessary. The microcomputer according to claim 12.