JP2000188389A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2000188389A JP2000188389A JP10365839A JP36583998A JP2000188389A JP 2000188389 A JP2000188389 A JP 2000188389A JP 10365839 A JP10365839 A JP 10365839A JP 36583998 A JP36583998 A JP 36583998A JP 2000188389 A JP2000188389 A JP 2000188389A
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- Prior art keywords
- concentration
- type semiconductor
- semiconductor region
- low
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Thyristors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
(57)【要約】
【課題】 サイリスタ構造を有する保護回路において、
スイッチング電圧を変えずに、ホールディング電圧の低
減を図る。
【解決手段】 サイリスタのアノード部とカソード部に
挟まれた、Ｎ型半導体領域、もしくはＰ型半導体領域に
相当する、第１の低濃度Ｎ型半導体領域と第１の低濃度
Ｐ型半導体領域の間に、第１の低濃度Ｎ型半導体領域よ
りも不純物濃度の低い、第２の低濃度Ｎ型半導体領域も
しくは基板領域を形成する、あるいは、第１の低濃度Ｐ
型半導体領域よりも不純物濃度の低い、第２の低濃度Ｐ
型半導体領域もしくは基板領域を形成し、ホールディン
グ電圧を低下させる。この構成により、外部から加わっ
た電荷（電圧）は、より低い電圧まで放電され、内部の
ＩＣやＬＳＩ回路に対して外部電荷（電圧）の影響が小
さくすることが可能となる。
(57) [Summary] In a protection circuit having a thyristor structure,
To reduce the holding voltage without changing the switching voltage. SOLUTION: A first low-concentration N-type semiconductor region and a first low-concentration P-type semiconductor region corresponding to an N-type semiconductor region or a P-type semiconductor region sandwiched between an anode portion and a cathode portion of a thyristor. In between, a second low-concentration N-type semiconductor region or a substrate region having an impurity concentration lower than that of the first low-concentration N-type semiconductor region is formed, or the first low-concentration N-type semiconductor region is formed.
Low-concentration P having a lower impurity concentration than the p-type semiconductor region
Forming a semiconductor region or a substrate region to lower the holding voltage. With this configuration, an externally applied charge (voltage) is discharged to a lower voltage, and the influence of the external charge (voltage) on an internal IC or LSI circuit can be reduced.
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＭＩＳ型半導体装
置のゲート酸化膜を過大電圧から保護するための静電保
護装置と、その製造方法に関するものであり、特にＣＭ
ＯＳプロセス等で作製する場合に、静電保護のために半
導体基板上に形成されるサイリスタの特性改善を目的と
するものである。[0001] 1. Field of the Invention [0002] The present invention relates to an electrostatic protection device for protecting a gate oxide film of an MIS type semiconductor device from excessive voltage, and a method of manufacturing the same.
The purpose of the present invention is to improve the characteristics of a thyristor formed on a semiconductor substrate for protection from static electricity when it is manufactured by an OS process or the like.
【０００２】[0002]
【従来の技術】半導体装置は年々微細化されており、そ
れに伴い、外部からの望まない静電破壊（Ｅｌｅｃｔｒ
ｏ Ｓｔａｔｉｃ Ｄｉｓｃｈａｒｇｅｓ：ＥＳＤ）に
対する、保護装置を半導体回路の入出力部に組み込むの
が、一般的になっている。また、それらの保護装置の特
性も、保護すべき対象となる半導体装置の微細化に応じ
た、適切な特性を必要とされている。2. Description of the Related Art Semiconductor devices are miniaturized year by year, and accordingly, unwanted electrostatic discharge (Electr
It is common to incorporate a protection device against static discharges (ESD) into an input / output unit of a semiconductor circuit. Also, the characteristics of these protection devices are required to have appropriate characteristics in accordance with the miniaturization of the semiconductor device to be protected.
【０００３】これら保護装置として、ＭＯＳ型半導体装
置のプロセスにおいては、サイリスタとよばれる半導体
装置がよく用いられる。サイリスタはＰＮ接合を２つ以
上含む半導体装置で、典型的には、Ｐ−Ｎ−Ｐ−Ｎの構
造をもち、一方の端部となるＰ型半導体をアノード、も
う一方の端部のＮ型半導体をカソードと呼んでいる。こ
のようなサイリスタにおける従来構造と製造方法を、Ｐ
型シリコン基板に作製する場合を例にとり、図１１の
（ａ）から（ｆ）に従って説明する。In the process of a MOS semiconductor device, a semiconductor device called a thyristor is often used as a protection device. A thyristor is a semiconductor device including two or more PN junctions, and typically has a P-N-P-N structure. A P-type semiconductor at one end is an anode, and an N-type at the other end. The semiconductor is called a cathode. The conventional structure and manufacturing method of such a thyristor are described by P
11A to 11F will be described with reference to FIGS.
【０００４】まず、図１１（ａ）に示すように、Ｐ型シ
リコン基板１に、基板面にフォトレジストを塗布し、素
子分離領域を形成する部分のレジストを取り除き、シリ
コン基板をエッチング後、酸化物埋め込みを行い、その
後、化学的機械的研磨（ＣＭＰ）を実施し、素子分離領
域２を形成する。First, as shown in FIG. 11A, a photoresist is applied to the surface of a P-type silicon substrate 1 to remove the resist in a portion where an element isolation region is to be formed. An object is buried, and thereafter, chemical mechanical polishing (CMP) is performed to form an element isolation region 2.
【０００５】次に、図１１（ｂ）に示すように、フォト
レジストを塗布し、低濃度Ｎ型半導体領域を形成する部
分のレジストを除去し、Ｎ型不純物を低濃度にイオン注
入して低濃度Ｎ型半導体領域４を形成する。その後、再
度フォトレジストを塗布し、低濃度Ｐ型半導体領域を形
成する部分のレジストを除去しした後、Ｐ型不純物を低
濃度にイオン注入し、低濃度Ｐ型半導体領域３を形成す
る。[0005] Next, as shown in FIG. 11 (b), a photoresist is applied, a portion of the resist where a low-concentration N-type semiconductor region is to be formed is removed, and N-type impurities are ion-implanted at a low concentration. A concentration N-type semiconductor region 4 is formed. After that, a photoresist is applied again to remove the resist in a portion where the low-concentration P-type semiconductor region is to be formed. Then, a low-concentration P-type semiconductor region 3 is formed by ion-implanting a P-type impurity at a low concentration.
【０００６】続いて、図１１（ｃ）に示すように、フォ
トレジスト５を塗布し、低濃度Ｎ型半導体領域上の一部
と、低濃度Ｐ型半導体領域上の一部を開口し、Ｐ型不純
物を基板表面に対して、ほぼ垂直方向から、高濃度にイ
オン注入を行い、高濃度Ｐ型半導体領域６、７を形成す
る。Subsequently, as shown in FIG. 11C, a photoresist 5 is applied to open a part on the low-concentration N-type semiconductor region and a part on the low-concentration P-type semiconductor region. High-concentration P-type semiconductor regions 6 and 7 are formed by performing high-concentration ion implantation of a type impurity from a direction substantially perpendicular to the substrate surface.
【０００７】次に、図１１（ｄ）に示すように、レジス
トを除去後、再びフォトレジスト８を塗布し、低濃度Ｎ
型半導体領域上の一部と、低濃度Ｐ型半導体領域上の一
部を開口し、Ｎ型不純物を基板表面に対して、ほぼ垂直
方向から、高濃度にイオン注入を行い、高濃度Ｎ型半導
体領域９、１０を形成する。Next, as shown in FIG. 11D, after removing the resist, a photoresist 8 is applied again, and the low concentration N
A portion of the upper portion of the semiconductor region and a portion of the lower concentration P-type semiconductor region are opened, and an N-type impurity is ion-implanted at a high concentration in a direction substantially perpendicular to the surface of the substrate. Semiconductor regions 9 and 10 are formed.
【０００８】次に、図１１（ｅ）に示すように、熱処理
により、図１１（ｃ）及び（ｄ）で示す工程で注入した
不純物を活性化する。その後、図１１（ｆ）に示すよう
に、高濃度Ｎ型半導体領域と高濃度Ｐ型半導体領域の各
領域に、コンタクトを形成し、金属配線１１、１２、１
３等で、電源、グラウンド、もしくは入出力端子のいず
れかに、電気的に接続する。Next, as shown in FIG. 11E, the impurities implanted in the steps shown in FIGS. 11C and 11D are activated by heat treatment. Thereafter, as shown in FIG. 11F, contacts are formed in each of the high-concentration N-type semiconductor region and the high-concentration P-type semiconductor region, and the metal wirings 11, 12, and 1 are formed.
At 3, etc., it is electrically connected to any of a power supply, a ground, and an input / output terminal.
【０００９】以上のような工程により作製された従来技
術の構造では、基板に低濃度Ｎ型半導体領域、及び、低
濃度Ｐ型半導体領域が形成されており、低濃度Ｎ型半導
体領域と低濃度Ｐ型半導体領域は接しており、かつ、低
濃度Ｎ型半導体領域には、高濃度Ｎ型半導体領域１０
と、アノード部を形成する高濃度Ｐ型半導体領域７が存
在する。一方、低濃度Ｐ型半導体領域には、高濃度Ｐ型
半導体領域１１と、カソード部を形成する高濃度Ｎ型半
導体領域９が存在する。このような従来技術の構造を有
するサイリスタにおいて、オン状態における抵抗は図６
（サイリスタの等価回路）に示すように、低濃度Ｐ型半
導体領域３に形成された、高濃度Ｎ型半導体領域９（カ
ソード部）と低濃度Ｎ型半導体領域４の間に存在する、
低濃度Ｐ型半導体領域の不純物濃度、及び、低濃度Ｎ型
半導体領域４に形成された、高濃度Ｐ型半導体領域７
（アノード部）と低濃度Ｐ型半導体領域の間に存在す
る、低濃度Ｎ型半導体領域の不純物濃度に大きく依存す
る。以上の説明は、Ｐ型基板にサイリスタを作製する場
合であるが、Ｎ型基板に作製する場合も、プロセス的に
は、全く同様である。In the prior art structure manufactured by the above-described steps, a low-concentration N-type semiconductor region and a low-concentration P-type semiconductor region are formed on a substrate. The P-type semiconductor region is in contact, and the low-concentration N-type semiconductor region is
And a high-concentration P-type semiconductor region 7 forming an anode portion. On the other hand, in the low-concentration P-type semiconductor region, there are a high-concentration P-type semiconductor region 11 and a high-concentration N-type semiconductor region 9 forming a cathode portion. In the thyristor having such a conventional structure, the resistance in the ON state is as shown in FIG.
As shown in (equivalent circuit of the thyristor), there exists between the high-concentration N-type semiconductor region 9 (cathode portion) and the low-concentration N-type semiconductor region 4 formed in the low-concentration P-type semiconductor region 3.
The impurity concentration of the low-concentration P-type semiconductor region and the high-concentration P-type semiconductor region 7 formed in the low-concentration N-type semiconductor region 4
It largely depends on the impurity concentration of the low-concentration N-type semiconductor region existing between the (anode portion) and the low-concentration P-type semiconductor region. Although the above description is for the case where a thyristor is manufactured on a P-type substrate, the case of manufacturing a thyristor on an N-type substrate is completely the same in terms of process.
【００１０】[0010]
【発明が解決しようとする課題】サイリスタの特性は、
一般的に図５に示すような電流ー電圧特性を示す。ここ
で示された特性に於いて、ホールディング電圧は、静電
保護素子としての重要な値となる。サイリスタをＭＯＳ
型半導体の保護素子として用いる場合、高電界がかかっ
た場合に、サイリスタを介して電荷を逃がすことになる
が、このホールディング電圧が、保護したいＭＯＳ型半
導体素子のゲート酸化膜の耐圧より低いことが求められ
る。この酸化膜の耐圧は、プロセスの微細化に伴い、ま
すます低下しており、サイリスタのホールディング電圧
（オン電圧）を低くすることが求められている。The characteristics of the thyristor are as follows.
Generally, it shows current-voltage characteristics as shown in FIG. In the characteristics shown here, the holding voltage is an important value as an electrostatic protection element. Thyristor is MOS
When used as a protection element for a type semiconductor, when a high electric field is applied, charges are released through a thyristor. However, this holding voltage must be lower than the withstand voltage of the gate oxide film of the MOS type semiconductor element to be protected. Desired. The breakdown voltage of this oxide film has been increasingly reduced with the miniaturization of the process, and it is required to lower the holding voltage (on-voltage) of the thyristor.
【００１１】そのためサイリスタのホールディング電圧
（オン電圧）を低くするには、図６に示した等価回路の
バイポーラトランジスタのオン電圧をどちらか一方、あ
るいは両方のオン電圧を低くすればよく、この為にはベ
ース領域、つまりアノード部とカソード部の間に存在す
る低濃度Ｎ型半導体領域もしくは低濃度Ｐ型半導体領域
の不純物濃度を低くすればよい。しかしながら、上述し
たような従来構造のサイリスタの構造では、低濃度Ｎ型
半導体領域、もしくは低濃度Ｐ型半導体領域の不純物濃
度を低下させると、図６のＲｓｐおよびＲｓｎで示した
抵抗値も変化させてしまい、結果的にスイッチング電圧
を低下させてしまうという問題がある。即ち、サイリス
タのスイッチング電圧（図５参照）は、これらの抵抗Ｒ
ｓｐおよびＲｓｎに依存しており、また、スイッチング
電圧も、保護すべきプロセスに応じて適切に定める必要
があるために、従属的に変更されるのは望ましくない。Therefore, in order to lower the holding voltage (ON voltage) of the thyristor, one or both of the ON voltages of the bipolar transistors of the equivalent circuit shown in FIG. 6 may be reduced. The impurity concentration of the low concentration N-type semiconductor region or the low concentration P-type semiconductor region existing between the anode region and the cathode region may be reduced. However, in the structure of the thyristor having the conventional structure as described above, when the impurity concentration of the low-concentration N-type semiconductor region or the low-concentration P-type semiconductor region is reduced, the resistance values indicated by Rsp and Rsn in FIG. As a result, there is a problem that the switching voltage is reduced. That is, the switching voltage of the thyristor (see FIG. 5) is controlled by these resistors R
It depends on sp and Rsn, and it is not desirable that the switching voltage be changed in a dependent manner because the switching voltage needs to be appropriately determined according to the process to be protected.
【００１２】本発明の目的は、ＣＭＯＳプロセスを用い
てつくられ、ＭＯＳ型半導体の保護素子として用いられ
る、サイリスタのホールディング電圧が、プロセスに合
った適切な値を持つようにし、静電保護素子として有効
に機能させることにある。An object of the present invention is to make a holding voltage of a thyristor, which is formed by using a CMOS process and is used as a protection device of a MOS type semiconductor, have an appropriate value suitable for a process, and is effective as an electrostatic protection device. Function.
【００１３】[0013]
【課題を解決するための手段】上記問題を解決するため
に、請求項１に記載の発明は、Ｐ型半導体基板に低濃度
Ｎ型半導体領域、及び、低濃度Ｐ型半導体領域が形成さ
れ、前記低濃度Ｎ型半導体領域と前記低濃度Ｐ型半導体
領域に挟まれてＰ型半導体基板領域が存在し、かつ、前
記低濃度Ｎ型半導体領域には、高濃度Ｎ型半導体領域
と、アノード部を形成する高濃度Ｐ型半導体領域が存在
し、一方、前記低濃度Ｐ型半導体領域には、高濃度Ｐ型
半導体領域が存在すると共に、前記低濃度Ｐ型半導体領
域と基板領域の両領域に接するように、カソード部を形
成する高濃度Ｎ型半導体領域が存在することを特徴とす
るものである。According to a first aspect of the present invention, a low-concentration N-type semiconductor region and a low-concentration P-type semiconductor region are formed on a P-type semiconductor substrate. A P-type semiconductor substrate region exists between the low-concentration N-type semiconductor region and the low-concentration P-type semiconductor region, and the low-concentration N-type semiconductor region includes a high-concentration N-type semiconductor region and an anode portion. There is a high-concentration P-type semiconductor region that forms the following. On the other hand, in the low-concentration P-type semiconductor region, a high-concentration P-type semiconductor region exists, and in both the low-concentration P-type semiconductor region and the substrate region. A high-concentration N-type semiconductor region forming the cathode portion is provided so as to be in contact therewith.
【００１４】また、請求項２に記載の発明は、請求項１
に記載のＰ型半導体基板の代わりにＮ型半導体基板に適
用したことを特徴とするものである。[0014] The invention described in claim 2 is the first invention.
Wherein the present invention is applied to an N-type semiconductor substrate instead of the P-type semiconductor substrate described in (1).
【００１５】また、請求項３に記載の発明は、基板表面
に第１の低濃度Ｎ型半導体領域、及び、第１の低濃度Ｐ
型半導体領域が形成され、前記第１の低濃度Ｎ型半導体
領域と前記第１の低濃度Ｐ型半導体領域に挟まれ、前記
第１の低濃度Ｐ型半導体領域よりも不純物濃度が低い、
第２の低濃度Ｐ型半導体領域が存在し、かつ、前記第１
の低濃度Ｎ型半導体領域には、高濃度Ｎ型半導体領域
と、アノード部を形成する高濃度Ｐ型半導体領域が存在
し、一方、前記第１の低濃度Ｐ型半導体領域には、高濃
度Ｐ型半導体領域が存在すると共に、前記第１の低濃度
Ｐ型半導体領域と前記第２の低濃度Ｐ型半導体領域の両
領域に接するように、カソード部を形成する高濃度Ｎ型
半導体領域が存在することを特徴とするものである。According to a third aspect of the present invention, the first low-concentration N-type semiconductor region and the first low-concentration P-type semiconductor region are formed on the substrate surface.
Type semiconductor region is formed and sandwiched between the first low-concentration N-type semiconductor region and the first low-concentration P-type semiconductor region, and has an impurity concentration lower than that of the first low-concentration P-type semiconductor region.
A second low-concentration P-type semiconductor region exists;
In the low-concentration N-type semiconductor region, there is a high-concentration N-type semiconductor region and a high-concentration P-type semiconductor region forming an anode portion. On the other hand, in the first low-concentration P-type semiconductor region, A high-concentration N-type semiconductor region forming a cathode portion is provided so that a P-type semiconductor region is present and both the first low-concentration P-type semiconductor region and the second low-concentration P-type semiconductor region are in contact with each other. It is characterized by being present.
【００１６】また、請求項４に記載の発明は、基板表面
に第１の低濃度Ｎ型半導体領域、及び、第１の低濃度Ｐ
型半導体領域が形成され、前記第１の低濃度Ｎ型半導体
領域と前記第１の低濃度Ｐ型半導体領域に挟まれ、前記
第１の低濃度Ｎ型半導体領域よりも、不純物濃度が低
い、第２の低濃度Ｎ型半導体領域が存在し、かつ、前記
低濃度Ｐ型半導体領域には、高濃度Ｐ型半導体領域と、
カソード部を形成する高濃度Ｎ型半導体領域が存在し、
一方、前記第１の低濃度Ｎ型半導体領域には、高濃度Ｎ
型半導体領域が存在すると共に、前記第１のＮ型半導体
領域と前記第２のＮ型半導体領域の両領域に接するよう
に、アノード部を形成する高濃度Ｐ型半導体領域が存在
することを特徴とするものである。According to a fourth aspect of the present invention, a first low-concentration N-type semiconductor region and a first low-concentration P-type semiconductor region are formed on the substrate surface.
Type semiconductor region is formed and sandwiched between the first low-concentration N-type semiconductor region and the first low-concentration P-type semiconductor region, and has an impurity concentration lower than that of the first low-concentration N-type semiconductor region. A second low-concentration N-type semiconductor region exists, and the low-concentration P-type semiconductor region includes a high-concentration P-type semiconductor region;
There is a high-concentration N-type semiconductor region forming a cathode portion,
On the other hand, the first low-concentration N-type semiconductor region has a high-concentration N-type semiconductor region.
And a high-concentration P-type semiconductor region forming an anode portion so as to be in contact with both the first N-type semiconductor region and the second N-type semiconductor region. It is assumed that.
【００１７】また、請求項５に記載の発明は、Ｐ型半導
体基板表面に素子分離領域を形成する部分をエッチ後、
絶縁物を埋め込み、平坦化のためのＣＭＰ処理をして素
子分離領域を形成する工程と、低濃度Ｎ型半導体領域を
形成する部分を開口し、Ｎ型不純物を低濃度にイオン注
入し低濃度Ｎ型半導体領域を形成し、続いて前記Ｎ型半
導体領域と所定の距離を離しＰ型半導体基板領域が存在
するように、低濃度Ｐ型半導体領域を形成する部分を開
口し、Ｐ型不純物を低濃度にイオン注入し、低濃度Ｐ型
半導体領域を形成する工程と、前記低濃度Ｎ型半導体領
域上の一部と、前記低濃度Ｐ型半導体領域上の一部を開
口し、Ｐ型不純物を高濃度にイオン注入し、高濃度Ｐ型
半導体領域を形成する工程と、前記低濃度Ｎ型半導体領
域上の一部と、前記低濃度Ｐ型半導体領域と前記Ｐ型半
導体基板領域の接面上の一部を開口し、Ｎ型不純物を高
濃度にイオン注入を行い、高濃度Ｎ型半導体領域を形成
する工程と、熱処理により、注入した不純物を活性化さ
せる工程と、前記高濃度Ｎ型半導体領域と前記高濃度Ｐ
型半導体領域の各領域に、コンタクトを形成し、金属配
線等で、電源、グラウンド、もしくは入出力端子のいず
れかに、電気的に接続する工程とを含むことを特徴とす
るものである。According to a fifth aspect of the present invention, after a portion for forming an element isolation region on the surface of a P-type semiconductor substrate is etched,
A step of burying an insulator and performing a CMP process for planarization to form an element isolation region; opening a portion where a low-concentration N-type semiconductor region is to be formed; An N-type semiconductor region is formed, and a portion where a low-concentration P-type semiconductor region is formed is opened so that a P-type semiconductor substrate region exists at a predetermined distance from the N-type semiconductor region. Forming a low-concentration P-type semiconductor region by ion-implanting at a low concentration; opening a portion on the low-concentration N-type semiconductor region and a portion on the low-concentration P-type semiconductor region; Forming a high-concentration P-type semiconductor region by ion-implanting a high-concentration P-type semiconductor region, a portion on the low-concentration N-type semiconductor region, and a contact surface between the low-concentration P-type semiconductor region and the P-type semiconductor substrate region. Open the upper part and ion implant N-type impurities at high concentration Performed, forming a high-concentration N-type semiconductor region, by heat treatment, a step of activating the implanted impurities, the heavily doped P and the high-concentration N-type semiconductor region
Forming a contact in each region of the mold semiconductor region, and electrically connecting to a power supply, a ground, or an input / output terminal with a metal wiring or the like.
【００１８】また、請求項６に記載の発明は、請求項５
に記載のＰ型半導体基板の代わりにＮ型半導体基板に適
用したことを特徴とするものである。The invention described in claim 6 is the same as the invention in claim 5
Wherein the present invention is applied to an N-type semiconductor substrate instead of the P-type semiconductor substrate described in (1).
【００１９】また、請求項７に記載の発明は、基板表面
に素子分離領域を形成する部分をエッチ後、絶縁物を埋
め込み、平坦化のためのＣＭＰ処理をして素子分離領域
を形成する工程と、低濃度Ｎ型半導体領域を開口し、Ｎ
型不純物を低濃度にイオン注入を行い、第１の低濃度Ｎ
型半導体領域を形成し、続いて前記第１の低濃度Ｎ型半
導体領域と所定の距離を離し、低濃度Ｐ型半導体領域を
開口し、Ｐ型不純物を低濃度にイオン注入を行い、第１
の低濃度Ｐ型半導体領域を形成し、次いで、前記第１の
低濃度Ｎ型半導体領域と前記第１の低濃度Ｐ型半導体領
域に挟まれた領域を開口し、前記第１の低濃度Ｐ型半導
体領域より低濃度のＰ型不純物をイオン注入して、第２
の低濃度Ｐ型半導体領域を形成する工程と、前記第１の
低濃度Ｐ型半導体領域と前記第２の低濃度Ｐ型半導体領
域の接面上の一部と、低濃度Ｎ型半導体領域上の一部を
開口し、Ｐ型不純物を高濃度にイオン注入を行い、高濃
度Ｐ型半導体領域を形成する工程と、前記第１の低濃度
Ｐ型半導体領域上の一部と、前記第１の低濃度Ｎ型半導
体領域上の一部を開口し、Ｎ型不純物を高濃度にイオン
注入を行い、高濃度Ｎ型半導体領域を形成する工程と、
熱処理により、注入した不純物を活性化する工程と、前
記高濃度Ｎ型半導体領域と前記高濃度Ｐ型半導体領域の
各領域に、コンタクトを形成し、金属配線等で、電源、
グラウンド、もしくは入出力端子のいずれかに、電気的
に接続する工程とを含むことを特徴とするものである。According to a seventh aspect of the present invention, there is provided a method of forming a device isolation region by etching a portion for forming a device isolation region on a substrate surface, burying an insulator, and performing a CMP process for planarization. And opening a low concentration N-type semiconductor region,
Ion is implanted at a low concentration to form a first low concentration N
Forming a low-concentration P-type semiconductor region, separating the first low-concentration N-type semiconductor region by a predetermined distance, opening a low-concentration P-type semiconductor region, and ion-implanting a P-type impurity at a low concentration;
Is formed, and then a region between the first low-concentration N-type semiconductor region and the first low-concentration P-type semiconductor region is opened to form the first low-concentration P-type semiconductor region. Ion implantation of a P-type impurity at a lower concentration than the
Forming a low-concentration P-type semiconductor region, a portion on a contact surface between the first low-concentration P-type semiconductor region and the second low-concentration P-type semiconductor region, and a portion on the low-concentration N-type semiconductor region. Forming a high-concentration P-type semiconductor region by ion-implanting a P-type impurity at a high concentration, forming a portion on the first low-concentration P-type semiconductor region; Forming a high-concentration N-type semiconductor region by opening a part of the low-concentration N-type semiconductor region and ion-implanting N-type impurities at a high concentration;
Activating the implanted impurities by heat treatment; forming contacts in each of the high-concentration N-type semiconductor region and the high-concentration P-type semiconductor region;
Electrically connecting to either the ground or the input / output terminal.
【００２０】また、請求項８に記載の発明は、請求項７
に記載の第２の低濃度Ｐ型半導体領域の代わりに、第２
の低濃度Ｎ型半導体領域を形成することを特徴とするも
のである。結果として、請求項１と請求項５、あるい
は、請求項２と請求項６によれば、サイリスタのオン状
態におけるホールディング電圧は、従来技術に比べ、低
濃度Ｎ型半導体領域もしくは低濃度Ｐ型半導体領域より
も、不純物濃度が低いＮ型もしくはＰ型半導体基板領域
が存在しているために、より低いホールディング電圧と
なる。かつ、この場合、工程の追加を必要としない。ま
た請求項３、請求項７によれば、サイリスタのオン状態
におけるホールディング電圧は、第１の低濃度Ｐ型半導
体領域よりも不純物濃度の低い、第２の低濃度Ｐ型半導
体領域が存在しており、従来技術に比べ、ホールディン
グ電圧は低下する。また、請求項４、請求項８によれ
ば、サイリスタのオン状態におけるホールディング電圧
は、第１の低濃度Ｎ型半導体領域よりも不純物濃度の低
い、第２の低濃度Ｎ型半導体領域が存在しており、従来
技術に比べ、ホールディング電圧は低下する。上記の請
求項のいずれにおいても、低濃度Ｎ型半導体領域中に形
成された、高濃度Ｎ型半導体領域、及び、低濃度Ｐ型半
導体領域中に形成された高濃度Ｐ型半導体領域は、従来
技術と同等の不純物濃度の領域を抵抗領域として、サイ
リスタを形成するために、ホールディング電圧以外の電
気特性、特にスイッチング電圧に影響を及ぼさない。The invention described in claim 8 is the same as the invention described in claim 7.
In place of the second low-concentration P-type semiconductor region described in
In which a low-concentration N-type semiconductor region is formed. As a result, according to claim 1 and claim 5, or claim 2 and claim 6, the holding voltage in the ON state of the thyristor is lower than that of the prior art in the lightly doped N-type semiconductor region or lightly doped P-type semiconductor. Since an N-type or P-type semiconductor substrate region having a lower impurity concentration than the region exists, the holding voltage becomes lower. In this case, no additional steps are required. According to the third and seventh aspects, the holding voltage in the ON state of the thyristor is such that the second low-concentration P-type semiconductor region having an impurity concentration lower than that of the first low-concentration P-type semiconductor region exists. As a result, the holding voltage is lower than that of the related art. According to the fourth and eighth aspects, the holding voltage in the ON state of the thyristor is such that the second low-concentration N-type semiconductor region has a lower impurity concentration than the first low-concentration N-type semiconductor region. Therefore, the holding voltage is lower than that of the related art. In any of the above claims, the high-concentration N-type semiconductor region formed in the low-concentration N-type semiconductor region and the high-concentration P-type semiconductor region formed in the low-concentration P-type semiconductor region may be a conventional one. Since a thyristor is formed using a region having an impurity concentration equivalent to that of the technology as a resistance region, it does not affect electric characteristics other than the holding voltage, particularly, the switching voltage.
【００２１】[0021]
【発明の実施の形態】以下、実施の形態に基づいて、本
発明について詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments.
【００２２】Ｐ型シリコン基板に作製する場合を例にと
り、本発明の構造と製造方法を、図１に従って説明す
る。The structure and manufacturing method of the present invention will be described with reference to FIGS.
【００２３】まず、図１（ａ）に示すように、Ｐ型シリ
コン基板（不純物濃度〜２．０×１０15／ｃｍ3）１４
に、基板面にフォトレジストを塗布し、パターニングに
より、素子分離領域を形成する部分のレジストを取り除
く。続いて、シリコン基板をエッチングし、酸化物埋め
込みを行い、化学的機械的研磨（ＣＭＰ）処理を実施
し、素子分離領域１５を形成する。First, as shown in FIG. 1A, a P-type silicon substrate (impurity concentration: 2.0 × 10 15 / cm 3 ) 14
Then, a photoresist is applied to the substrate surface, and the resist in a portion where an element isolation region is to be formed is removed by patterning. Subsequently, the silicon substrate is etched, an oxide is buried, and a chemical mechanical polishing (CMP) process is performed to form an element isolation region 15.
【００２４】次に、図１（ｂ）に示すように、再度、フ
ォトレジストを塗布し、パターニングにより、低濃度Ｎ
型半導体領域を形成する部分のレジストを除去し、続い
て、リン（31Ｐ+）等のＮ型不純物を低濃度にイオン注
入し、低濃度Ｎ型半導体領域（不純物濃度〜５．０×１
０17／ｃｍ3）１７を形成する。その後、フォトレジス
トを除去し、再びフォトレジストを塗布して、低濃度Ｐ
型半導体領域を形成する部分のレジストを除去し、ボロ
ン（11Ｂ+）等のＰ型不純物を低濃度にイオン注入し、
低濃度Ｐ型半導体領域（不純物濃度〜２．０×１０17／
ｃｍ3）１６を形成する。Next, as shown in FIG. 1B, a photoresist is applied again and patterned to form a low-density N
The resist in the portion where the type semiconductor region is to be formed is removed, and then an N-type impurity such as phosphorus ( 31 P + ) is ion-implanted at a low concentration to obtain a low-concentration N-type semiconductor region (impurity concentration of about 5.0 × 1).
0 17 / cm 3 ) 17 is formed. After that, the photoresist is removed, the photoresist is applied again, and the low concentration P
Type resist is removed in portions forming the semiconductor region, a P-type impurity such as boron (11 B +) is ion-implanted at a low concentration,
Low-concentration P-type semiconductor region (impurity concentration: 2.0 × 10 17 /
cm 3 ) 16 are formed.
【００２５】次に、図１（ｃ）に示すように、フォトレ
ジスト１８を塗布し、パターニングにより低濃度Ｎ型半
導体領域上の一部と、低濃度Ｐ型半導体領域上の一部を
開口し、ボロン（ＢＦ2+）等のＰ型不純物を基板表面に
対して、ほぼ垂直方向から、高濃度に（〜２．０×１０
15／ｃｍ2、４０ｋｅＶ）イオン注入を行い、高濃度Ｐ
＋半導体領域１９、２０を形成する。ここで領域２０は
サイリスタのアノードとなる領域である。Next, as shown in FIG. 1C, a photoresist 18 is applied, and a part of the low concentration N-type semiconductor region and a part of the low concentration P-type semiconductor region are opened by patterning. P-type impurities such as boron (BF 2+ ) at a high concentration (up to 2.0 × 10
15 / cm 2 , 40 keV) ion implantation is performed,
+ Semiconductor regions 19 and 20 are formed. Here, the region 20 is a region to be the anode of the thyristor.
【００２６】次に、図１（ｄ）に示すように、フォトレ
ジストを除去後、再び塗布し、パターニングにより低濃
度Ｎ型半導体領域上の一部と、低濃度Ｐ型半導体領域と
基板領域の接面上の一部を開口し、ヒ素（75Ａｓ+）等
のＮ型不純物を基板表面に対して、ほぼ垂直方向から、
高濃度に（〜３．０×１０15／ｃｍ2、５０ｋｅＶ）イ
オン注入を行い、高濃度Ｎ型半導体領域２２、２３を形
成する。ここで領域２２はサイリスタのカソードとなる
領域である。Next, as shown in FIG. 1D, after the photoresist is removed, the photoresist is applied again, and a portion on the low-concentration N-type semiconductor region and a portion of the low-concentration P-type semiconductor region and the substrate region are formed by patterning. opening a portion of the contact surface, the arsenic (75 As +) N-type impurity such as with respect to the substrate surface, a substantially vertical direction,
High-concentration (up to 3.0 × 10 15 / cm 2 , 50 keV) ions are implanted to form high-concentration N-type semiconductor regions 22 and 23. Here, the region 22 is a region serving as a cathode of the thyristor.
【００２７】次に、図１（ｅ）に示すように、熱処理に
より、図１（ｃ）及び（ｄ）に示す工程で注入した不純
物を活性化する。その後、図１（ｆ）に示すように、高
濃度Ｎ型半導体領域と高濃度Ｐ型半導体領域の各領域
に、コンタクトを形成し、金属配線等２４、２５、２６
で、電源、グラウンド、もしくは入出力端子のいずれか
に、電気的に接続する。Next, as shown in FIG. 1E, the impurities implanted in the steps shown in FIGS. 1C and 1D are activated by heat treatment. Thereafter, as shown in FIG. 1F, contacts are formed in each of the high-concentration N-type semiconductor region and the high-concentration P-type semiconductor region, and metal wirings 24, 25, and 26 are formed.
Then, it is electrically connected to a power supply, a ground, or an input / output terminal.
【００２８】以上の工程で作製すると、低濃度Ｎ型半導
体領域と低濃度Ｐ型半導体領域の間に、低濃度Ｐ型半導
体基板が存在するため、オン状態の時のホールディング
電圧が低くなる。本構造によるホールディング電圧の低
減の効果を図９、図１０を用いて説明する。図９は従来
構造による電流電圧特性を示し、図１０は本発明による
電流ー電圧特性を示す。この例では、ホールディング電
圧が約１Ｖ程度低くなっており、一方スイッチング電圧
は従来例と比較してほとんど変化がない。また図２は前
述した図１のＰ型半導体基板に代えて、Ｎ型半導体基板
を用いて形成された、本発明の別の実施例である。この
場合においても、図１と同等の効果がある。In the above process, since the low-concentration P-type semiconductor substrate exists between the low-concentration N-type semiconductor region and the low-concentration P-type semiconductor region, the holding voltage in the ON state is reduced. The effect of reducing the holding voltage by this structure will be described with reference to FIGS. FIG. 9 shows a current-voltage characteristic according to a conventional structure, and FIG. 10 shows a current-voltage characteristic according to the present invention. In this example, the holding voltage is lower by about 1 V, while the switching voltage hardly changes compared to the conventional example. FIG. 2 shows another embodiment of the present invention in which an N-type semiconductor substrate is used instead of the above-described P-type semiconductor substrate of FIG. Also in this case, there is an effect equivalent to that of FIG.
【００２９】また、図３、図４は本発明による、半導体
装置の別の実施例である。図３では、第１の低濃度Ｎ型
半導体領域４２と第１低濃度Ｐ型半導体領域４０の間
に、第２のＰ型半導体領域４１が存在する。また、図４
では、第１の低濃度Ｐ型半導体領域５２と第１の低濃度
Ｎ型半導体領域５３の間に、第２のＮ型半導体領域５４
が存在する。これら図３と図４に示した実施例では、第
２の低濃度Ｐ型半導体領域、もしくは、第２の低濃度Ｎ
型半導体領域が存在し、この領域の不純物濃度を調整す
ることにより、ホールディング電圧を調整することがで
きる。言い換えれば図３、図４のほうが図１、図２の構
造に比較し、ホールディング電圧をより最適化すること
が可能となる。FIGS. 3 and 4 show another embodiment of the semiconductor device according to the present invention. In FIG. 3, a second P-type semiconductor region 41 exists between the first low-concentration N-type semiconductor region 42 and the first low-concentration P-type semiconductor region 40. FIG.
Then, a second N-type semiconductor region 54 is provided between the first low-concentration P-type semiconductor region 52 and the first low-concentration N-type semiconductor region 53.
Exists. In the embodiment shown in FIGS. 3 and 4, the second low-concentration P-type semiconductor region or the second low-concentration N-type semiconductor region is used.
The holding voltage can be adjusted by adjusting the impurity concentration of the type semiconductor region. In other words, the holding voltage in FIGS. 3 and 4 can be more optimized than the structure in FIGS. 1 and 2.
【００３０】次に、本発明によるサイリスタを静電気保
護回路に適用した回路例を図７、及び図８に示す。図７
では電源端子ーグラウンド端子間の保護素子として用い
られ、図８では電源端子ー入出力間の保護素子として用
いられている。上記実施例に示されるように、本発明に
より、従来例よりも低いホールディング電圧を持ち、か
つ、他の特性に影響を与えない、サイリスタが作製可能
となる。このように保護回路としてのサイリスタにおい
て、従来よりも低いホールディング電圧を有するため、
外部から加わった電荷（電圧）は、より低い電圧まで放
電され内部のＩＣやＬＳＩ回路に対して外部電荷（電
圧）の影響が小さくすることが可能となる。Next, FIGS. 7 and 8 show circuit examples in which the thyristor according to the present invention is applied to an electrostatic protection circuit. FIG.
In FIG. 8, it is used as a protection element between the power supply terminal and the ground terminal, and in FIG. 8, it is used as a protection element between the power supply terminal and the input / output. As shown in the above embodiment, the present invention makes it possible to manufacture a thyristor having a lower holding voltage than the conventional example and without affecting other characteristics. Since the thyristor as a protection circuit has a lower holding voltage than before,
The externally applied charge (voltage) is discharged to a lower voltage, and the influence of the external charge (voltage) on the internal IC and LSI circuit can be reduced.
【００３１】[0031]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、ＣＭＯＳプロセスにより形成されるサイリスタ
において、サイリスタのアノード部とカソード部に挟ま
れた、Ｎ型半導体領域もしくはＰ型半導体領域に相当す
る、第１の低濃度Ｎ型半導体領域と第１の低濃度Ｐ型半
導体領域の間に、第１の低濃度Ｎ型半導体領域よりも不
純物濃度の低い、第２の低濃度Ｎ型半導体領域もしくは
半導体基板領域を形成する、あるいは、第１の低濃度Ｐ
型半導体領域よりも不純物濃度の低い、第２の低濃度Ｐ
型半導体領域もしくは半導体基板領域を形成することに
より、ホールディング電圧を低くすることが可能であ
る。また、スイッチング電圧等のサイリスタの他の電気
特性は、従来構造と同様に決定され、ホールディング電
圧以外の特性には影響を与えない。As described above in detail, according to the present invention, in a thyristor formed by a CMOS process, an N-type semiconductor region or a P-type semiconductor region sandwiched between an anode portion and a cathode portion of a thyristor. And a second low-concentration N-type impurity having a lower impurity concentration than the first low-concentration N-type semiconductor region between the first low-concentration N-type semiconductor region and the first low-concentration P-type semiconductor region. Forming a semiconductor region or a semiconductor substrate region;
Low-concentration P having a lower impurity concentration than the p-type semiconductor region
By forming the mold semiconductor region or the semiconductor substrate region, the holding voltage can be reduced. Further, other electrical characteristics of the thyristor such as the switching voltage are determined in the same manner as in the conventional structure, and do not affect characteristics other than the holding voltage.
【００３２】以上のように、本発明により、微細プロセ
スに適した、低い酸化膜耐圧を持つプロセスに対する、
有効な半導体装置を形成する事が可能である。As described above, according to the present invention, for a process having a low oxide film breakdown voltage suitable for a fine process,
It is possible to form an effective semiconductor device.
【図１】本発明の実施例の工程断面図である。FIG. 1 is a process sectional view of an embodiment of the present invention.
【図２】本発明の別の実施例の断面図である。FIG. 2 is a cross-sectional view of another embodiment of the present invention.
【図３】本発明の別の実施例の断面図である。FIG. 3 is a sectional view of another embodiment of the present invention.
【図４】本発明の別の実施例の断面図である。FIG. 4 is a sectional view of another embodiment of the present invention.
【図５】一般的なサイリスタの電流−電圧特性を示す図
である。FIG. 5 is a diagram showing current-voltage characteristics of a general thyristor.
【図６】サイリスタの等価回路を示す図である。FIG. 6 is a diagram showing an equivalent circuit of a thyristor.
【図７】本発明の保護回路の第１の適用例である。FIG. 7 is a first application example of the protection circuit of the present invention.
【図８】本発明の保護回路の第２の適用例である。FIG. 8 is a second application example of the protection circuit of the present invention.
【図９】従来例の電流ー電圧特性を示す図である。FIG. 9 is a diagram showing current-voltage characteristics of a conventional example.
【図１０】本発明による電流ー電圧特性を示す図であ
る。FIG. 10 is a diagram showing current-voltage characteristics according to the present invention.
【図１１】従来例の工程断面図である。FIG. 11 is a process sectional view of a conventional example.
１４ Ｐ型シリコン基板 １７、３０ 低濃度Ｎ型半導体領域 １６、２９ 低濃度Ｐ型半導体領域 １５、２８、３９、５１ 素子分離絶縁部 ２３、３４、４６、５８ Ｎ型高濃度半導体領域 ２２、３３、４５、５７ Ｎ型高濃度半導体領域（カソ
ード部） １９、３１、４３、５５ Ｐ型高濃度半導体領域 ２０、３２、４４、５６ Ｐ型高濃度半導体領域（アノ
ード部） ２４、２５、２６、３５、３６、３７、４７、４８、４
９ 、５９、６０、６１ 配線部 ２７ Ｎ型シリコン基板 ３８、５０ Ｐ型シリコン基板もしくはＮ型シリコン基
板 ４２、５３ 第１の低濃度Ｎ型半導体領域 ４０、５２ 第１の低濃度Ｐ型半導体領域 ５４ 第２の低濃度Ｎ型半導体領域 ４１ 第２の低濃度Ｐ型半導体領域14 P-type silicon substrate 17, 30 Low-concentration N-type semiconductor region 16, 29 Low-concentration P-type semiconductor region 15, 28, 39, 51 Element isolation insulating part 23, 34, 46, 58 N-type high-concentration semiconductor region 22, 33 , 45, 57 N-type high-concentration semiconductor regions (cathode) 19, 31, 43, 55 P-type high-concentration semiconductor regions 20, 32, 44, 56 P-type high-concentration semiconductor regions (anode) 24, 25, 26, 35, 36, 37, 47, 48, 4
9, 59, 60, 61 Wiring section 27 N-type silicon substrate 38, 50 P-type silicon substrate or N-type silicon substrate 42, 53 First low-concentration N-type semiconductor region 40, 52 First low-concentration P-type semiconductor region 54 second low-concentration N-type semiconductor region 41 second low-concentration P-type semiconductor region
Claims (9)
域、及び、低濃度Ｐ型半導体領域が形成され、前記低濃
度Ｎ型半導体領域と前記低濃度Ｐ型半導体領域に挟まれ
てＰ型半導体基板領域が存在し、かつ、前記低濃度Ｎ型
半導体領域には、高濃度Ｎ型半導体領域と、アノード部
を形成する高濃度Ｐ型半導体領域が存在し、一方、前記
低濃度Ｐ型半導体領域には、高濃度Ｐ型半導体領域が存
在すると共に、前記低濃度Ｐ型半導体領域と基板領域の
両領域に接するように、カソード部を形成する高濃度Ｎ
型半導体領域が存在することを特徴とする半導体装置。1. A low-concentration N-type semiconductor region and a low-concentration P-type semiconductor region are formed in a P-type semiconductor substrate, and a P-type semiconductor region is sandwiched between the low-concentration N-type semiconductor region and the low-concentration P-type semiconductor region. A semiconductor substrate region exists, and the low-concentration N-type semiconductor region includes a high-concentration N-type semiconductor region and a high-concentration P-type semiconductor region forming an anode portion. A high-concentration P-type semiconductor region exists in the region, and a high-concentration N-type region for forming a cathode portion contacts both the low-concentration P-type semiconductor region and the substrate region.
A semiconductor device characterized by having a type semiconductor region.
域、及び、低濃度Ｐ型半導体領域が形成され、前記低濃
度Ｎ型半導体領域と前記低濃度Ｐ型半導体領域に挟まれ
てＮ型半導体基板領域が存在し、かつ、前記低濃度Ｐ型
半導体領域には、高濃度Ｐ型半導体領域と、カソード部
を形成する高濃度Ｎ型半導体領域が存在し、一方、前記
低濃度Ｎ型半導体領域には、高濃度Ｎ型半導体領域が存
在すると共に、前記低濃度Ｎ型半導体領域と基板領域の
両領域に接するように、アノード部を形成する高濃度Ｐ
型半導体領域が存在することを特徴とする半導体装置。2. A low-concentration N-type semiconductor region and a low-concentration P-type semiconductor region are formed on an N-type semiconductor substrate, and the N-type semiconductor region is sandwiched between the low-concentration N-type semiconductor region and the low-concentration P-type semiconductor region. A semiconductor substrate region exists, and the low-concentration P-type semiconductor region includes a high-concentration P-type semiconductor region and a high-concentration N-type semiconductor region forming a cathode portion. In the region, a high-concentration N-type semiconductor region exists, and a high-concentration P-type region for forming an anode portion contacts both the low-concentration N-type semiconductor region and the substrate region.
A semiconductor device characterized by having a type semiconductor region.
域、及び、第１の低濃度Ｐ型半導体領域が形成され、前
記第１の低濃度Ｎ型半導体領域と前記第１の低濃度Ｐ型
半導体領域に挟まれ、前記第１の低濃度Ｐ型半導体領域
よりも不純物濃度が低い、第２の低濃度Ｐ型半導体領域
が存在し、かつ、前記第１の低濃度Ｎ型半導体領域に
は、高濃度Ｎ型半導体領域と、アノード部を形成する高
濃度Ｐ型半導体領域が存在し、一方、前記第１の低濃度
Ｐ型半導体領域には、高濃度Ｐ型半導体領域が存在する
と共に、前記第１の低濃度Ｐ型半導体領域と前記第２の
低濃度Ｐ型半導体領域の両領域に接するように、カソー
ド部を形成する高濃度Ｎ型半導体領域が存在することを
特徴とする半導体装置。3. A first low-concentration N-type semiconductor region and a first low-concentration P-type semiconductor region are formed on a surface of a substrate, and the first low-concentration N-type semiconductor region and the first low-concentration N-type semiconductor region are formed. A second low-concentration P-type semiconductor region sandwiched between P-type semiconductor regions and having a lower impurity concentration than the first low-concentration P-type semiconductor region; and the first low-concentration N-type semiconductor region Has a high-concentration N-type semiconductor region and a high-concentration P-type semiconductor region forming an anode portion, while the first low-concentration P-type semiconductor region has a high-concentration P-type semiconductor region. In addition, a high-concentration N-type semiconductor region forming a cathode portion exists so as to be in contact with both the first low-concentration P-type semiconductor region and the second low-concentration P-type semiconductor region. Semiconductor device.
域、及び、第１の低度Ｐ型半導体領域が形成され、前記
第１の低濃度Ｎ型半導体領域と前記第１の低濃度Ｐ型半
導体領域に挟まれ、前記第１の低濃度Ｎ型半導体領域よ
りも、不純物濃度が低い、第２の低濃度Ｎ型半導体領域
が存在し、かつ、前記低濃度Ｐ型半導体領域には、高濃
度Ｐ型半導体領域と、カソード部を形成する高濃度Ｎ型
半導体領域が存在し、一方、前記第１の低濃度Ｎ型半導
体領域には、高濃度Ｎ型半導体領域が存在すると共に、
第１のＮ型半導体領域と第２のＮ型半導体領域の両領域
に接するように、アノード部を形成する高濃度Ｐ型半導
体領域が存在することを特徴とする半導体装置。4. A first low-concentration N-type semiconductor region and a first low-concentration P-type semiconductor region are formed on a substrate surface, and the first low-concentration N-type semiconductor region and the first low-concentration N-type semiconductor region are formed. A second low-concentration N-type semiconductor region sandwiched between P-type semiconductor regions and having an impurity concentration lower than that of the first low-concentration N-type semiconductor region exists. A high-concentration P-type semiconductor region and a high-concentration N-type semiconductor region forming a cathode portion, while the first low-concentration N-type semiconductor region includes a high-concentration N-type semiconductor region,
A semiconductor device, wherein a high-concentration P-type semiconductor region forming an anode portion is present in contact with both the first N-type semiconductor region and the second N-type semiconductor region.
成する部分をエッチ後、絶縁物を埋め込み、平坦化のた
めのＣＭＰ処理をして素子分離領域を形成する工程と、 低濃度Ｎ型半導体領域を形成する部分を開口し、Ｎ型不
純物を低濃度にイオン注入し低濃度Ｎ型半導体領域を形
成し、続いて前記Ｎ型半導体領域と所定の距離を離しＰ
型半導体基板領域が存在するように、低濃度Ｐ型半導体
領域を形成する部分を開口し、Ｐ型不純物を低濃度にイ
オン注入し、低濃度Ｐ型半導体領域を形成する工程と、 前記低濃度Ｎ型半導体領域上の一部と、前記低濃度Ｐ型
半導体領域上の一部を開口し、Ｐ型不純物を高濃度にイ
オン注入し、高濃度Ｐ型半導体領域を形成する工程と、 前記低濃度Ｎ型半導体領域上の一部と、前記低濃度Ｐ型
半導体領域と前記Ｐ型半導体基板領域の接面上の一部を
開口し、Ｎ型不純物を高濃度にイオン注入を行い、高濃
度Ｎ型半導体領域を形成する工程と、 熱処理により、注入した不純物を活性化させる工程と、 前記高濃度Ｎ型半導体領域と前記高濃度Ｐ型半導体領域
の各領域に、コンタクトを形成し、金属配線等で、電
源、グラウンド、もしくは入出力端子のいずれかに、電
気的に接続する工程とを含む半導体装置の製造方法。5. A step of forming a device isolation region by etching a portion where a device isolation region is to be formed on the surface of a P-type semiconductor substrate, embedding an insulator, and performing a CMP process for planarization to form a device isolation region. An opening is formed in a portion where a semiconductor region is to be formed, an N-type impurity is ion-implanted at a low concentration to form a low-concentration N-type semiconductor region.
Forming a low-concentration P-type semiconductor region by opening a portion where a low-concentration P-type semiconductor region is to be formed so that a low-concentration P-type semiconductor region is present; Forming a high-concentration P-type semiconductor region by opening a portion on the N-type semiconductor region and a portion on the low-concentration P-type semiconductor region, and ion-implanting a P-type impurity at a high concentration; An opening is formed in a portion on the N-type semiconductor region and a portion on a contact surface between the low-concentration P-type semiconductor region and the P-type semiconductor substrate region. Forming an N-type semiconductor region; activating implanted impurities by heat treatment; forming contacts in each of the high-concentration N-type semiconductor region and the high-concentration P-type semiconductor region; Power supply, ground, or input / output terminal Electrically connecting to one of the semiconductor devices.
成する部分をエッチ後、絶縁物を埋め込み、平坦化のた
めのＣＭＰ処理をして素子分離領域を形成する工程と、 低濃度Ｎ型半導体領域を形成する部分を開口し、Ｎ型不
純物を低濃度にイオン注入し低濃度Ｎ型半導体領域を形
成し、続いて前記Ｎ型半導体領域と所定の距離を離しＮ
型半導体基板領域が存在するように、低濃度Ｐ型半導体
領域を形成する部分を開口し、Ｐ型不純物を低濃度にイ
オン注入し低濃度Ｐ型半導体領域を形成する工程と、 前記低濃度Ｎ型半導体領域と前記Ｎ型半導体基板領域の
接面上の一部と、前記低濃度Ｐ型半導体領域上の一部を
開口し、Ｐ型不純物を高濃度にイオン注入を行い、高濃
度Ｐ型半導体領域を形成する工程と、 前記低濃度Ｎ型半導体領域上の一部と、前記低濃度Ｐ型
半導体領域上の一部を開口し、Ｎ型不純物を高濃度にイ
オン注入を行い、高濃度Ｎ型半導体領域を形成する工程
と、 熱処理により、注入した不純物を活性化させる工程と、 前記高濃度Ｎ型半導体領域と前記高濃度Ｐ型半導体領域
の各領域に、コンタクトを形成し、金属配線等で、電
源、グラウンド、もしくは入出力端子のいずれかに、電
気的に接続する工程とを含む半導体装置の製造方法。6. A step of forming an element isolation region by etching a portion where an element isolation region is to be formed on the surface of the N-type semiconductor substrate and then burying an insulator, and performing CMP for planarization to form an element isolation region. An opening is formed in a portion where a semiconductor region is to be formed, an N-type impurity is ion-implanted at a low concentration to form a low-concentration N-type semiconductor region.
Forming a low-concentration P-type semiconductor region by opening a portion where a low-concentration P-type semiconductor region is to be formed so as to have a low-concentration P-type semiconductor region; A part of the contact region between the n-type semiconductor substrate region and the n-type semiconductor substrate region and a part of the low-concentration p-type semiconductor region are opened, and a high-concentration p-type impurity is ion-implanted. Forming a semiconductor region; opening a part of the low-concentration N-type semiconductor region and a part of the low-concentration P-type semiconductor region; performing high-concentration ion implantation of N-type impurities; Forming an N-type semiconductor region; activating implanted impurities by heat treatment; forming contacts in each of the high-concentration N-type semiconductor region and the high-concentration P-type semiconductor region; Power supply, ground, or input / output Electrically connecting to one of the terminals.
をエッチ後、絶縁物を埋め込み、平坦化のためのＣＭＰ
処理をして素子分離領域を形成する工程と、 低濃度Ｎ型半導体領域を開口し、Ｎ型不純物を低濃度に
イオン注入を行い、第１の低濃度Ｎ型半導体領域を形成
し、続いて前記第１の低濃度Ｎ型半導体領域と所定の距
離を離し、低濃度Ｐ型半導体領域を開口し、Ｐ型不純物
を低濃度にイオン注入を行い、第１の低濃度Ｐ型半導体
領域を形成し、次いで、前記第１の低濃度Ｎ型半導体領
域と前記第１の低濃度Ｐ型半導体領域に挟まれた領域を
開口し、前記第１の低濃度Ｐ型半導体領域より低濃度の
Ｐ型不純物をイオン注入して、第２の低濃度Ｐ型半導体
領域を形成する工程と、 前記第１の低濃度Ｐ型半導体領域と前記第２の低濃度Ｐ
型半導体領域の接面上の一部と、低濃度Ｎ型半導体領域
上の一部を開口し、Ｐ型不純物を高濃度にイオン注入を
行い、高濃度Ｐ型半導体領域を形成する工程と、 前記第１の低濃度Ｐ型半導体領域上の一部と、前記第１
の低濃度Ｎ型半導体領域上の一部を開口し、Ｎ型不純物
を高濃度にイオン注入を行い、高濃度Ｎ型半導体領域を
形成する工程と、 熱処理により、注入した不純物を活性化する工程と、 前記高濃度Ｎ型半導体領域と前記高濃度Ｐ型半導体領域
の各領域に、コンタクトを形成し、金属配線等で、電
源、グラウンド、もしくは入出力端子のいずれかに、電
気的に接続する工程とを含む半導体装置の製造方法。7. After etching a portion for forming an element isolation region on a substrate surface, an insulator is buried, and CMP for planarization is performed.
Performing a process to form an element isolation region; opening a low-concentration N-type semiconductor region; performing ion implantation of N-type impurities at a low concentration to form a first low-concentration N-type semiconductor region; The first low-concentration N-type semiconductor region is separated from the first low-concentration N-type semiconductor region by a predetermined distance, a low-concentration P-type semiconductor region is opened, and P-type impurities are ion-implanted at low concentration to form a first low-concentration P-type semiconductor region. Then, an opening is formed in a region between the first low-concentration N-type semiconductor region and the first low-concentration P-type semiconductor region, and a P-type lower in concentration than the first low-concentration P-type semiconductor region is formed. Forming a second low-concentration P-type semiconductor region by ion-implanting an impurity; and forming the first low-concentration P-type semiconductor region and the second low-concentration P-type semiconductor region.
Opening a part on the contact surface of the type semiconductor region and a part on the low-concentration N-type semiconductor region, implanting P-type impurities at a high concentration, and forming a high-concentration P-type semiconductor region; A portion on the first low-concentration P-type semiconductor region;
Forming a high-concentration N-type semiconductor region by ion-implanting a portion of the low-concentration N-type semiconductor region with high-concentration N-type impurities; and activating the implanted impurities by heat treatment. And forming a contact in each of the high-concentration N-type semiconductor region and the high-concentration P-type semiconductor region, and electrically connecting to a power supply, a ground, or an input / output terminal by a metal wiring or the like. And a method of manufacturing a semiconductor device.
をエッチ後、絶縁物を埋め込み、平坦化のためのＣＭＰ
処理をして素子分離領域を形成する工程と、 低濃度Ｎ型半導体領域を開口し、Ｎ型不純物を低濃度に
イオン注入を行い、第１の低濃度Ｎ型半導体領域を形成
し、続いて前記第１の低濃度半導体領域と所定の距離を
離し、低濃度Ｐ型半導体領域を開口し、Ｐ型不純物を低
濃度にイオン注入を行い、第１の低濃度Ｐ型半導体領域
を形成し、次いで、前記第１の低濃度Ｎ型半導体領域と
前記第１の低濃度Ｐ型半導体領域に挟まれた領域を開口
し、前記第１の低濃度Ｎ型半導体領域より低濃度のＮ型
不純物をイオン注入して、第２の低濃度Ｎ型半導体領域
を形成する工程と、 前記第１の低濃度Ｐ型半導体領域上の一部と、前記第１
の低濃度Ｎ型半導体領域上の一部を開口し、Ｎ型不純物
を高濃度にイオン注入を行い、高濃度Ｎ型半導体領域を
形成する工程と、 前記第１の低濃度Ｎ型半導体領域と前記第２の低濃度Ｎ
型半導体領域の接面上の一部と、低濃度Ｐ型半導体領域
上の一部を開口し、Ｐ型不純物を高濃度にイオン注入を
行い、高濃度Ｐ型半導体領域を形成する工程と、 熱処理により、注入した不純物を活性化する工程と、 前記高濃度Ｎ型半導体領域と前記高濃度Ｐ型半導体領域
の各領域に、コンタクトを形成し、金属配線等で、電
源、グラウンド、もしくは入出力端子のいずれかに、電
気的に接続する工程とを含む半導体装置の製造方法。8. A method for etching a portion for forming an element isolation region on a substrate surface, embedding an insulator, and performing CMP for planarization.
Performing a process to form an element isolation region; opening a low-concentration N-type semiconductor region; performing ion implantation of N-type impurities at a low concentration to form a first low-concentration N-type semiconductor region; Forming a first low-concentration P-type semiconductor region by separating a predetermined distance from the first low-concentration semiconductor region, opening a low-concentration P-type semiconductor region, and ion-implanting a P-type impurity at a low concentration; Next, an area between the first low-concentration N-type semiconductor region and the first low-concentration P-type semiconductor region is opened, and an N-type impurity having a lower concentration than the first low-concentration N-type semiconductor region is removed. Ion-implanting to form a second low-concentration N-type semiconductor region; a portion on the first low-concentration P-type semiconductor region;
Forming a high-concentration N-type semiconductor region by opening a part of the low-concentration N-type semiconductor region and ion-implanting N-type impurities at a high concentration; The second low concentration N
Forming a high-concentration P-type semiconductor region by opening a part of the contact surface of the p-type semiconductor region and a part of the low-concentration P-type semiconductor region, and performing high-concentration ion implantation of P-type impurities; Activating the implanted impurities by heat treatment; forming contacts in each of the high-concentration N-type semiconductor region and the high-concentration P-type semiconductor region; Electrically connecting to one of the terminals.
半導体装置を、スイッチング電圧を低減するための構造
もしくは回路に組み込んだ事を特徴とする半導体装置。9. A semiconductor device, wherein the semiconductor device according to claim 1 is incorporated in a structure or a circuit for reducing a switching voltage.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP36583998A JP3398077B2 (en) | 1998-12-24 | 1998-12-24 | Semiconductor device and manufacturing method thereof |
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| JP36583998A JP3398077B2 (en) | 1998-12-24 | 1998-12-24 | Semiconductor device and manufacturing method thereof |
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| JP2000188389A true JP2000188389A (en) | 2000-07-04 |
| JP3398077B2 JP3398077B2 (en) | 2003-04-21 |
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| JP36583998A Expired - Lifetime JP3398077B2 (en) | 1998-12-24 | 1998-12-24 | Semiconductor device and manufacturing method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002329792A (en) * | 2001-04-27 | 2002-11-15 | Seiko Instruments Inc | Semiconductor device |
| JP2004531047A (en) * | 2000-11-06 | 2004-10-07 | サーノフ コーポレイション | Silicon controlled rectifier electrostatic discharge protection device with compact internal dimensions and external on-chip triggering for fast triggering |
| US7456440B2 (en) | 2004-04-23 | 2008-11-25 | Nec Electronics Corporation | Electrostatic protection device |
-
1998
- 1998-12-24 JP JP36583998A patent/JP3398077B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004531047A (en) * | 2000-11-06 | 2004-10-07 | サーノフ コーポレイション | Silicon controlled rectifier electrostatic discharge protection device with compact internal dimensions and external on-chip triggering for fast triggering |
| JP2002329792A (en) * | 2001-04-27 | 2002-11-15 | Seiko Instruments Inc | Semiconductor device |
| US7456440B2 (en) | 2004-04-23 | 2008-11-25 | Nec Electronics Corporation | Electrostatic protection device |
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| Publication number | Publication date |
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| JP3398077B2 (en) | 2003-04-21 |
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