JP2000183362A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve high isolation by keeping the potential in a region between Schottky electrodes constant in a dual-gate (multi-gate) FET. SOLUTION: Ohmic electrodes 14a and 14b that become source and drain electrodes are formed on a active layer 13 formed on a substrate 12, and two Schottky electrodes 15 are formed between both ohmic electrodes 14a and 14b. A pattern 17 for connection (a conductive layer) is drawn from the active layer region between the Schottky electrodes 15 and is connected to the ohmic electrode 14a, thus stabilizing the DC potential of the region between the Shottky electrodes 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor device. In particular, the present invention relates to a field effect type semiconductor element such as a MESFET and a semiconductor device such as an integrated circuit (IC) having the element.

[0002]

2. Description of the Related Art Switching elements of semiconductor MMICs are required to have high isolation, low loss, and small space (compact integration). As one of methods for satisfying these requirements, there are a dual gate FET, a multi-gate FET, and the like in which two or more Schottky electrodes are formed between ohmic electrodes, which are used for switching ICs.

FIG. 1 shows a conventional dual gate FET.
1 shows ohmic electrodes 4 a and 4 b serving as a source electrode and a drain electrode on an active layer 3 formed on a surface portion of a semiconductor substrate 2, and two electrodes extending from a pad portion 5. The Schottky electrode (gate electrode) 6 is disposed between the ohmic electrodes 4a and 4b.
Such dual gate FET and multi gate FET
Is adopted, a switching characteristic similar to that of a multi-stage FET switch in which a plurality of single gate FETs are arranged can be obtained. That is, according to the dual-gate FET, the size of the IC can be reduced while maintaining high isolation. In order to reduce the loss of the FET, FE
When T is on, the resistance Ron between the Schottky electrodes must be reduced. For this purpose, as in the dual gate FET 7 shown in FIG. 2, a method of forming a low resistance region 8 in the active layer 3 in an intermediate region between the Schottky electrodes 6 to reduce the loss. Commonly used.

[0004]

However, FIGS. 1 and 2
In the conventional dual-gate FET 7 shown in FIG. 5, since the region between the Schottky electrodes (intermediate region) is in a floating state (state in which the potential is not fixed), the Schottky electrodes 6, 6 located on both sides of the intermediate region Is affected by the fluctuation of the voltage applied to the intermediate region, and the voltage fluctuates up to the potential of the intermediate region (this fluctuation particularly occurs when the low resistance region is formed in the intermediate region). When the potential of the intermediate region fluctuates in accordance with the potentials of the Schottky electrodes 6 and 6 in this manner, the potential difference between the two decreases, but when the potential difference decreases, the pinch-off characteristics of the FET deteriorate. This is because the depletion layer is unlikely to spread between the regions having a small potential difference. As a result, there arises a problem that the ON / OFF characteristics of the switching element deteriorate.

When the potential of the intermediate region fluctuates with the potential of the Schottky electrodes 6, 6, the switching is performed using two gate regions.
The two gate regions and the intermediate region near the potential of the gate region operate as if they constitute one gate region. As a result, a situation arises in which the Coff value that should be reduced by the dual gate configuration cannot be sufficiently reduced. Note that the Coff value is an electric capacitance generated between the source and drain electrodes when the FET is pinched off.
Despite the pinch-off, the number of high-frequency signals leaking from the source electrode side to the drain electrode side increases (that is, the isolation decreases).

The present invention has been made to solve the above-mentioned technical problems, and an object of the present invention is to provide two or more Schottky electrodes between ohmic electrodes formed on a semiconductor substrate. Another object of the present invention is to make it possible to maintain a constant potential in a region (intermediate region) between respective Schottky electrodes in a field-effect semiconductor device.

[0007]

According to a first aspect of the present invention, there is provided a field effect type semiconductor device in which a plurality of Schottky electrodes are arranged between ohmic electrodes on a semiconductor substrate. And a means for maintaining a DC voltage at substantially the same potential as that of a region where the voltage is stable.

In the semiconductor device according to the present invention, a region (intermediate region) between the Schottky regions is DC-connected to a region (eg, an ohmic electrode such as a source / drain electrode) having a stable potential during operation of the semiconductor device. By doing so, the potential of the intermediate region is fixed (stabilized) to the potential of the stable region, the fluctuation of the potential of the intermediate region due to the fluctuation of the voltage of the Schottky electrode is suppressed, and the pinch-off characteristic of the semiconductor device is improved. It shall be. As a result, the Coff value can be reduced as originally intended, and the isolation of the semiconductor device can be increased. Further, it is not necessary to consider the fluctuation of the potential in the intermediate region when designing the semiconductor device, so that the design can be facilitated.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the region in which the voltage during operation is stable is an ohmic electrode or a region near the ohmic electrode.

The region where the voltage during operation is stable includes the ohmic electrode or a region near the ohmic electrode. If the region between the Schottky electrodes is connected to an ohmic electrode or the like, the means for holding the region between the Schottky electrodes at substantially the same DC potential as the region in which the voltage during operation is stable can be shortened. Can be reduced in size.

According to a third aspect of the present invention, in the semiconductor device according to the first aspect, the region between the Schottky electrodes and the region where the voltage during operation is stable are maintained at substantially the same DC potential. The means is a conductive layer which is drawn from a region between the Schottky electrodes and connected to a region where the voltage during operation is stable.

In this embodiment, the means for holding the region between the Schottky electrodes at the same DC potential as the region where the voltage during operation is stable is formed by the conductive layer.
In the case where the conductive layer is formed of an active layer, means for holding the region between the Schottky electrodes at substantially the same DC potential as the region in which the voltage during operation is stable can be formed simultaneously with the active layer. It can be simplified.

According to a fourth aspect of the present invention, in the semiconductor device according to the third aspect, a voltage between the Schottky electrodes during operation is increased by the conductive layer via a resistor capable of blocking a high-frequency signal. It is characterized by being connected to a stable area.

In this embodiment, since the means for holding the region between the Schottky electrodes at substantially the same DC potential as the region in which the voltage during operation is stable is provided with a resistor capable of cutting off the high-frequency signal, High frequency signals can be prevented from leaking from the region where the voltage is stable to the region between the Schottky electrodes or from the region between the Schottky electrodes to the region where the voltage during operation is stable.

According to a fifth aspect of the present invention, in the semiconductor device according to the third aspect, a region between the Schottky electrodes is connected to a region in which a voltage during operation is stabilized by the conductive layer via an inductor. It is characterized in that the region between the Schottky electrodes and the ohmic electrode have substantially the same DC potential, and the high-frequency signal is cut off.

In this embodiment, since the means for holding the region between the Schottky electrodes at substantially the same DC potential as the region where the voltage during operation is stable is provided with the inductor capable of cutting off the high-frequency signal, High frequency signals can be prevented from leaking from the region where the voltage is stable to the region between the Schottky electrodes or from the region between the Schottky electrodes to the region where the voltage during operation is stable.

An embodiment according to claim 6 is an embodiment according to claim 3,
The semiconductor device according to 4 or 5, wherein a low-resistance region is provided between the Schottky electrodes, and the conductive layer is drawn out of the low-resistance region.

In this embodiment, since the low-resistance region is formed between the Schottky electrodes, the loss of the semiconductor device can be reduced. Furthermore, since the potential of the region between the Schottky electrodes is stabilized by the connection pattern, a decrease in isolation which has conventionally been caused by providing a low-resistance region can be improved.

[0019]

(First Embodiment) FIG. 3 is a plan view showing the structure of a dual gate FET 11 according to one embodiment of the present invention. In the dual gate FET 11, an active layer 13 is formed on a surface layer on a GaAs semi-insulating substrate 12, and on both ends of the active layer 13,
An ohmic electrode 14a serving as a source electrode and an ohmic electrode 14b serving as a drain electrode are formed. Two Schottky electrodes (gate electrodes) 15 having a fine line width are formed on the upper surface of the active layer 13 in a region between the ohmic electrodes 14a and 14b, and are formed outside the active layer 13 (outside the element region). An electrode pad 16 is provided at an end of the Schottky electrode 15. Further, a connection pattern 17 is provided on the surface layer portion of the substrate 12 so as to be drawn out from a region between the Schottky electrodes 15 in the active layer 13, and the connection pattern 17 bypasses the outside of the active layer 13. The other end is connected to one ohmic electrode 1
The lower surface 4a (source electrode) is connected to the active layer 13 again. This connection pattern 13 is desirably formed at the same time as the active layer 13 by the same method, but may be formed separately.

The connection pattern 17 is a high-frequency cut (RF
Cut), and the DC potential in the region between the Schottky electrodes 15 (active layer region) through the connection pattern 17 is the same as the region in which the ohmic electrode 14a is provided (active layer region). But
High frequency signals are cut off. When the connection pattern 17 and the active layer 13 are formed at the same time and the sheet resistances of the two are equal, it is desirable to increase the length of the connection pattern 17 to increase the resistance value between both ends. . In this case, in order to increase the resistance value between both ends with a small area, the connection pattern 17 may be formed in a meandering shape (meander shape). Alternatively, when the active layer 13 and the connection pattern 17 are formed separately, the sheet resistance of the connection pattern 17 is
The sheet resistance should be larger than the sheet resistance of No. 3. These points also apply to other embodiments described below.

In the illustrated example, the Schottky electrode 15
The other end of the connection pattern 17 drawn out from the region between the two is electrically connected to the active layer 13 on the lower surface of one ohmic electrode 14a, but is electrically connected to the active layer 13 on the lower surface of both ohmic electrodes 14a and 14b. You may. Alternatively, the other end of the connection pattern 17 drawn from the region between the Schottky electrodes is not necessarily connected to the ohmic electrode 14.
The area is not limited to the area where a and 14b are formed.
What is necessary is just a part which is hardly affected by the fluctuating Schottky voltage as in the embodiment described later.

Further, the connection pattern 17 for connecting the region between the Schottky electrodes 15 and the lower surface region of the ohmic electrode 14a is preferably formed continuously by the same conductive layer as the active layer 13 to simplify the production of the connection pattern. Although desirable from the viewpoint, the connection pattern 17 may be formed by metal wiring formed on the substrate 12.

Next, a method of manufacturing the dual gate FET will be described. First, as shown in FIG. 4A, a GaAs semi-insulating substrate 1 is formed by MBE or MOCVD.
An active layer 13 is formed in each element formation region of No. 2. For example,
A dose of 5 × 10 ¹⁷ / cm using Si as a dose species
^The active layer 13 is grown in ² to obtain an active layer 13 having a sheet resistance of 700Ω / port.

Thereafter, as shown in FIG.
2 is covered with a resist film 18, a pattern for element isolation is formed by photolithography, and an element isolation groove 19 is formed in the substrate 12 by wet etching to perform element isolation. Here, for example, phosphoric acid:
Using an aqueous solution of hydrogen peroxide: water = 1: 1: 100, element isolation is completed in 10 minutes of etching time.

When patterning one element region by element isolation in this way, as shown in FIG.
The connection between the Schottky electrode 15 of the active layer 13 and the region where one of the ohmic electrodes 14 a (for example, the source electrode) is formed is connected to bypass the outside of the active layer 13. The pattern 17 is formed.
Therefore, the connection pattern 17 is the same conductive layer as the active layer 13 and has the same physical properties as the active layer 13, and is formed to have a line width of 5 μm and a length of 100 μm, for example.

Next, two ohmic electrodes 14a and 14b are formed on the upper surface of the active layer 13. In this step, after a resist film is applied on the substrate 12, the resist film is patterned by photolithography, and the Au-Ge
/ Ni or the like, which is to be in ohmic contact with the GaAs semi-insulating substrate 12, is vapor-deposited on the substrate 12 from above the patterned resist film, and the resist film is peeled off, as shown in FIG. Thus, ohmic electrodes 14a and 14b having a desired pattern are obtained.

Next, a Schottky electrode 15 is formed on the active layer 13. In this step, as shown in FIG. 4E, a resist film is formed on the substrate 12, the resist film is patterned by photolithography, and the Schottky electrode formation region is recess-etched. Next, after depositing an electrode material, such as Al, for Schottky junction with the GaAs semi-insulating substrate 12, a resist film is formed on the substrate 1.
2 to form a recess 20 by a lift-off method.
The Schottky electrode 15 is formed therein.

Next, an insulating film is formed on the substrate 12,
An electrode portion is opened in the insulating film by photolithography and etching, and an upper layer electrode is formed on the Schottky electrode and the ohmic electrode by photolithography and metal deposition. As a result, a dual gate FET 11 as shown in FIG. 3 is obtained.

The dual gate FET 11 is connected to the Schottky electrode 15 via the connection pattern 17 as described above.
Since the intermediate region (intermediate region) is connected to the ohmic electrode 14a whose potential is stable during the operation of the FET, the DC potential in the region between the Schottky electrodes 15 can be stabilized or fixed, and the pinch-off characteristics deteriorate. , The value of Coff can be reduced. Further, as shown in a measurement example described later, even if the DC potential in the region between the Schottky electrodes 15 is fixed, the resistance Ron between the Schottky electrodes 15 does not significantly affect the resistance value Ron between the Schottky electrodes 15. It can be kept at the same level as the conventional dual gate FET. As a result, the dual gate FET 11
Isolation can be improved while maintaining the features of low loss and small space.

(Second Embodiment) FIG. 5 is a plan view showing the structure of a dual gate FET 21 according to another embodiment of the present invention, and FIGS. 6 (a) to 6 (c) are plan views showing the manufacturing steps. . In this dual-gate FET 21, the low-resistance active layer 22 and the low-resistance active layer 22 are formed in the regions where the ohmic electrodes 14 a and 14 b are formed and
23, the low-resistance active layer 22 on which one ohmic electrode 14a is formed and the low-resistance active layer 23 between the Schottky electrodes 15 are connected by the connection pattern 17.

Hereinafter, the method for fabricating the dual gate FET according to this embodiment will be described with reference to FIGS. 6 (a) to 6 (c) and FIG. First, as shown in FIG. 6A, an active layer 13 and a connection pattern 17 are formed on a surface layer of a GaAs semi-insulating substrate 12 by selective ion implantation. To perform selective ion implantation, use an ion implanter to pass Si through a mask at an area density of, for example, 70 keV and 5 × 10 ¹² / cm ^2.
The active layer 13 having a desired pattern is formed by implanting ions.
And a connection pattern 17 are formed. In the connection pattern 17 shown in FIG. 6A, a gap is formed between both ends and the active layer 13. Here, the connection pattern 17 for connecting the active layer region between the Schottky electrodes 15 and the ohmic electrode 14a and the active layer 13 are formed at the same time, but they may be formed under different conditions.

Next, as shown in FIG. 6B, low resistance active layers 22 and 23 having lower resistance than the active layer 13 are formed on the substrate 12 by selective ion implantation. The low resistance active layers 22 and 23 are formed in a region where the ohmic electrodes 14 a and 14 b are formed and a region between the Schottky electrodes 15. That is, the active layer 13 is formed so as to avoid the region where the Schottky electrode 15 is formed. The low-resistance active layers 22 and 23 are formed so as to reach both ends of the connection pattern 17 and become conductive. The low resistance active layers 22 and 2
3 is, for example, 200 keV, 5 × 1 by an ion implanter.
It is formed by implanting Si ions at an area density of 0 ¹³ / cm ² .

Thereafter, activation annealing is performed at 820 ° C. for 20 minutes, and the active layer 1 having a sheet resistance of about 700 Ω / port is formed.
3 and the connection pattern 17 and a sheet resistance of about 70Ω /
The low-resistance active layers 22 and 23 of the mouth are obtained. In this way,
The connection pattern 17 is formed so as to be drawn out of the active layer 13 from the low resistance active layer 23 between the Schottky electrodes 15 and connected to the low resistance active layer 22 forming the ohmic electrode 14a. The connection pattern 17 also serves as an RF cut high impedance line, and is formed, for example, to have a width of 5 μm and a length of 100 μm.

Next, as shown in FIG. 6C, ohmic electrodes 14a and 14b are formed on the low resistance active layers 22 at both ends. In the ohmic electrode forming step, after forming a resist film on the substrate 12, the resist film is patterned by photolithography to form a Ga film such as Au-Ge / Ni.
An electrode material that forms an ohmic junction with the As semi-insulating substrate 12 is formed by vapor deposition from above the resist film, and the resist film is peeled off to obtain ohmic electrodes 14a and 14b having a desired pattern by a lift-off method.

Next, a Schottky electrode 15 is formed on the active layer 13 between the ohmic electrodes 14a and 14b.
Also in the Schottky electrode forming step, after forming a resist film on the substrate 12, the resist film is patterned by photolithography, and an electrode material such as Al for Schottky bonding with the GaAs semi-insulating substrate 12 is formed from above the resist film. A Schottky electrode 15 having a desired pattern is obtained by a lift-off method as shown in FIG. 5 by forming the film by vapor deposition and removing the resist film.

Finally, an insulating film is formed on the substrate 12, an electrode portion is opened in the insulating film by photolithography and etching, and a Schottky electrode 15 and ohmic electrodes 14a and 14b are formed by photolithography and metal deposition.
An upper electrode is formed on the substrate. As a result, the dual gate FET 21 of this embodiment is obtained.

The dual gate FET 21 of this embodiment
In this case, the DC potential in the region between the Schottky electrodes 15 is changed to a low-resistance active layer 22 having a stable potential during FET operation.
To stabilize the pinch-off characteristics and reduce the value of Coff, thereby realizing a switching IC with high isolation. In this embodiment, since the low-resistance active layer 23 is provided in the region between the Schottky electrodes 15, the loss can be further reduced.

(Third Embodiment) FIG. 7 is a plan view showing a structure of a dual gate FET 26 according to still another embodiment of the present invention. In this dual gate FET 26, the connection pattern 17 drawn from the low resistance active layer 23 between the Schottky electrodes 15 is connected to an independent electrode pad 27 provided on the GaAs semi-insulating substrate 12. . The independent electrode pad 27 is a pad that does not affect the electrical operation of any of the dual-gate FETs on the substrate 12 (that is, does not allow an AC signal to flow). A DC potential may be applied to the electrode pad 27 from outside the substrate, or the electrode pad 27 may be connected to a ground line.

According to this embodiment, the position of the electrode pad 27 and the circuit connected thereto can be arbitrarily selected, and the DC potential in the region between the Schottky electrodes 15 can be further stabilized.

(Fourth Embodiment) FIG. 8 is a plan view showing a structure of a dual gate FET 31 according to still another embodiment of the present invention. In this embodiment, a winding-shaped inductor portion 32 is formed in the middle of the connection pattern 17 drawn from the low-resistance active layer 23 between the Schottky electrodes 15. This inductor part 32 is
The same structure as in 3 may be incorporated in the substrate 12,
It may be formed on the substrate 12 by electrode wiring.
Reference numeral 33 denotes an insulating layer for insulation at the intersection of the inductor section 32. The inductor portion 32 is provided between the Schottky electrode 15 and the low-resistance active layer 2 for the DC potential.
3 has the same potential as the low-resistance active layer 22 provided with the ohmic electrode 14a, but is selected so that high-frequency signals are cut off. Further, in this embodiment, the inductor portion 32 is formed on or in the substrate 12, but may be configured to connect an inductor of an individual component outside the substrate.

According to this embodiment, the inductor section 32
Can be arbitrarily adjusted, and the design of the connection pattern 17 of the dual gate FET 31 becomes easy.

(Measurement Example) A conventional dual gate FET having a structure as shown in FIG. 1 was manufactured by changing the distance between gate electrodes (Schottky electrodes) to 2.4 μm, 2.8 μm, and 3.2 μm. . Similarly, the distance between the gate electrodes (Schottky electrodes) is set to 2.4 μm, 2.8 μm, and 3.2 μm.
The dual gate FET of the present invention having a structure as shown in FIG. Then, the resistance Ron and the Coff value between the Schottky electrodes in the conventional dual gate FET were measured. Further, the dual gate F of the present invention
In ET, the area between the Schottky electrodes is grounded through a connection pattern, and the resistance Ron and C
The off value was measured.

FIG. 9 shows the measured results of Ron and Coff (measured values in the dual gate FET of the present invention) /
(Measured value in a conventional dual-gate FET). As can be seen from the measurement results, by fixing the DC potential in the region between the Schottky electrodes as in the present invention, the value of Coff could be reduced by about 11% without deteriorating the pinch-off characteristics. Further, even if the DC potential in the region between the Schottky electrodes is fixed, the resistance Ron between the Schottky electrodes is not so affected.
Ron of the same level as that of the conventional dual gate FET was obtained.

[Brief description of the drawings]

FIG. 1 is a plan view showing a structure of a conventional dual gate FET.

FIG. 2 is a plan view showing the structure of another conventional dual gate FET.

FIG. 3 illustrates a dual gate FE according to an embodiment of the present invention.
It is a top view showing the structure of T.

FIGS. 4A to 4E are dual gate FETs according to the first embodiment;
It is a schematic sectional drawing which shows the manufacturing process of.

FIG. 5 illustrates a dual gate F according to another embodiment of the present invention.
It is a top view showing the structure of ET.

FIGS. 6 (a), (b) and (c) show dual gate F of the above.
It is a top view which shows the manufacturing process of ET.

FIG. 7 is a plan view showing a structure of a dual gate FET according to still another embodiment of the present invention.

FIG. 8 is a plan view showing a structure of a dual gate FET according to still another embodiment of the present invention.

FIG. 9 is a diagram showing Ron ratio and Coff ratio of a dual gate FET according to the present invention and a conventional dual gate FET.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 12 GaAs semi-insulating substrate 13 Active layer 14a, 14b Ohmic electrode 15 Schottky electrode 17 Connection pattern 22, 23 Low resistance active layer 27 Electrode pad 32 Inductor part

Continued on the front page F term (reference) 5F038 AR20 AZ01 AZ05 BE07 DF02 5F102 GA15 GA17 GA18 GB01 GC01 GC05 GD01 GJ05 GL05 GT02 GV03 HC01 HC07 HC11 HC15 HC19 HC21

Claims (6)

[Claims] In a field effect type semiconductor device in which a plurality of Schottky electrodes are arranged between ohmic electrodes on a semiconductor substrate, a region between the Schottky electrodes is directly connected to a region in which a voltage during operation is stable. A semiconductor device provided with means for maintaining substantially the same potential. 2. The semiconductor device according to claim 1, wherein the region in which the voltage during operation is stable is an ohmic electrode or a region near an ohmic electrode. 3. The means for maintaining a region between Schottky electrodes and a region in which a voltage during operation is stable at substantially the same potential in terms of direct current, comprises: The semiconductor device according to claim 1, wherein the semiconductor device is a conductive layer connected to a stable region. 4. The region between the Schottky electrodes is connected to a region in which a voltage during operation is stabilized by the conductive layer via a resistor capable of blocking a high-frequency signal. 13. The semiconductor device according to claim 1. 5. A region between the Schottky electrodes is connected to a region in which a voltage during operation is stabilized by the conductive layer via an inductor, and a region between the Schottky electrodes and the ohmic electrode are DC-connected. 4. The semiconductor device according to claim 3, wherein the high-frequency signals are substantially the same and the high-frequency signal is cut off. 6. The semiconductor device according to claim 3, wherein a low-resistance region is provided between the Schottky electrodes, and the conductive layer is extended from the low-resistance region.