JP2000174260A - Semiconductor device - Google Patents

Abstract

(57) Abstract: A semiconductor device comprising a HEMT in which a lightly doped layer or a non-doped layer is interposed between a cap layer and a channel layer to improve the withstand voltage in the forward and reverse directions at the gate. Even if there is no problem,
Ohmic contacts such as source and drain electrodes can be made well. SOLUTION: A semiconductor layer laminated structure formed on a substrate 1 and including at least a channel layer 3, an electron supply layer 5a, and a barrier layer 5b, and formed in a recess formed in a source region in the semiconductor layer laminated structure. And a heat-resistant metal layer 10 interposed between the wall surface of the recess and the source electrode 7 and in contact with both.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including a field effect transistor which has a high withstand voltage in a forward direction and a reverse direction at a gate and can make good ohmic contacts such as a source and a drain. About.

[0002]

2. Description of the Related Art As one of compound semiconductor field-effect transistors having good high-frequency characteristics and high-speed operation characteristics, a high electron mobility transistor (high electron mobility transistor) is known.
A known property is known as "bility transformer (HEMT)".

[0003] There are various types of HEMTs depending on the required characteristics. For example, if a high breakdown voltage is required,
Means such as planar doping or laminating a lightly doped layer or an undoped layer on the electron supply layer without taking uniform doping of the impurity in the electron supply layer are adopted.

In the HEMT having such a configuration, it is said that it is more difficult to form an ohmic contact than a HEMT having a standard structure, that is, a HEMT not intended to have a high breakdown voltage.

FIG. 12 is a sectional side view for explaining a HEMT having a standard structure, in which 1 is a substrate, 2 is a buffer layer, 3 is a channel layer, 4 is a spacer layer, 5a is an electron supply layer, 6 is a cap layer, 7 is a source electrode, 8 is a drain electrode, 9 is a gate electrode, 11 is an alloyed region, 13 is a current path, and 14 is a leak current path.

In this HEMT, since the forward and reverse breakdown voltages of the gate are not required to be so high, the gate electrode 9 has a structure in which the gate electrode 9 is in direct contact with the electron supply layer 5a. Since both layers 6 are heavily doped, the source electrode 7 and the drain electrode 8 can be easily brought into ohmic contact with the two-dimensional electron gas layer.

FIGS. 13 and 14 are sectional side views for explaining a HEMT having a structure for increasing the withstand voltage in the forward and reverse directions at the gate, and have the same symbols as those used in FIG. The symbols represent the same parts or have the same meaning.

Referring to FIG. 13, reference numeral 5b denotes a barrier layer formed between the electron supply layer 5a and the cap layer 6 and formed on the entire surface of the electron supply layer 5a.

In FIG. 14, reference numeral 12 denotes a low impurity concentration gate electrode buried layer formed on the barrier layer 5B.

In the HEMT shown in FIG. 13 or FIG. 14, the resistance of the region where the source electrode 7 and the drain electrode 8 are formed is high because of the presence of the barrier layer 5b and the low impurity concentration gate electrode buried layer 12. Difficult to make ohmic contact.

FIG. 15 is a cutaway side view of a main part for explaining a HEMT for solving the problem of the conventional example described with reference to FIG. 13 or FIG. 14, and is the same as the symbol used in FIG. The symbols represent the same parts or have the same meaning.

In FIG. 15, reference numeral 21 denotes a recess reaching the channel layer 3 from the surface of the cap layer 6.

In the HEMT shown in FIG. 15, layers having a high resistance such as a low impurity concentration gate electrode buried layer 12 and a barrier layer 5b are removed, and a source electrode 7 and a drain electrode 8 are brought into direct contact with the channel layer 3. Therefore, the problem of the HEMT described with reference to FIG. 13 or FIG. 14 has been solved, but a new problem arises due to the structure.

That is, in the HEMT shown in FIG. 15, a gap is formed between the gate side wall surface of the recess 21 and the ohmic electrode, so that a depletion layer spreads to a portion of the channel layer 3 immediately below the gap, and a parasitic layer is formed. The resistance will increase.

In order to prevent the generation of such a depletion layer, it seems to be sufficient to prevent the generation of the above-mentioned voids. However, in such a case, new inconvenience occurs. Will be.

FIG. 16 shows the HEMT described with reference to FIG.
FIG. 16 is a sectional side view of a main part for explaining a HEMT in which a gap is eliminated in FIG. 12, and the same symbols as those used in FIGS. 12 to 15 represent the same parts or have the same meanings.

In the HEMT shown in FIG. 16, the wall surface of the recess and the source electrode 7 or the drain electrode 8 are in contact with each other.
When the alloying heat treatment of the drain electrode 8 and the channel layer 3 is performed, the alloyed region 11 abnormally diffuses in the lateral direction, and the gate electrode 9 and the ohmic electrode come close to each other and the forward and reverse directions in the gate are formed. Withstand voltage of both of them decreases.

[0018]

According to the present invention, there is provided a HEMT in which a lightly doped layer or a non-doped layer is interposed between a cap layer and a channel layer to improve the withstand voltage in the forward and reverse directions at the gate. Even so, ohmic contacts such as a source electrode and a drain electrode can be satisfactorily obtained without causing any problem.

[0019]

According to the present invention, there is no difference from the prior art in that a recess is formed in a region where an ohmic electrode is formed, and the semiconductor layer requires ohmic contact directly. Basically, the configuration is such that no void is formed between the wall surface of the recess and the ohmic electrode, and the alloyed region of the ohmic electrode does not expand in the gate direction.

FIG. 1 is a cutaway side view showing a semiconductor device for explaining the principle of the present invention. In FIG. 1, reference numeral 1 denotes a substrate, 2 denotes a buffer layer, 3 denotes a channel layer, and 4 denotes a spacer layer. 5a is an electron supply layer, 5b is a barrier layer, 6 is a cap layer, 7 is a source electrode, 8 is a drain electrode, 9 is a gate electrode, 10 is a heat-resistant metal layer, 11 is an alloyed region, and 12 is a low concentration gate electrode. Each of the buried layers is shown.

A characteristic structure of the semiconductor device shown in FIG. 1 is that a heat-resistant metal layer 10 is interposed between a wall surface in a recess for forming a source electrode 7 or a drain electrode 8 and each ohmic electrode. It was done.

By adopting this configuration, the problem that the depletion layer extends to the channel layer 3 located immediately below the wall surface of the recess and the ohmic electrode and the parasitic resistance increases can be solved. When the alloying heat treatment of the ohmic electrode and the semiconductor is performed, there is no problem that the alloying region extends in the gate direction and the breakdown voltage is reduced.

As described above, in the semiconductor device according to the present invention, (1) at least a channel layer (for example, channel layer 3) formed on a semiconductor substrate (for example, substrate 1) and a carrier supply layer (for example, electron A semiconductor layer stack structure including a supply layer 5a) and a barrier layer (eg, barrier layer 5b); and a source electrode (eg, source electrode 7) formed in a recess formed in a source region in the semiconductor layer stack structure. And a refractory metal layer (for example, a refractory metal layer 10) interposed between the wall surface of the recess and the source electrode and in contact with both of the recesses. Even if the source electrode is formed after the recess is formed in the source provided closer to the gate electrode than the drain, the alloyed region may diffuse abnormally during the alloying heat treatment. Can be effectively prevented by a heat-resistant metal layer, and

(2) In the above (1), a drain electrode (for example, a drain electrode 8) formed in a recess formed in the drain region in the semiconductor layered structure, a wall surface of the recess, and And a heat-resistant metal layer interposed between and in contact with the drain electrode. According to this configuration, the drain electrode is usually formed after forming the recess also in the drain. However, abnormal diffusion of the alloyed region during the alloying heat treatment can be effectively prevented by the heat-resistant metal layer.

(3) In the above (1) or (2),
Characterized by the recess reaching the barrier layer,

(4) In the above (1) or (2),
The recess reaches the channel layer. According to this configuration and the configuration described in the above (3), the depth of the recess is selected according to the semiconductor layer laminated structure, and the depth of the recess is determined by the alloying heat treatment. Good alloying area with channel layer and ohmic
Can be contacted,

(5) In any one of the above (1) to (4), the impurity contained in the carrier supply layer may be a planar impurity.
Characterized by being doped, and

(6) In any one of the above (1) to (5), the carrier supply layer is an electron supply layer (for example, the electron supply layer 105a: see FIG. 2, the same applies hereinafter) and the electron supply layer On the layer, an i-layer (for example, barrier layer 105b) or an n-layer (for example, n ⁻ ) having a lower impurity concentration than the electron supply layer is provided.
Layers) are laminated, and

(7) In any one of the above (1) to (5), the carrier supply layer is a hole supply layer, and the carrier supply layer is formed on the hole supply layer as compared with the i-layer or the hole supply layer. And a p-layer having a low impurity concentration is formed by lamination.
Also,

(8) In any one of the above (1) to (7), the carrier supply layer (for example, the electron supply layer 135a:
9, the same applies hereinafter) is interposed between a channel layer (for example, channel layer 133) and a semiconductor substrate (for example, substrate 131). According to this configuration, a so-called inverted HEMT structure is realized. Is done.

By adopting the above means, a lightly doped layer or a non-doped layer is interposed between the cap layer and the channel layer in the HEMT to improve the withstand voltage in the forward and reverse directions at the gate, Even with such a semiconductor layer configuration, ohmic contacts such as a source electrode and a drain electrode can be satisfactorily realized, and problems caused by the configuration, such as a gap between the recess wall surface and the ohmic electrode, are reduced. There is no problem such as the occurrence of a depletion layer or the alloyed region of the ohmic electrode approaching the gate.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a sectional side view showing a main part of a semiconductor device for explaining a first embodiment of the present invention.

In the figure, 101 is a substrate, 102a is a buffer layer, 102b is a buffer layer, 103 is a channel layer, 104 is a spacer layer, 105a is an electron supply layer,
5b is a barrier layer, 106 is a cap layer, 107 is a source electrode, 108 is a drain electrode, 109 is a gate electrode, 1
Reference numeral 10 denotes a heat-resistant metal layer, and 111 denotes an alloyed region.

FIGS. 3 to 7 are cutaway side views of a main part of a semiconductor device in a process essential point for explaining a manufacturing process of the semiconductor device shown in FIG. 2. Referring to FIGS. It will be explained while doing.

FIG. 3 (A) 3- (1) MOVPE (metalorganic vapor)
A first buffer layer 102a, a second buffer layer 102b, a channel layer 103, and a spacer layer 10 are formed on a substrate 101 by applying a phase epitaxy method.
4. An electron supply layer 105a, a barrier layer 105b, and a cap layer 106 are formed.

The main data relating to each of the above semiconductor portions is exemplified as follows. About the substrate 101 Material: semi-insulating InP About the first buffer layer 102a Material: i-InP Thickness: 50 [nm] About the second buffer layer 102b Material: i-InAlAs (In composition 0.52) Thickness: 300 [ nm] About the channel layer 103 Material: i-InGaAs (In composition 0.53) Thickness: 20 [nm] About the spacer layer 104 Material: i-InAlAs Thickness: 3 [nm] About the electron supply layer 105a Material: n− InAlAs (In composition 0.52) Impurity concentration: 5 × 10 ¹⁸ [cm ⁻³ ] Thickness: 5 [nm] About barrier layer 105b Material: i-InAlAs (In composition 0.52) Thickness: 20 [nm] About the cap layer 106 Material: n-InGaAs (In composition 0.53) Impurity concentration: 1 × 10 ¹⁹ [cm ⁻³ ] Thickness: 50 [nm] ]

Referring to FIG. 3B, a resist film 161 having an opening at a portion where a recess is to be formed is formed by applying a resist process in lithography.

3- (3) Wet using etchant as phosphoric acid-based etching solution
By applying the etching method, the resist film 161 is formed.
, The cap layer 106, the barrier layer 105b,
The electron supply layer 105a and the spacer layer 104 are etched to form a recess 104A.

4 (A) 4- (1) A WSi film 162 having a thickness of about 5 [nm] is formed on the entire surface by applying the sputtering method.

[0040] FIG. 4 (B) depending on the reference 4- (2) to the etching gas applying the dry etching method with SF _6, anisotropic etching is performed of the WSi film 162, the wall surface of the recess 104A Only WSi film 1
Leave 62.

5 (A) 5- (1) The thickness is 30 [nm] by applying the vacuum evaporation method.
An electrode material film 163 of AuGe / Au having a thickness of / 300 [nm] is formed.

Referring to FIG. 5B, 5- (2) the resist film 1 is immersed in a resist stripping solution.
Patterning is performed by peeling the electrode material 61 together with the laminated electrode material film 163.

The electrode material film 163 remaining after the lift-off process is used as the source electrode 107 and the drain electrode 108.
Becomes

5- (3) By applying the ion milling method, the electrode material film 163 and the WSi film 16 projecting on the recess wall surface are formed.
2 is removed by milling from an oblique direction.

5- (4) At a temperature of 400 ° C. and a time of 3 minutes, a heat treatment for alloying the semiconductor with the source electrode 107 and the drain electrode 108 is performed, and the channel layer 3 An alloyed region 111 that contacts the gas layer is created.

6 (A) 6- (1) An electron beam (elect) having a different sensitivity is obtained by applying a resist process in lithography technology.
ron beam: EB) resist films 164a and 164a
64b are formed. The EB resist films 164a and 164a
The sensitivity of 64b is 164a <164b.

6- (2) EB lithography is performed to form openings 164B in the resist films 164b and 164a in the portions where gate electrodes are to be formed, corresponding to the laterally extending portions of the gate electrode having a T-shaped cross section.
An opening 164A having a shape corresponding to the leg portion is also formed.

6- (3) The resist film 16 is formed by applying a wet etching method using an etchant as a citric acid-based etching solution.
The cap layer 106 is etched using the masks 4b and 164a as masks.

The etching here is over-etching, and a side etching of, for example, about 0.1 [μm] is applied to the cap layer 106 in the lateral direction. As a result, the opening 164A of the resist film 164a (FIG. 5
A void 106H extending beyond the range of (A) is generated. Note that the citric acid-based etchant does not etch the barrier layer 105b made of i-InAlAs, which is the base of the cap layer 106.

6- (4) By applying the vacuum evaporation method, a thickness of 30
An Al film of about [nm] is formed.

The Al film is formed of resist films 164b and 164a.
Through the opening of the cap layer 106, and the tip thereof makes Schottky contact with the barrier layer 105b.

FIG. 7 7- (1) The resist film 1 is immersed in a resist stripping solution.
By stripping 64b and 164a together with the laminated Al film, the Al film is patterned to form the gate electrode 165.

The semiconductor device manufactured through the above steps is
Since the WSi film 162 is interposed between the source electrode 107 or the drain electrode 108 and the recess wall, no depletion layer is generated in the channel layer 103, so that the parasitic resistance does not increase. Since there is no problem that the activated region 111 extends from the side surface of the source electrode 107 or the drain electrode 108 and approaches the gate electrode 165, the gate breakdown voltage does not decrease.

FIG. 8 is a fragmentary side view showing a semiconductor device for explaining a second embodiment of the present invention.
The same symbols as those used in FIG. 7 to FIG. 7 represent the same parts or have the same meanings.

In the figure, 121 is a substrate, 122a is a buffer layer, 122b is a buffer layer, 123 is a channel layer, 124 is a spacer layer, 125a is an electron supply layer, 12
5b indicates a barrier layer, and 126 indicates a cap layer.

The main differences between the second embodiment and the first embodiment are the configuration of the semiconductor portion and the method of forming the ohmic electrode recess. This will be described below.

About the substrate 121 Material: semi-insulating GaAs About the buffer layer 122a Material: i-GaAs Thickness: 50 [nm] About the buffer layer 122b Material: i-AlGaAs (Al composition 0.3) Thickness: 300 [nm] About the channel layer 123 Material: i-InGaAs (In composition 0.15) Thickness: 15 [nm] About the spacer layer 124 Material: i-InGaP (In composition 0.5) Thickness: 3 [nm] Electron supply layer About 125a Material: n-InGaP (In composition 0.5) Impurity concentration: 2 × 10 ¹⁸ [cm ⁻³ ] Thickness: 20 [nm] About barrier layer 125b Material: i-InGaP (In composition 0.5) Thickness Thickness: 10 [nm] About the cap layer 126 Material: n-GaAs Impurity concentration: 2 × 10 ¹⁸ [cm ⁻³ ] Thickness: 50 [nm]

The method of forming the ohmic electrode recess is as follows.
Dry etching of ₄ or wet etching using an etchant as an ammonia-based etchant is applied. For InGaP, wet etching using an etchant as an HCl-based etchant is applied.

FIG. 9 is a fragmentary side view showing a semiconductor device for describing Embodiment 3 of the present invention.
8 to FIG. 8 represent the same parts or have the same meaning.

In the figure, 131 is a substrate, 132a is a buffer layer, 132b is a buffer layer, 133 is a channel layer, 134 is a spacer layer, 135a is an electron supply layer, 13
5b indicates a barrier layer, and 136 indicates a cap layer.

The main differences between the third embodiment and the first embodiment are the configuration of the semiconductor portion and the method of forming the ohmic electrode recess. This will be described below.

About the substrate 131 Material: semi-insulating GaAs About the buffer layer 132a Material: i-GaAs Thickness: 50 [nm] About the buffer layer 132b Material: i-AlGaAs (Al composition 0.3) Thickness: 300 [nm] About the channel layer 133 Material: i-InGaAs (In composition 0.15) Thickness: 15 [nm] About the spacer layer 134 Material: i-AlGaAs (Al composition 0.3) Thickness: 3 [nm] Electron supply layer About 135a Material: n-AlGaAs (Al composition 0.3) Impurity concentration: 2 × 10 ¹⁸ [cm ⁻³ ] Thickness: 20 [nm] About barrier layer 135b Material: i-AlGaAs (Al composition 0.5) Thickness Thickness: 20 [nm] About the cap layer 136 Material: n-GaAs Impurity concentration: 2 × 10 ¹⁸ [cm ⁻³ ] Thickness: 50 [nm] The barrier layer is made of AlGaAs having an Al composition of 0.4 or more.
In the case where s is used, if the configuration in which the ohmic electrode is formed on the cap layer 136 is adopted, it is difficult to make ohmic contact, and in the configuration in which the ohmic electrode is formed in the recess, the problem is solved because it is advantageous. .

As a method of forming the ohmic electrode recess, dry etching using SiCl ₄ as an etching gas or wet etching using an etchant as an ammonia-based etching solution is applied.

FIG. 10 is a cutaway side view showing a main part of a semiconductor device for describing a fourth embodiment of the present invention. The same symbols as those used in FIGS. 2 to 9 denote the same parts. Shall represent or have the same meaning.

In the figure, 141 is a substrate, 142a is a buffer layer, 142b is a buffer layer, 143 is a channel layer, 144 is a spacer layer, 145a is an electron supply layer,
5b is a barrier layer, 145c is a gate burying layer, 146
Indicates a cap layer.

The main differences between the fourth embodiment and the first embodiment are the configuration of the semiconductor portion, the method of forming the ohmic electrode recess and the etching depth, and the method of manufacturing the gate. These will be described below. .

For the substrate 141 Material: Semi-insulating GaAs Buffer layer 142a Material: i-GaAs Thickness: 50 [nm] For Buffer Layer 142b Material: i-AlGaAs (Al composition 0.3) Thickness: 300 [nm] About the channel layer 143 Material: i-InGaAs (In composition 0.15) Thickness: 15 [nm] About the spacer layer 144 Material: i-AlGaAs (Al composition 0.3) Thickness: 3 [nm] Electron supply layer About 145a Material: n-AlGaAs (Al composition 0.3) Impurity concentration: 2 × 10 ¹⁸ [cm ⁻³ ] Thickness: 20 [nm] About barrier layer 145b Material: i-AlGaAs (Al composition 0.3) Thickness Thickness: 10 [nm] About the gate burying layer 145 c Material: i-GaAs Thickness: 30 [nm] About the cap layer 146 Material: n-GaAs Impurity concentration: 2 × 10 ¹⁸ [cm ⁻³ ] Thickness: 50 [nm]

As the method for forming the ohmic electrode recess, dry etching using SiCl ₄ as an etching gas or wet etching using an etchant as an ammonia-based etchant is applied, and the recess is formed by the cap layer 146 and the gate. This is the depth from which the buried layer 145c has been removed.

As a method of manufacturing a gate, as in Embodiment 1, after etching the cap layer 146, subsequently etching the gate burying layer 145c, depositing a gate metal, and then lifting the gate. Patterning is performed by the off method.

FIG. 11 is a cutaway side view showing a main part of a semiconductor device for explaining a fifth embodiment of the present invention. The same symbols as those used in FIGS. 2 to 10 denote the same parts. Shall represent or have the same meaning.

In the figure, 151 is a substrate, 152a is a buffer layer, 152b is a buffer layer, 153 is a channel layer, 154 is a spacer layer, 155a is an electron supply layer,
5b is a barrier layer having a high Al composition, 155c is a barrier layer,
155d indicates a gate burying layer, and 156 indicates a cap layer.

The main differences between the fifth embodiment and the first embodiment are the configuration of the semiconductor portion, the method of forming the recess for the ohmic electrode, the etching depth, and the method of manufacturing the gate, which will be described below. .

(1) For the substrate 151 Material: semi-insulating GaAs (2) For the buffer layer 152a Material: i-GaAs Thickness: 50 [nm] (3) For the buffer layer 152b Material: i-AlGaAs (Al composition 0) .3) Thickness: 300 [nm] (4) About the channel layer 153 Material: i-InGaAs (In composition 0.15) Thickness: 15 [nm] (5) About the spacer layer 154 Material: i-AlGaAs (Al Composition: 0.3) Thickness: 3 [nm] (6) Regarding the electron supply layer 155a Material: n-AlGaAs (Al composition: 0.3) Impurity concentration: 2 × 10 ¹⁸ [cm ⁻³ ] Thickness: 20 [nm] (7) About barrier layer 155b with high Al composition Material: i-AlGaAs (Al composition 0.5) Thickness: 7 [nm] (8) About barrier layer 155c : I-AlGaAs (Al composition 0.3) Thickness: 3 [nm] (9) About gate burying layer 155d Material: i-GaAs Thickness: 30 [nm] (10) About cap layer 156 Material: n-GaAs Impurity concentration: 2 × 10 ¹⁸ [cm ^-3 ] Thickness: 50 [nm]

As a method for forming the ohmic electrode recess, dry etching using SiCl ₄ as an etching gas or wet etching using an etchant as an ammonia-based etching solution is applied, and the recess is formed by the cap layer 156 and the gate. This is the depth from which the buried layer 155c is removed.

As in the first embodiment, the gate layer is formed by etching the cap layer 156, subsequently etching the gate burying layer 155c, depositing a gate metal, and then lifting the gate. Patterning is performed by the off method.

Next, an example in which the carrier supply layer is formed by planar doping will be described as a sixth embodiment of the present invention. The structure of the semiconductor device is shown in FIGS.
0 according to the first embodiment described for n-InA
The illustration is omitted because only the GaAs electron supply layer 105a is replaced with a planar doping layer.

In order to fabricate a semiconductor device using planar doping, the same steps as in the first embodiment are employed to form each semiconductor layer up to the spacer layer 104 on the substrate 101, and then an As material, for example, A Si raw material, for example, disilane (Si ₂ H ₆ ) is supplied together with arsine (AsH ₃ ) to form a Si planar doping layer.

Here, the reason why the As material is supplied is to prevent re-evaporation of As from the spacer layer 104, and the impurity concentration in the Si planar doping layer is 5 × 10 ¹² [cm ^-2 ].

After forming the Si planar doping layer, the same steps as in the first embodiment, that is, the barrier layer 10
5b and cap layer 106, formation of WSi film 162, formation of source electrode 107 and drain electrode 108,
What is necessary is just to form the gate electrode 165 and to complete it.

In the sixth embodiment, since the electron supply layer or the hole supply layer, which is the carrier supply layer, is a monoatomic layer, the distance between the gate electrode and the channel layer becomes short, and the short channel effect occurs. It has the advantage of being difficult, and is suitable for a semiconductor device with a short gate length.

In the present invention, without being limited to the above-described embodiment, many other modifications can be realized.
By appropriately selecting the conductivity type of each semiconductor layer or the like, the electron supply layer can be replaced with a hole supply layer, and a semiconductor device using holes as carriers can be easily formed.

The material of each semiconductor layer, for example, an appropriate material such as InAlAs, InGaP, or AlGaAs for the carrier supply layer can be selected and used. Conditions, doping concentrations, impurity addition conditions, metal materials, manufacturing processes, and the like can be appropriately selected. Particularly, as the material of the heat-resistant metal layer, in addition to WSi used in the above-described embodiment, W
One or more types can be selected from SiN, TiW, TiWN, Mo, and the like.

[0083]

In the semiconductor device according to the present invention, a semiconductor layer laminated structure formed on a semiconductor substrate and including at least a channel layer, a carrier supply layer and a barrier layer, and a source region in the semiconductor layer laminated structure A source electrode (or drain electrode) formed in a recess formed in the (or drain region), a heat-resistant intervening between a wall surface of the recess and the source electrode (or drain electrode) and in contact with both. A metal layer.

By adopting the above configuration, the forward breakdown voltage and the reverse breakdown voltage at the gate are improved by interposing a lightly doped layer or a non-doped layer between the cap layer and the channel layer in the HEMT, Even with such a semiconductor layer configuration, ohmic contacts such as a source electrode and a drain electrode can be satisfactorily realized, and problems caused by the configuration, such as a gap between the recess wall surface and the ohmic electrode, are reduced. There is no problem such as the occurrence of a depletion layer or the alloyed region of the ohmic electrode approaching the gate.

[Brief description of the drawings]

FIG. 1 is a fragmentary side view showing a semiconductor device for explaining a principle of the present invention;

FIG. 2 is a fragmentary side view showing a semiconductor device for describing Embodiment 1 of the present invention;

FIG. 3 is a fragmentary side view showing the semiconductor device at a key step in the manufacturing process of the semiconductor device shown in FIG. 2;

FIG. 4 is a fragmentary side view showing the semiconductor device at a key step in the manufacturing process of the semiconductor device shown in FIG. 2;

5 is a fragmentary side view showing a semiconductor device at a key step in the manufacturing process of the semiconductor device shown in FIG. 2;

FIG. 6 is a fragmentary side view showing the semiconductor device at a key step in the manufacturing process of the semiconductor device shown in FIG. 2;

FIG. 7 is a fragmentary side view showing the semiconductor device at a key step in the manufacturing process of the semiconductor device shown in FIG. 2;

FIG. 8 is a fragmentary side view showing a semiconductor device for explaining a second embodiment of the present invention;

FIG. 9 is a fragmentary side view showing a semiconductor device for describing a third embodiment of the present invention;

FIG. 10 is a fragmentary side view showing a semiconductor device for describing Embodiment 4 of the present invention;

FIG. 11 is a fragmentary side view showing a semiconductor device for describing Embodiment 5 of the present invention;

FIG. 12 is a fragmentary side view for explaining a HEMT having a standard structure.

FIG. 13 is a fragmentary side view for explaining a HEMT having a structure for increasing the forward breakdown voltage and the reverse breakdown voltage in the gate.

FIG. 14 is a fragmentary side view for explaining a HEMT having a structure for increasing the forward breakdown voltage and the reverse breakdown voltage in the gate.

FIG. 15 is a cutaway side view of a main part for explaining a HEMT for solving the problem of the conventional example described with reference to FIG. 13 or FIG.

FIG. 16 is a cutaway side view of a main part for explaining a HEMT in which a gap is eliminated in the HEMT described with reference to FIG. 15;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Buffer layer 3 Channel layer 4 Spacer layer 5a Electron supply layer 5b Barrier layer 6 Cap layer 7 Source electrode 8 Drain electrode 9 Gate electrode 10 Heat resistant metal layer 11 Alloyed area 12 Low impurity concentration gate electrode buried layer

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 AA04 AA05 BB02 BB09 BB10 CC01 CC03 DD08 DD09 DD34 DD68 FF04 FF07 FF27 GG12 5F102 FA01 FA03 GB01 GC01 GD01 GJ05 GJ06 GK04 GK05 GK06 GK08 GL04 G04 GM04 GM20 GM04 GM20 GT02 HC01 HC04 HC11 HC15 HC18 HC21

Claims (8)

[Claims] A semiconductor layer structure formed on a semiconductor substrate and including at least a channel layer, a carrier supply layer, and a barrier layer; and a recess formed in a source region of the semiconductor layer structure. A source electrode, and a refractory metal layer interposed between a wall surface of the recess and the source electrode and in contact with both. 2. A drain electrode formed in a recess formed in a drain region in a semiconductor layered structure, a heat-resistant metal interposed between a wall surface of the recess and the drain electrode and in contact with both. The semiconductor device according to claim 1, further comprising a layer. 3. The semiconductor device according to claim 1, wherein the recess reaches the barrier layer. 4. The semiconductor device according to claim 1, wherein the recess reaches the channel layer. 5. The semiconductor device according to claim 1, wherein said impurity contained in said carrier supply layer is planar-doped. 6. The carrier supply layer is an electron supply layer, and an i-layer or an n-layer having a lower impurity concentration than the electron supply layer is formed on the electron supply layer. The semiconductor device according to claim 1. 7. The method according to claim 7, wherein the carrier supply layer is a hole supply layer, and an i-layer or a p-layer having a lower impurity concentration than the hole supply layer is formed on the hole supply layer. The semiconductor device according to claim 1, wherein: 8. The semiconductor device according to claim 1, wherein a carrier supply layer is interposed between the channel layer and the semiconductor substrate.