JP2000165051A - Dielectric circuit board and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: Provided is a dielectric circuit board having excellent high-frequency characteristics and capable of being miniaturized, and a method of manufacturing the same. According to the present invention, an internal conductor pattern (2) made of a low-resistance metal material is arranged between dielectric layers of a laminated body (1) formed by laminating a plurality of dielectric layers (1a to 1e).
This is a dielectric circuit board formed with via-hole conductors 3 made of a low-resistance metal material penetrating in the thickness direction of a to 1e. In a part between the adjacent dielectric layers, the upper and lower main surfaces are the conductive film 7.
1, 73 and the dielectric layers 1a to 1
Capacitor forming portion 7 made of dielectric film 72 thinner than e
Was placed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dielectric circuit board in which a high-capacity capacitor is built in a laminated body, which is excellent in high frequency applications, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Hitherto, a dielectric circuit board having a multilayer structure including a resonator, a capacitor, a filter element and the like has been widely known.

[0003] In particular, in recent years, with the development and spread of high frequency devices such as mobile communications represented by mobile phones, dielectric ceramics have been actively used as electronic components used in a high frequency region. .

In a dielectric circuit board having a multilayer structure, it is necessary to simultaneously sinter a dielectric ceramic constituting a dielectric layer and a conductor material constituting an internal conductor pattern such as a resonance conductor pattern, a conductor film for generating inductance, and a capacitor electrode. There is. Therefore, it is necessary to prevent the internal conductor pattern from melting at the firing temperature of the ceramics constituting the dielectric layer.

[0005] Ceramic materials constituting the dielectric layer, for example, dielectric ceramics such as alumina, steatite and forsterite have high firing temperatures, and metals such as Pt, Pd, W and Mo are used for the internal conductor pattern. Had been.

[0006] However, although the metal has a high melting point, it also has a large conduction resistance, and as a result, the Q value of the resonance circuit is reduced as a circuit board used for high-frequency equipment, and the transmission of the conductor line is reduced. There were problems such as a large loss.

In order to solve such a problem, it has been proposed to use a low-resistance metal such as Ag, Cu, or Au for the internal conductor pattern. At the same time, a dielectric material which can be sufficiently fired even in such a metal material is proposed. Various body ceramics have been proposed.

Further, in order to meet the demand for miniaturization and high performance of circuit boards used in recent high-frequency devices, the resonance circuit and inductance can be miniaturized by increasing the relative permittivity εr in a specific frequency region. Various types of composite dielectrics have been proposed, since the Q factor of the dielectric ceramic can be increased, and the Q factor of the resonance circuit can be increased to reduce the loss.

Conventionally, for example, the dielectric ceramic composition disclosed in Japanese Patent Application Laid-Open No. 4-292460 is composed of anorthite-calcium titanate-based glass and TiO _2, and can be fired simultaneously at a low temperature. It could be fired simultaneously with a metal such as Ag or Cu as the metal material of the conductor pattern.

As a method of manufacturing a multilayer substrate, there has been a laminating method using a green sheet multilayer method (Japanese Patent Publication No. 40-8458) and a printing multilayer method (Japanese Patent Publication No. 57-19599).

[0011]

However, in the dielectric porcelain composition disclosed in Japanese Patent Application Laid-Open No. 4-292460, the relative dielectric constant .epsilon.r is as low as less than 16 in a high-frequency region of 4 to 6 GHz, which is lower than the conventional value. With a multilayer substrate structure, only a low-capacitance capacitor can be formed, and there is a limit to miniaturization of a circuit board used for high-frequency equipment.

The present invention has been made in view of the above problems,
An object of the present invention is to provide a dielectric circuit board which can use an internal conductor pattern of a low-resistance metal material of Au, Ag, or Cu, has excellent high-frequency characteristics, and can be miniaturized, and a method of manufacturing the same. .

[0013]

A first invention is a dielectric circuit board, and a second invention is a manufacturing method of the first invention.

According to a first aspect of the present invention, an internal conductor pattern made of a low-resistance metal material is arranged between each dielectric layer of a laminate formed by laminating a plurality of dielectric layers, and a thickness direction of the dielectric layer is changed. In a dielectric circuit board having a via-hole conductor made of a low-resistance metal material penetrating therethrough, both upper and lower main surfaces are sandwiched by a conductor film in a part between the adjacent dielectric layers, and have a thickness greater than that of the dielectric layer. This is a dielectric circuit board on which a capacitance forming section made of a thin dielectric film is disposed.

According to a second aspect of the present invention, there is provided (1) a first method for forming a dielectric layer.
And facilitating the second dielectric green sheet;
(2) a step of forming a conductor to be an internal conductor pattern and a via hole conductor on the first and second dielectric green sheets; and (3) a lower conductor film and a dielectric on a part of the second dielectric green sheet. The body film and the upper conductor film are sequentially printed and laminated,
Forming a capacitance generating portion, (4) laminating and pressing the first dielectric green sheet and the second green sheet to form a laminate, and (5) firing the laminate. This is a method for manufacturing a dielectric circuit board comprising:

[0016]

According to the first aspect of the present invention, a capacitance forming portion including a lower electrode, a dielectric film, and an upper electrode is disposed in a part of the dielectric layer. However, this dielectric film is thinner than the dielectric layer.

Therefore, short-circuits between the internal conductor patterns arranged between adjacent dielectric layers are less likely to occur.
An extremely large capacitance can be obtained as compared with the capacitance obtained by sandwiching the dielectric layer between the internal conductor patterns in the capacitance forming portion composed of the lower electrode, the dielectric film, and the upper electrode.

Further, by controlling the thickness of the dielectric film in the capacitance forming portion, an arbitrary capacitance can be arranged in a local portion of the laminated body.

In the second invention, the dielectric layer is formed of a dielectric green sheet, and the capacitance forming portion is formed on a specific dielectric green sheet (second dielectric green sheet) by a thick film technique. After a conductor film serving as a film, a coating film serving as a dielectric film, and a conductor film serving as an upper electrode are formed, a green sheet multilayer including these second dielectric green sheets is formed.

In high frequency applications, the thickness of the fired internal conductor pattern is required to be about 15 μm in order to reduce the conductor resistance of the internal conductor pattern. Further, in order to match the characteristic impedance, a fine pattern of about 100 μm must be formed.

Here, if the thickness of the dielectric green sheet is set to 10 μm or less in order to obtain a high capacity, the rigidity of the green sheet is reduced, and even if the above-mentioned internal conductor pattern is formed in accordance with a high frequency application. In addition, the conductor film serving as the internal conductor pattern cannot be formed stably, and when the conductor film serving as the internal conductor pattern is baked, cracks may occur around the internal conductor pattern, or the dielectric green sheet and the internal conductor pattern may not be formed. Therefore, the thickness difference between the dielectric film and the conductive film cannot be absorbed, and peeling between dielectric layers occurs.

In this respect, in the present invention, the thickness of the dielectric green sheet forming the internal conductor pattern is set to, for example, 100
By setting the thickness sufficiently to about 200 μm, the conductive film serving as the internal conductor pattern can be reduced in conduction resistance and formed into a fine pattern.

Further, since the capacitance forming portion is constituted by a capacitance forming portion formed on the green sheet by a thick film technique, a higher capacitance can be arbitrarily formed due to the thickness of the dielectric film. In addition, since the thickness of the dielectric film has no influence on the internal conductor pattern arranged between the dielectric layers, the characteristics of both can be maintained stably.

In addition, since a capacitance forming portion having a predetermined capacitance can be arranged at an arbitrary portion in the laminated circuit board, the circuit configuration, that is, the degree of freedom in drawing a circuit pattern is improved, and a small circuit board is obtained. .

That is, in the multilayer substrate structure of the present invention, a thin dielectric film can be formed inside the substrate as compared with the conventional structure, a capacitor having a high capacitance can be formed, and the size of the high-frequency electronic component can be reduced. High performance can be realized.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a dielectric circuit board according to the present invention and a method for manufacturing the same will be described with reference to the drawings.

FIG. 1 is a sectional view of a dielectric circuit board according to the present invention.

In the circuit board 10 according to the present invention, an internal conductor pattern 2 and a via-hole conductor 3 are formed in a laminate 1 in which a plurality of dielectric layers 1a to 1e are laminated. A surface wiring hattern 4 is formed, and electronic components 5 and 6 are mounted as needed.

A capacitance forming portion 7 is formed between the dielectric layers, for example, between the dielectric layers 1b and 1c. The capacitance forming portion 7 is configured by laminating a lower conductor film (lower electrode) 71, a dielectric film 72, and an upper conductor film (upper electrode) 73 continuously with the internal conductor pattern 2.

The dielectric layers 1a to 1e are made of MgO, CaO,
It is composed of a dielectric ceramic containing TiO ₂ as a main component and B ₂ O ₃ , Li ₂ CO ₃ , etc. so that it can be sintered at a low temperature.

As an example of the composition, aMgO-
When expressed as bCaO-cTiO ₂ , the molar ratios a, b, and c are 2
5 ≦ a ≦ 35, 0.3 ≦ b ≦ 7, 60 ≦ c ≦ 70, where a + b + c = 100, and 3 to 20 parts by weight of the boric acid compound and 1 of the lithium-containing compound with respect to 100 parts by weight of the main component. -10 parts by weight.

The dielectric layers 1a to 1e are formed of dielectric green sheets containing the above-described dielectric material as a main component, and have a thickness of 100 to 200 μm.

The dielectric film 72 of the capacitance forming section 7 is formed by printing a dielectric paste made of the above-described dielectric material, and has a thickness of about 20 to 30 μm.

Further, between the plurality of dielectric layers 1a to 1e,
The internal conductor patterns 2 are arranged to form a predetermined circuit network. Here, the internal conductor pattern 2 includes, in addition to a conductive pattern forming a predetermined circuit network, a resonance circuit, an inductor conductor forming a filter, an electrode forming a capacitor having a relatively small capacitance, an electrode layer serving as a ground potential, and the like. Can be illustrated.

The internal conductor pattern is made of an Ag-based material (Ag is a material containing Ag as a main component, Ag alone or Ag-Pd or the like).
(Alloy), Au-based and Cu-based materials having a low melting point and low resistance.

In the thickness direction of the dielectric layers 1a to 1e, via-hole conductors 3 for forming a predetermined circuit network are formed. The internal conductor patterns 2 are connected to each other by the via-hole conductors 3. The via-hole conductor 3 is also made of an Ag-based material (Ag is a main component of Ag, or an Ag alloy such as Ag-Pd), an Au-based, or a Cu-based metal material, similarly to the internal conductor pattern 2.

On the surface of the laminate 1, a surface wiring pattern connected to the via-hole conductor 3 formed in the dielectric layer 1a is formed.

On this surface wiring pattern 4, an electronic component 5 such as an IC chip and a chip component 6 to be joined by solder or the like are mounted as required.

Further, the capacitor forming portion 7 formed inside the laminate 1 is provided with the lower electrode 7 connected to the internal conductor pattern 2.
1, a dielectric film 72, and an upper electrode 73.

The lower electrode 71 and the upper electrode 73 are made of an Ag-based material (a material containing Ag as a main component, Ag alone or an Ag alloy such as Ag-Pd) as in the case of the internal conductor pattern 2,
, A Cu-based metal material and a dielectric film 72
Is made of the same dielectric material as the dielectric layers 1a to 1e as described above. The lower electrode 71 is integrally connected to the inner conductor pattern 2 on the same plane as shown in the figure, and is further connected to, for example, a via-hole conductor 3 (not shown in the figure) formed in the dielectric layer 1c. It is connected. The upper electrode 73 extends to the outside of the dielectric film 72 and is connected to the internal conductor pattern 2 formed on the same plane as the lower electrode 71.
Dielectric layer 1 connected to via hole conductor 3 formed in
It is connected to the internal conductor pattern 2 between the layers a and 1b.

As described above, the dielectric film 72 is formed on the dielectric layer 1.
a to 1e composed of the same dielectric material;
When the upper and lower electrodes 71 and 73 are made of the same material as the internal conductor pattern 2, the manufacturing process involves integrally firing.
This is to prevent separation or the like due to a difference in sintering behavior.

In the figure, a capacitance forming section 8 is also formed on the surface of the dielectric layer 1a. The capacitance forming portion 8 on this surface
Is composed of a lower electrode 81, a dielectric film 82, and an upper electrode 83 which are integrally connected to the surface wiring pattern 4 in the same manner as the capacitance forming portion 7 arranged inside the above-mentioned laminated body 1. The capacitance forming section 8 may be formed after the laminated body 1 is formed by firing, or may be formed on a green sheet.

Such a dielectric circuit board is formed as follows.

First, there is a step of preparing first and second dielectric green sheets to be the dielectric layers 1a to 1e.

The dielectric green sheets serving as the dielectric layers 1a to 1e are prepared by first mixing 24 parts of a raw material powder of MgTiO ₃ and CaTiO _{3 having} a purity of 99% or more, which are dielectric materials, with pure water.
After mixing in a ball mill for an hour, the mixture is dried, and then the dried product is calcined in the air at a temperature of 1200 ° C. for 1 hour, and B ₂ O ₃ powder and Li ₂ CO ₃ are added to the calcined product.
After mixing the powder in a ball mill for 24 hours, it was dried to obtain a dielectric raw material powder, and an acrylic binder, a plasticizer, and toluene were added to the powder and mixed in a ball mill for 40 hours.
A green sheet was obtained by a doctor blade method.

The dielectric green sheets can be roughly classified into two types in terms of processing. That is, the dielectric layers 1b, 1d, 1e
A first dielectric green sheet (having no capacitance forming portion on the upper surface) and a second dielectric green sheet (capacitance forming portion formed on the upper surface) to become the dielectric layers 1a and 1c. is there.

Next, there is a step of forming a conductor to be an internal conductor pattern and a via-hole conductor on the first and second dielectric green sheets.

In the first and second dielectric green sheets,
According to the formation position of the via-hole conductor 3, a through-hole to be the via-hole conductor 3 is formed by an NC punch or the like.

Thereafter, the conductor paste is filled in the through-hole and dried to form a conductor. Subsequently, the conductive film serving as the internal conductor pattern 2 and the surface wiring pattern 4 is printed and dried with a conductive paste.

In the figure, since the lower electrodes of the capacitance forming portions 7 and 8 are formed integrally with the internal conductor pattern 2 and the surface wiring pattern 4, the conductor film to be the lower electrodes 71 and 81 is formed in this step. It may be formed.

Next, on the second dielectric green sheet to be the dielectric layers 1a and 1c, portions to be the capacitance forming portions 7 and 8 are formed. Here, since the conductor films to be the lower conductor films 71 and 81 are formed in the previous step, the description is omitted. Then, a coating film to be the dielectric films 72 and 82 is formed on the conductor film to be the lower electrodes 71 and 81 by printing and drying a dielectric paste. Dielectric films 72, 82
A conductive film to be the upper electrodes 73 and 83 is further formed on the coating film to be printed by printing and drying a conductive paste. By printing and drying the conductive paste and the dielectric paste, the components of the stacked capacity generating units 7 and 8 are formed.

The dielectric films 72 and 82 are formed on the dielectric layer 1
a, 1c as the binder, ethyl cellulose as the solvent, and 2.2.4. as the solvent. -Trimethyl-1.3. A dielectric paste obtained by mixing one pendiol monoisobutyrate with a three-roll mill to form a paste is used.

FIG. 2A shows, for example, the dielectric layer 1b.
FIG. 2 shows a cross-sectional view of a first green sheet,
(B) is a cross-sectional view of a second green sheet to be a dielectric layer 1c, for example.

Next, the first dielectric green sheet and the second green sheet are laminated and pressed in accordance with the lamination order to form a laminate.

That is, the first dielectric green sheet and the second green sheet are laminated in accordance with the lamination order of the dielectric layers 1a to 1e to form the laminate 1.

In this state, for example, since the surface wiring pattern 4 has already been formed on the surface of the dielectric layer 1a, a surface wiring pattern on the lower surface side of the dielectric layer 1e is formed before and after lamination.

Next, the above-described laminate is fired. The firing includes a binder removal step and a main firing step. The binder removal step is a temperature range of about 600 ° C. or lower, and is a process of burning out the first and second dielectric green sheets, the dielectric film, the conductor film, and the organic binder contained in the conductor. In addition, the main firing step is performed at a peak temperature of 850-10.
This is a firing process at 50 ° C., for example, at 900 ° C. for 60 minutes. As a result, the five dielectric layers 1a to 1e, the capacitance forming parts 7 and 8, the internal conductor pattern 2, the via hole conductor 3, and the surface wiring pattern 4 undergo a sintering reaction, and the laminate 1 is achieved.

Thereafter, the electronic components 5 and 6 are mounted as required.

In the above-described structure, at least the inside of the laminated body 1, that is, between the dielectric layers 1b and 1c,
Can be formed locally.

In particular, the capacitance characteristics of the capacitance forming section 7 are determined by the area of the lower electrode 71 facing the upper electrode 73 and the thickness of the dielectric film 72. In order to obtain a high capacitance, the facing area may be increased, but this is not preferable because the size of the substrate is increased. Therefore, the thickness of the dielectric film 72 is important. The thickness of the dielectric film 72 is 1 by one printing.
A film thickness of 5 to 20 μm is obtained. Therefore, the dielectric film 72
If printing is performed twice at the maximum in forming the film, the film thickness becomes about 15 to 40 μm, and a very high capacity can be formed. Incidentally, preferably 20 to 30 μm
It is.

In consideration of the thickness of the dielectric layers 1a to 1e, the thickness is about 100 to 200 μm, that is, 100 μm or more. This is a thickness necessary for obtaining sufficient rigidity as a green sheet and for stably forming a conductor film serving as the internal conductor pattern 2 formed on the green sheet.

In particular, in high frequency applications, printing is performed so that the thickness of the internal conductor pattern after firing is about 15 μm in order to reduce the conductor resistance of the internal conductor pattern 2, and about 100 μm in order to match the characteristic impedance. Easy printing of fine patterns. Thereby, the high frequency characteristics of the entire dielectric circuit board can be improved. This means that the internal conductor pattern 2 itself is made of Au, Ag, C
By using a low-resistance material such as u, a circuit board having more excellent high-frequency characteristics can be obtained.

The dielectric layers 1a to 1e and the dielectric film 7
2 and 82 are made of the same dielectric material, and the inner conductor pattern 2 and the lower electrodes 71 and 81 and the upper electrodes 73 and 83 are made of the same material. No peeling or cracking occurs.

In the above-described embodiment, the circuit board having five dielectric layers has been described. However, the number of dielectric layers is not limited to five.
Although one capacitance forming portion is formed between the dielectric layers of the multilayer body 1 in the figure, a plurality of capacitance forming portions may be formed depending on a circuit network.

In the manufacturing method, the conductor film to be the surface wiring pattern 4 may be baked after the laminate is fired, and at the same time, the capacity forming section 8 may be formed in the fired laminate.

As a dielectric layer and a dielectric film, Mg
Although the description has been given of the dielectric ceramic containing O, CaO, and TiO ₂ as main components, the dielectric material is not limited to the above-described materials as long as the same material can be fired at 800 to 1050 ° C.

[0067]

According to the present invention, a short circuit between internal conductor patterns arranged between adjacent dielectric layers is less likely to occur, and a capacitance component of a capacitance forming portion composed of a lower electrode, a dielectric film, and an upper electrode is reduced. Thus, the dielectric circuit board can obtain a very large capacitance as compared with the capacitance obtained by sandwiching the dielectric layer between the internal conductor patterns.

Further, by controlling the thickness of the dielectric film in the capacitance forming portion, an arbitrary capacitance can be arranged in a local portion of the laminated body.

Further, since the capacitance forming portion is formed by the thick film method, its capacitance characteristics can be controlled by the thickness of the dielectric film, and the internal conductor pattern can be formed with a sufficient thickness and a fine pattern. Therefore, a circuit board having excellent high-frequency characteristics can be obtained.

Further, since a capacity forming portion having a predetermined capacity can be arranged at an arbitrary portion in the laminated circuit board, the circuit configuration, that is, the degree of freedom in the arrangement of circuit patterns is improved, and a small circuit board is obtained. .

[Brief description of the drawings]

FIG. 1 is a sectional view of a dielectric circuit board according to the present invention.

FIG. 2 (a) is a view showing a first example of a dielectric circuit board according to the present invention.
FIG. 3B is a cross-sectional view of the dielectric green sheet of FIG.
3 is a cross-sectional view of the dielectric green sheet of FIG.

[Explanation of symbols]

 1 ... Laminated body 1a-1e ... Dielectric layer 2 ... Inner conductor pattern 3 ... Via hole conductor 4 ... Surface wiring pattern 7 ... Capacity forming part 71 ... Lower electrode 72 Dielectric film 73 Upper electrode

Claims (2)

[Claims] An internal conductor pattern made of a low-resistance metal material is disposed between each dielectric layer of a laminate formed by laminating a plurality of dielectric layers, and a low-resistance metal penetrating through a thickness direction of the dielectric layer is provided. A dielectric circuit board formed with a via-hole conductor made of a material, wherein a dielectric film whose upper and lower main surfaces are sandwiched by a conductive film between a part of the adjacent dielectric layers and which is thinner than the dielectric layer A dielectric circuit board, wherein a capacitance forming part made of a film is arranged. And (2) a step of preparing first and second dielectric green sheets to be dielectric layers, and (2) an internal conductor pattern and a via-hole conductor on the first and second dielectric green sheets. (3) a step of sequentially printing and laminating a lower conductor film, a dielectric film, and an upper conductor film on a part of the second dielectric green sheet to form a capacitance generating portion. And (4) a step of laminating and pressing the first dielectric green sheet and the second green sheet to form a laminate, and (5) a step of firing the laminate. Method.