JP2000039717A - Method of forming resist pattern and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a resist pattern with high sensitivity by forming a specified resist layer on the surface of a substrate, exposing it and developing the exposed resist layer with a specified developer. SOLUTION: An electron beam resist layer contg. a compd. of formula I [where each of (m) and (n) is an integer of 10-10,000] is formed on the surface of a substrate and exposed by irradiation with energy beams and the exposed resist layer is developed with a developer of formula II (where R is 1-5C alkyl). The resist layer is formed by spin-coating the surface of the substrate such as an Si substrate with a resist contg. the compd. of the formula I and carrying out prescribed baking. The selected region of the resist layer is irradiated with electron beams and the substrate with the resist layer is immersed in a developing soln. contg. the developer of the formula II to develop the resist layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of forming a resist pattern, and more particularly to a method of forming a resist pattern using an electron beam resist and a method of manufacturing a semiconductor device.

[0002]

2. Description of the Related Art In a semiconductor device, it is desired to reduce the size of a semiconductor element in order to improve the degree of integration or the operating speed. In order to satisfy such a demand for miniaturization, it is necessary to increase the resolution of a lithography technique used for patterning. In order to improve the resolution, it is effective to use an energy beam having a short wavelength.

[0003] X-rays and electron beams have wavelengths significantly shorter than ultraviolet rays, and can realize high resolution. Electron beam exposure scans the electron beam further,
Various patterns can be arbitrarily drawn according to a program.

As one of the manufacturing techniques of a semiconductor device using electron beam exposure, there is a method of forming a gate electrode of a high-speed element using a compound semiconductor. In order to improve the characteristics of a high-speed element such as a high electron mobility transistor, it is necessary to reduce the opening width of the gate electrode. However, simply reducing the width of the gate electrode opening increases the resistance of the gate electrode, which hinders speeding up.

As a means for solving this problem, a gate electrode is formed by a T-shaped electrode. The T-shaped electrode is an electrode having a cross section in which the width is small on the side in contact with the semiconductor substrate and widened toward the top. When a Schottky gate electrode of a compound semiconductor transistor such as a HEMT is formed by a T-shaped electrode, it is possible to reduce the width of an effective gate electrode in contact with a semiconductor substrate and reduce the resistance of the gate electrode.

As a lithography technique for forming a T-shaped gate electrode, a three-layer resist laminated structure is used,
A technique for performing heavy exposure is known. Two electron beam resist layers are formed with the alkali-soluble layer interposed therebetween, and a wide width exposure is performed for the upper electron beam resist layer and a narrow width exposure is performed for the lower electron beam resist layer.

The upper electron beam resist layer is developed corresponding to a wide exposure area, the intermediate alkali-soluble layer is developed through an opening formed in the upper electron beam resist layer, and the lower electron beam resist layer is narrow. Develop corresponding to the width of the exposure area.

By such a process, it is possible to form a resist pattern having a compound opening having a narrow opening width at the lower portion and a wide opening width at the upper portion. After forming such a resist pattern, an electrode layer for a Schottky gate electrode is formed by vapor deposition, sputtering, etc., and the laminated resist pattern is removed, and the electrode layer thereon is lifted off, so that the electrode layer is deposited on the resist opening of the composite shape. T
A schottky gate electrode remains on the substrate.

[0009]

According to the conventional three-layer resist process, during the development of the lower electron beam resist layer, the effect of the wide width electron beam irradiation for the upper electron beam resist layer remains, realizing high resolution. It was difficult to do.

An object of the present invention is to provide a method of forming a resist pattern which can realize high sensitivity.

Another object of the present invention is to provide a method of manufacturing a semiconductor device which realizes a fine pattern.

[0012]

According to one aspect of the present invention, a step of forming a resist layer containing the general formula (1) on a base surface;

[0013]

Embedded image . . . . (1)

Irradiating the resist layer with an energy beam to expose the resist layer; developing the exposed resist layer with a developer containing the general formula (2);

[0015]

Embedded image . . . . (2) A method for forming a resist pattern comprising:

According to another aspect of the present invention, a step of forming a first electron beam resist layer on a base surface, a step of forming an alkali-soluble layer on the first electron beam resist layer,
Forming a second electron beam resist layer containing the general formula (1) on the alkali-soluble layer;

[0017]

Embedded image . . . . (1)

A step of irradiating the second electron beam resist layer with an energy beam from above the second electron beam resist layer and exposing the second electron beam resist layer to a general formula (2) Developing with a developer containing

[0019]

Embedded image . . . . (2) A method for forming a resist pattern comprising:

According to yet another aspect of the present invention, (a)
A step of preparing a semiconductor substrate having a channel region and a pair of current extraction regions connected to the channel region;
(B) forming a first electron beam resist layer, an alkali-soluble layer, and a second electron beam resist layer on the semiconductor substrate in this order; and (c) traversing a channel region between the pair of current extraction regions. Exposing the second electron beam resist layer with an energy beam of a first width so as to perform the second step; and (d) exposing the second electron beam resist layer with an energy beam of a second width smaller than the first width in the first region. (1) exposing the electron beam resist layer;
(E) developing the second electron beam resist layer with a first developer containing the general formula (2);

[0021]

Embedded image . . . . (2)

(F) removing the alkali-soluble layer under the opening formed in the second electron beam resist layer;
(G) developing the first electron beam resist layer with a second developer.

When a developer containing the general formula (2) is used as a developer for the electron beam resist, high sensitivity can be realized.
By making the development highly sensitive, the time required for the lithography process can be reduced.

In the three-layer resist process, the upper electron beam resist layer is developed with high sensitivity to reduce the amount of energy beam irradiation for the upper electron beam resist layer. The amount of irradiation of the energy beam which is incidentally incident on the lower electron beam resist layer is reduced, and the lower electron beam resist layer can be developed with high resolution.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited to these embodiments.

FIGS. 1A to 1D show a lithography process of a single-layer electron beam resist layer according to an embodiment of the present invention.

As shown in FIG. 1A, an electron beam resist layer 11 is formed on a base substrate 10. For example, Si
An electron beam positive resist ZEP520A manufactured by ZEON CORPORATION, which is a resist containing the substance represented by the above general formula (1), is spin-coated on a surface of a base substrate 10 formed of a substrate with a thickness of about 0.2 μm. Apply. Electron beam resist layer 1
After spin coating 1, 180 ° C on a hot plate,
Bake for 120 seconds. Baking is 180 ° C
The temperature is not limited to 120 ° C. and 250 ° C. or less.

Thereafter, the selected area 12 of the electron beam resist layer 11 is irradiated with an electron beam EB. For example, electron beam irradiation is performed at an acceleration voltage of 30 kV and a current value of 0.1 nA using an electron beam exposure apparatus ELS-3300 manufactured by Elionix. By changing the electron beam irradiation time,
The dose amount D is changed.

As shown in FIG. 1B, a base substrate 10 having an electron beam resist layer 11 irradiated with an electron beam is immersed in a developing solution 15 containing the general formula (2) to develop the electron beam resist layer 11. Perform

[0030]

Embedded image . . . . (2)

The compound represented by the general formula (2) includes
For example, ethyl benzoate represented by the chemical formula (3) can be used.

[0032]

Embedded image . . . . (3)

According to the above-described embodiment, ethyl benzoate was used as a developer, and the development time T was changed in the range of 30 seconds to 300 seconds. After the development, the underlying substrate having the patterned electron beam resist layer is replaced with ZMD-B manufactured by Zeon Corporation.
(89:11 mixed solution of methyl isobutyl ketone and isopropyl alcohol).

For comparison, the same development was carried out using ZEP-SD (40:60 mixed solution of methyl ethyl ketone and methyl isobutyl ketone) manufactured by Zeon Corporation as a developer according to the conventional technique.

FIG. 1C is a graph showing a change in the residual film ratio with respect to Dose D when ethyl benzoate is used as a developer. The development time T was 30 seconds, 60 seconds,
The characteristics when 120 seconds, 180 seconds, and 300 seconds are employed are plotted.

When the developing time T is 30 seconds, the residual film ratio does not decrease significantly unless the dose D is high. Development time T is 6
When the time is increased to 0 seconds, 120 seconds, and 180 seconds, the remaining film ratio for the same dose D decreases, and eventually the remaining film ratio becomes zero. Therefore, even if the dose D is low, the development time T
Is sufficiently long, it is possible to completely remove the electron beam resist layer in the exposed area.

FIG. 1D shows ZEP-SD as a developing solution.
The result when using is shown. Development time T is 30 seconds, 60
The plots when changing to seconds, 120 seconds, and 300 seconds are shown. In general, the shorter the development time, the higher the residual film ratio for the same dose D is the same as in FIG. 1C. However, the value of the dose D at which the residual film ratio becomes almost zero is determined by the development time T
It is almost constant regardless of

Therefore, in order to completely remove the electron beam resist layer in the exposed area, a sufficiently high dose D must be given regardless of the development time. In the case of electron beam exposure, setting the dose D high means that the exposure time is extended and the time required for the lithography process is extended.

As a developing solution for the ZEP520A resist, in addition to the above-described ZEP-SD, xylene, butyl acetate, and the like are also known. However, each developing solution has low sensitivity and requires a long time for resist exposure. By using a compound represented by the general formula (2) such as benzoic acid as a developing solution for an electron beam resist such as ZEP520A, high sensitivity can be realized and the time required for development can be reduced. it can.

FIGS. 2A to 2E show an example of a three-layer resist process. As shown in FIG.
On the surface of the substrate 51, an electron beam positive type resist layer 52 such as ZEP520A manufactured by Zeon Corporation was rotated at a rotation speed of 4500 rpm.
The thickness is about 0.2 μm by spin coating. After spin coating the electron beam resist layer 52, baking is performed at 180 ° C. for 2 minutes.

Thereafter, an alkali-soluble layer 53 such as polydimethylglutarimide (PMGI) is formed on the electron beam resist layer 52 at a rotation speed of 3000 rpm to a thickness of about 0.5 μm.
Spin coat. After spin-coating the alkali-soluble layer 53, baking is performed at 180 ° C. for 2 minutes.

Subsequently, an electron beam positive resist layer 54 such as ZEP520A manufactured by Zeon Corporation is spin-coated on the alkali-soluble layer 53 at a rotation speed of 3000 rpm to a thickness of about 0.3 μm, and baked at 180 ° C. for 2 minutes. I do. In this way, the three-layer resist laminated structure 52, 53, 54
Create

After forming the three-layer resist laminated structure, the selected area is irradiated with the electron beam EB1. For example, exposure corresponding to the opening of the upper electron beam resist layer 54 is performed at an acceleration voltage of 50 kV.

Next, as shown in FIG. 2B, exposure corresponding to the opening of the lower electron beam positive resist layer 52 is performed using an electron beam EB2. For example, acceleration voltage 50k
Using the electron beam EB2 of V, exposure corresponding to an opening is performed on the lower electron beam positive resist layer 52 so as to overlap the exposure region for the upper electron beam positive resist layer 54.

As shown in FIG. 2C, the upper electron beam positive resist layer 54 is developed to form an opening 56. The development of the upper electron beam positive resist layer 54 is conventionally performed using, for example, ZEP-SD manufactured by Zeon Corporation, but in this embodiment, is performed using ethyl benzoate.

As shown in FIG. 2D, the alkali-soluble layer 53 exposed in the opening 56 of the upper electron beam positive resist layer 54 is exposed to tetramethylammonium hydroxide (NMD-TM, manufactured by Tokyo Ohka Co., Ltd.). Development is performed using an alkaline developer such as W). An opening 57 that extends further in the lateral direction from the opening 56 is formed.

As shown in FIG. 2E, the exposed region of the lower electron beam resist layer 52 is developed to form an opening 58 corresponding to the exposed region of the narrow electron beam EB2. In the prior art, development of the lower electron beam resist layer was performed using, for example, ZEP-SD manufactured by Zeon Corporation. However, in the embodiment of the present invention, the development can be performed using various developing solutions. .

For example, a compound represented by the general formula (2) such as ethyl benzoate may be used. Preferably,
A mixture of xylene, butyl acetate, methyl ethyl ketone and methyl isobutyl ketone (for example, ZEON Corporation) having lower sensitivity than the developing solution for the upper electron beam resist layer 54
P-SD) or the like. Further, a mixed solution of methyl isobutyl ketone and isopropyl alcohol (for example, ZMD-B manufactured by Nippon Zeon Co., Ltd.), which has been conventionally used as a rinsing liquid, may be used.

In the three-layer resist process, when the development of the upper electron beam positive resist layer 54 is performed with high sensitivity, the dose of the electron beam EB1 to the upper electron beam positive resist layer 54 shown in FIG. 2A is reduced. It becomes possible. Therefore, during exposure for the upper layer electron beam positive resist, it is possible to reduce the amount of exposure that the base electron beam positive resist layer 52 receives secondarily, and to reduce the influence thereof.

Referring to FIG. 2A, the case where the lower electron beam resist layer 52 has a thickness of 0.2 μm and the upper electron beam resist layer 54 has a thickness of 0.3 μm will be described as an example. The optimum exposure required for resolving a pattern having a line width (data length) of 0.6 μm in the upper electron beam resist layer 54 is 18 μC when ethyl benzoate is used as a developer and development is performed for 300 seconds. / Cm ² .

When ZEP-SD similar to the conventional one is used as a developing solution and development is performed for 30 seconds, the optimum exposure amount is 3
It becomes 0 μC / cm ² . This upper electron beam resist layer 54
Is also applied to the lower electron beam resist layer 52 almost as it is. In the case of the embodiment of the present invention, the dose of the secondary electron beam exposure received by the lower electron beam resist layer 52 can be reduced to about 60% of the conventional case.

The optimum exposure required for resolving a pattern having a line width (data length) of 0.2 μm on the lower electron beam resist layer 52 is 80 μC / cm ² .

For exposure of the upper electron beam resist layer 54, 30
If you make an electron beam exposure of the [mu] C / cm ^2, electron beam exposure for a lower electron beam resist layer will 50μC / cm ^2. When the electron beam exposure to the upper electron beam resist layer 54 is 18 μC / cm ² , the lower electron beam resist layer 5
2 can be 62 μC / cm ² .

As described above, by increasing the amount of electron beam exposure corresponding to a desired pattern and decreasing the amount of secondary electron beam exposure, the resolution of the electron beam resist layer 52 is improved and the opening shape is improved. Can be.

FIGS. 3A to 3D show experiments performed using a single electron beam resist layer to confirm this effect.

As shown in FIG. 3A, a ZEP520A manufactured by Zeon Corporation of Japan was used on
The electron beam positive resist layer 11 of μm was spin-coated.
After spin coating, baking was performed at 180 ° C. for 2 minutes. Subsequently, an electron beam EB1 corresponding to the electron beam exposure on the upper layer electron beam resist is applied to the electron beam resist layer 11
Was irradiated onto a wide area 12 having a line width of 1.2 μm. Note that this exposure area is 0.6 to 0.8 μm in an actual process.
However, in order to make it easier to understand the effect of EB1,
The experiment was conducted with a wider line width. The dose of the electron beam irradiation was carried out separately in cases of 18μC / cm ² and 30 .mu.C / cm ^2.

As shown in FIG. 3B, the exposure by the electron beam EB2 corresponding to the exposure area of the electron beam positive resist layer 11 is performed on the area 13 having a line width of 0.2 μm in the secondary exposure area 12. I did it. The dose of the electron beam exposure by the electron beam EB2 is 62 μC / cm ² when the dose by the electron beam EB1 is 18 μC / cm ² ,
50 when the dose of EB1 is 30 μC / cm ²
μC / cm ² .

As described above, in the sample corresponding to the embodiment of the present invention, 18 μC /
exposure cm ^2, subjected to exposure of 62μC / cm ² by an electron beam EB2, in the samples corresponding to the prior art,
30 .mu.C / cm ² out exposure by an electron beam EB1, exposure by the electron beam EB2 were performed in 50 .mu.C / cm ^2.

The electron beam resist layer 11 thus double-exposed was developed for 30 seconds using ZMD-B manufactured by Zeon Corporation, which is a mixed solution of methyl isobutyl ketone and isopropyl alcohol, as a developing solution. After the development, the substrate was rinsed with isopropyl alcohol for 20 seconds.

FIG. 3C shows the shape of an electron beam resist pattern exposed and developed according to the embodiment of the present invention. A region corresponding to the exposure by the electron beam EB2 is clearly removed, and the surface of the electron beam resist layer around the region is hardly deteriorated. Also, the width of the formed opening is close to the intended 0.2 μm.

FIG. 3D shows the shape of a sample which has been subjected to electron beam exposure and development according to the prior art. Although the exposure area by the electron beam EB2 was developed, the opening width was greatly widened. Further, the surface of the electron beam resist layer on both sides of the opening is severely deteriorated in a pleated shape.

As described above, when not only the intended electron beam exposure is performed on the single electron beam resist layer but also the secondary electron beam exposure is performed on the upper electron beam resist layer, Efficient development of the resist layer using ethyl benzoate, etc., reducing the amount of electron beam irradiation, reducing the effects of secondary irradiation areas, providing a high resolution, improved cross-sectional electron beam resist pattern Can be obtained.

After developing the electron beam positive type resist layer such as ZEP520A with ethyl benzoate, rinsing was carried out with ZMD-B (mixture of methyl isobutyl ketone and isopropyl alcohol) manufactured by Zeon Corporation as before. As a result, a residue was formed on the entire surface of the unexposed portion.

FIG. 4 shows a method of forming a resist pattern according to another embodiment of the present invention. As shown in FIG. 4A, an electron beam positive resist layer 2
2, alkali-soluble layer 23, electron beam positive resist layer 2
4 is formed, and the region 25 is exposed by an electron beam. This exposure is for the upper electron beam positive resist layer 24.

Thereafter, the electron beam positive resist layer 24 is developed using ethyl benzoate. The exposed area 25 of the electron beam positive resist layer 24 is developed with ethyl benzoate.

As shown in FIG. 4B, following the development step, the surface of the laminated resist structure is rinsed with a mixed solution of methyl ethyl ketone and methyl isobutyl ketone (for example, ZEP-SD manufactured by Zeon Corporation). For example, by rinsing for 20 seconds, a surface is obtained in which no residue is observed at all when ZMD-B is used as a rinsing liquid.

ZEP-SD is used as a developing solution in the prior art. By using ethyl benzoate as the developer, the amount of electron beam exposure is reduced, and after performing the desired development, rinsing with ZEP-SD does not cause deformation of the development area.

Subsequently, the alkali-soluble layer 23 is developed with an alkali developer to expose the lower electron beam resist layer. A desired region of the lower electron beam resist layer 22 is exposed to an electron beam, and development and rinsing are performed in the same manner as in the process described with reference to FIG.

Although the case of a three-layer resist structure has been described, similar results can be obtained when a single-layer electron beam resist layer having no lower electron beam positive resist layer 22 and no alkali-soluble layer 23 is used. It would be obvious.

FIG. 5 shows a method of forming a resist pattern for lifting off a T-type electrode according to another embodiment of the present invention.

As shown in FIG. 5A, the GaAs substrate 5
The surface of No. 1 was spin-coated with ZEP520A manufactured by Zeon Corporation at a rotation speed of 4500 rpm at a thickness of 0.2 μm,
Baking at 0 ° C. for 2 minutes. Subsequently, PMGI is rotated on the electron beam resist layer 52 at a rotation speed of 3000 rpm.
Is applied by spin coating at a thickness of 0.5 μm, and baked at 180 ° C. for 2 minutes. Further, ZEP520A manufactured by Zeon Corporation is rotated on the PMGI layer 53 at a rotation speed of 3000 rpm.
Then, spin coating is performed at a thickness of 0.25 μm and baking is performed at 180 ° C. for 2 minutes. Thus, a three-layer resist laminated structure is formed. An antistatic film (not shown) is applied on the three-layer resist laminated structure.

An electron beam EB having an acceleration energy of 50 keV
1 in a region having a data length of 0.8 μm and a dose of 40 μ / cm.
Irradiation at ² and electron beam exposure. After the EB exposure, the antistatic film is removed.

As shown in FIG. 5B, development was performed at room temperature for 180 seconds using ethyl benzoate as a developing solution.
The upper electron beam resist layer 54 is developed. An opening 56 is formed in the upper electron beam resist layer 54 by the development. After development, using a mixed solution of methyl isobutyl ketone and methyl ethyl ketone (for example, ZEP-SD manufactured by Zeon Corporation)
Rinse for 20 seconds at room temperature.

As shown in FIG. 5C, using the opening 56 formed in the upper electron beam resist layer 54 as a mask,
The underlying PMGI (alkali-soluble) layer 53 is developed with an alkali developer. For example, development is performed at room temperature for 30 seconds using tetramethyl ammonium hydroxide (NMD-W) manufactured by Tokyo Ohka. After the development, rinsing is performed using, for example, pure water. In this manner, an opening 57 having a wider width than the opening 56 is formed in the PMGI layer 53 in the lateral direction. The lower electron beam resist layer 52 is exposed at the bottoms of the openings 56 and 57.

As shown in FIG. 5D, the exposed lower electron beam resist layer 52 is exposed to an electron beam having a data length of 0.06 to 0.2 μm using an electron beam EB2. For example, at an acceleration energy of 50 keV and a data length of 0.0
Electron beam writing with a dose of 75 to 90 μC / cm ² is performed in a region of 8 μm.

As shown in FIG. 5E, a mixed solution of methyl isobutyl ketone and isopropyl alcohol (for example, ZMD-B manufactured by Zeon Corporation) was used as a developing solution for the lower electron beam resist layer 52 after the electron beam exposure. Perform development. After the development, rinsing is performed at room temperature for 20 seconds using, for example, isopropyl alcohol.

According to the above-described embodiment, an experiment was performed in which the data length of the opening, the development time, and the dose were changed, and the results were examined.

FIG. 6A shows the dependence of the opening length of the obtained lower resist layer on the development time. 0.06 μm, 0.08 μm, 0.1 μm,
The result when 0.2 μm is used is shown by a plot. The lower electron beam resist layer was exposed at a dose of 85 μC / cm ² . The upper electron beam resist layer was developed with benzoic acid.

FIG. 6B shows the dependence of the opening length of the obtained lower electron beam resist layer on the dose of the electron beam for the lower resist layer. The lower electron beam resist layer is made of ZM
Development was performed for 50 seconds using DB. As in FIG.
The data length for the opening is 0.06 μm, 0.08 μm, 0.
It was changed to 1 μm and 0.2 μm.

As is clear from FIGS. 6A and 6B,
The opening length obtained in the lower electron beam resist layer is determined by the development time,
Very low dependence on dose. Further, a stable opening length of 0.11 μm can be realized. According to the prior art, the minimum opening length obtained is about 0.15.
The opening length is significantly reduced as compared to the case of μm.

FIG. 7 shows a method of manufacturing a HEMT type semiconductor device according to an embodiment of the present invention. As shown in FIG. 7A, a heteroepitaxial layer is grown on the surface of the semi-insulating GaAs substrate 31 by metal organic chemical vapor deposition (MOCVD). First, a high-resistance GaAs layer 32 is grown to a thickness of about 300 nm on the surface of a semi-insulating GaAs substrate 31,
Non-doped InGaAs is formed thereon as an electron transit layer 33.
The layer is grown to a thickness of about 20 nm. On the electron transit layer 33,
As the electron supply layer 34, a Si-doped n-type AlGaAs layer is grown to a thickness of about 20 nm. Further, a Si-doped n ⁺ -type GaAs is formed on the electron supply layer 34 as a surface low-resistance layer 35.
An s layer is grown to a thickness of about 50 nm. Thus, HE
A heteroepitaxial layer for forming an MT element is formed.

After the epitaxial growth, oxygen is ion-implanted into a region surrounding the transistor region to form a semi-insulating region around the transistor to form an element isolation region 36.

As shown in FIG. 7B, the element isolation region 3
A pair of current extraction terminals 38 is formed in the transistor region 37 surrounded by 6. The current extraction terminal 38 includes, for example, an AuGe layer 38a having a thickness of 50 nm and a thickness of 300 nm.
Of the Au layer 38b. In this way,
A pair of ohmic source / drain electrodes is formed.

As shown in FIG. 7C, a three-layer resist laminated structure 52, 53, 54 is formed on the substrate on which the ohmic electrode 38 has been formed by the same process as in the above embodiment. The opening of the three-layer resist laminated structure is arranged in the middle of a pair of ohmic electrodes 38 for extracting current.

Thereafter, aluminum is vapor-deposited on the three-layer resist laminated structure. By the evaporation, the Schottky gate electrode 39a is formed in the opening of the three-layer resist laminated structure. An aluminum layer 39b is also deposited on the three-layer resist laminated structure.

As shown in FIG. 7D, the three-layer resist laminated structures 52, 53, 54 are removed by using a stripper. Three
The aluminum layer 39b on the layer resist laminated structure is lifted off at the same time. Thus, a HEMT having a T-shaped Schottky gate electrode 39a made of aluminum is formed.

FIG. 8A shows the H fabricated in this manner.
5 shows IV characteristics of EMT. FIG. 8B shows the characteristics of a HEMT manufactured by a conventional technique for comparison.

The HEMT shown in FIG. 8A had a gate length of 0.12 μm, and the HEMT shown in FIG. 8B had a gate length of 0.15 μm. According to an embodiment of the present invention,
It can be seen that a three-terminal device having excellent characteristics has been obtained.

It will be apparent to those skilled in the art that various semiconductor devices can be manufactured without being limited to the HEMT.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, although the case where the electron beam resist layer is formed of ZEP520A has been mainly described, the electron beam resist is not limited to this. Various electron beam resists containing the substance represented by the general formula (1) can be used.

[0091]

Embedded image . . . . (1)

The electron beam resist layer may be exposed with an energy beam such as X-rays. Various compounds represented by the general formula (2) could be used as a developer for the electron beam resist layer. It will be apparent to those skilled in the art that various other modifications, improvements, and combinations are possible.

[0093]

As described above, according to the present invention, the lithography process using the electron beam resist layer can be performed with high sensitivity. The resolution of a lithography process using a laminated electron beam resist structure can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view and a graph showing a method for forming a resist pattern according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method of forming a resist pattern according to another embodiment of the present invention.

FIG. 3 is a cross-sectional view and a sketch showing an experiment performed to verify the effect of the embodiment of the present invention and the result.

FIG. 4 is a cross-sectional view illustrating a method of forming a resist pattern according to another embodiment of the present invention.

FIG. 5 is a sectional view illustrating a method of forming a resist pattern according to another embodiment of the present invention.

FIG. 6 is a graph showing the results of an experiment performed to verify the effects of the embodiment of the present invention.

FIG. 7 is a sectional view showing main steps of a method for manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 8 is a graph showing characteristics of a semiconductor device manufactured according to another embodiment of the present invention in comparison with characteristics of a semiconductor device manufactured by a conventional manufacturing method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Undersubstrate 11 Electron beam positive resist layer 12 (EB irradiation) area 15 Developer 21 Undersubstrate 22 Electron beam positive resist layer 23 Alkali-soluble layer 24 Electron beam positive resist layer 31 Semi-insulating GaAs substrate 32 High resistance GaAs Layer 33 Electron transit layer 34 Electron supply layer 35 Surface low resistance layer 36 Element isolation region 37 Transistor region 38 Current extraction terminal 39a T-shaped Schottky gate electrode 51 GaAs substrate 52 Electron beam positive resist layer 53 Alkali-soluble layer 54 Electron beam positive Resist layer 56-58 opening EB electron beam

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Ei Yano 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Keiji Watanabe 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 Fujitsu Co., Ltd. (72) Inventor Takahisa Namiki 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture 1-1 Within Fujitsu Co., Ltd. (72) Koji Nozaki 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 Fujitsu Co., Ltd. (72) Inventor Miwa Igarashi 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Within Fujitsu Co., Ltd. Location Fujitsu Quantum Devices Co., Ltd. No. 1 Fujitsu Co., Ltd. (72) Inventor Mizuhisa Nihei 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa F-term in Fujitsu Co., Ltd. (Reference) 2H025 AA00 AA02 AA03 AB16 AC06 AD03 BF08 CB16 CB55 DA11 DA14 DA20 FA16 FA28 2H096 AA25 BA11 EA06 GA03 KA07 5F046 AA28 DA02 JA04 JA22 LA12 LA14 LA18 NA06

Claims (10)

[Claims] 1. A step of forming a resist layer containing the general formula (1) on an underlayer surface; . . . . (1) a step of irradiating the resist layer with an energy beam to expose the resist layer, and a step of developing the exposed resist layer with a developer containing the general formula (2). . . . . (2) A method for forming a resist pattern comprising: 2. The method according to claim 1, further comprising the step of rinsing the developed resist layer with a mixed solution of methyl ethyl ketone and methyl isobutyl ketone. 3. The method according to claim 1, wherein the general formula (2) is ethyl benzoate. 4. A step of forming a first electron beam resist layer on an underlayer surface; a step of forming an alkali-soluble layer on the first electron beam resist layer; A) forming a second electron beam resist layer comprising: . . . . (1) a step of exposing the second electron beam resist layer by irradiating an energy beam from above the second electron beam resist layer; and forming the exposed second electron beam resist layer by a general formula (2)
Developing with a developer containing: . . . . (2) A method for forming a resist pattern comprising: 5. The method according to claim 4, further comprising the step of rinsing the developed second electron beam resist layer with a mixed solution of methyl ethyl ketone and methyl isobutyl ketone. 6. The method according to claim 4, wherein the general formula (2) is ethyl benzoate. 7. The step of exposing the second electron beam resist layer, the step of exposing the first electron beam resist layer, and the step of exposing the second electron beam resist layer. Irradiating an energy beam to a second region in the first exposure region of the one electron beam resist layer to expose the first electron beam resist layer; and selectively exposing the second region of the first electron beam resist layer. 5. The method for forming a resist pattern according to claim 4, further comprising the step of: 8. A step of preparing a semiconductor substrate having a channel region and a pair of current extraction regions connected to the channel region; and (b) a first electron beam resist layer on the semiconductor substrate. Forming an alkali-soluble layer and a second electron beam resist layer in this order; and (c) forming the second electron beam resist layer to have a first width so as to cross a channel region between the pair of current extraction regions. (D) exposing the first electron beam resist layer with an energy beam having a second width smaller than a first width in the first region; and (e) exposing the first electron beam resist layer to the first region. Developing the two-electron beam resist layer with a first developer containing the general formula (2); . . . . (2) (f) removing the alkali-soluble layer below the opening formed in the second electron beam resist layer; and (g) developing the first electron beam resist layer with a second developer. A method for manufacturing a semiconductor device including: 9. The steps (e), (f), and (g) are steps of forming a narrow opening at the bottom and a wide opening at the top in the resist stack, and further forming an electrode layer on the resist stack with the opening formed. 9. The method of manufacturing a semiconductor device according to claim 8, further comprising the steps of: depositing; and removing the resist stack together with an electrode layer thereon. 10. The method according to claim 8, wherein the step (d) is performed between the steps (f) and (g).