JP2000037079A - PWM circuit - Google Patents

Abstract

(57) Abstract: A signal wave 16 serving as a command value is output based on a signal wave reference signal 17, and a pulse output from a PLL circuit 15 with the signal wave reference signal 17 as an input is set in advance. The output is counted by an up / down counter 23, a carrier wave 25 synchronized with the signal wave 16 is output, and the signal wave 16 and the carrier wave 25 are compared to determine the switching element of the inverter. Gate pulse 28
In the PWM circuit that outputs the signal, when the frequency division ratio is changed to change the frequency magnification of the carrier wave 25 and the signal wave 16, generation of an incorrect gate pulse is prevented. SOLUTION: A frequency division ratio set in advance is temporarily held in a first register 21 and is transferred to a second register 22 at a timing when a phase of a signal wave 16 output from a PLL circuit 15 is 0 degree to divide the frequency. By using the ratio, the continuity of the carrier wave 25 is maintained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PWM circuit used for controlling a switching element of a power converter such as a self-excited inverter device.

[0002]

2. Description of the Related Art In a self-excited inverter device of a power conversion system, an output voltage is controlled by a triangular wave comparison PWM.
(Pulse Width Modulation) method is generally used.
The triangular wave comparison PWM method uses a triangular wave as a carrier wave and a voltage command value as a signal wave, and determines the switching time of the switching element according to the magnitude of the carrier wave and the signal wave. The output of the inverter device is changed by changing the amplitude of the signal wave. The voltage can be controlled. When the carrier wave and the signal wave are asynchronous, and when the carrier wave frequency and the signal wave frequency are approaching, the signal wave and the sideband signal approach or a beat is generated, so that the characteristics of the inverter device are significantly deteriorated. Therefore, for example, by making the frequency of the carrier wave three times or nine times the frequency of the signal wave, the magnification of the frequency of the carrier wave and the frequency of the signal wave is kept constant, and the phase is maintained and synchronized by maintaining a predetermined difference. It is known that this problem can be avoided.

When the output frequency of the inverter device is changed, it is realized by changing the frequency of the signal wave. However, if the magnification of the carrier wave frequency and the signal wave frequency is always kept constant as described above, the output frequency is proportional to the frequency of the signal wave. And the carrier frequency goes up and down. In the power conversion system, the frequency of the carrier is equivalent to the switching frequency of the switching element.If the variable range of the frequency of the signal wave is wide, the switching frequency of the switching element is proportional to the frequency of the inverter device, that is, the frequency of the signal wave. It goes up and down. In particular, when the switching frequency of the switching element becomes abnormally high, the switching loss increases, which may lead to the destruction of the switching element. Therefore, in order to keep the switching frequency of the switching element substantially constant even when the frequency of the signal wave changes, it is necessary to switch the magnification with the carrier frequency according to the signal wave frequency.

A general configuration of an inverter device using a conventional triangular wave comparison PWM method is described in, for example, Technical Report No. 596 of the Institute of Electrical Engineers of Japan (July 1997). FIG. 16 shows a configuration of a conventional PWM circuit applied to a synchronous inverter device for synchronizing a carrier and a carrier wave. In the figure, reference numeral 1 denotes a PLL circuit which operates with a signal wave reference signal 3 including frequency and phase information serving as a basis of a PWM signal wave 2 as an input. PL
The L circuit 1 generates a pulse having a frequency which is twice as high as the frequency of the signal wave reference signal 3 and also outputs a phase reference signal 4 indicating a specific phase of the signal wave reference signal 3. Also,
Reference numeral 5 denotes a CPU which sets various control information and outputs a signal wave 2 serving as a voltage command with the signal wave reference signal 3 as an input.

A pulse output from the PLL circuit 1 is frequency-divided by a frequency divider 7 according to a frequency division ratio set in advance by a CPU 5 and held by a register 6, and its output is increased / decreased.
Input to the counter 8. The up / down counter 8 performs a down operation when the value of the counter performing the up operation reaches the upper limit predetermined value, and shifts to an up operation when the value of the down operation counter reaches the predetermined lower limit value.
Repeat countdown. Further, upon receiving the phase reference signal 4 from the PLL circuit 1, the counter value of the up / down counter 8 is forcibly set to a predetermined value set by the CPU 5 in advance and held by the phase register 9 at that timing. The above operation of the up / down counter 8 becomes a triangular wave which is the carrier wave 10 in the PWM circuit of the inverter device.

The signal wave 2 output from the CPU 5 is input to a voltage command register 11, and the signal wave 2 output from the voltage command register 11 and the carrier wave 10 output from the up / down counter 8 are sent to a comparator 12. Upon input, the comparator 12 operates to compare the value of the signal wave 2 with the value of the carrier wave 10 and output 1 or 0 depending on the magnitude. This output is the ON / O of the switching element of the inverter device.
It becomes a gate pulse 13 for performing FF control and controls the output of the inverter device. The frequency of the carrier 10 can be changed by changing the frequency division ratio of the frequency divider 7.
By setting the frequency division ratio held in the register 6, the frequency division ratio can be changed and the frequency of the carrier 10 of the inverter device can be arbitrarily changed.

The manner in which the carrier wave 10 is synchronized with the signal wave reference signal 3, that is, with the signal wave 2 in the PWM circuit configured as described above will be described with reference to FIG. FIG. 17 (a)
FIG. 17 shows the signal wave 2 serving as a voltage command output from the CPU 5 based on the signal wave reference signal 3 and the operation of the up / down counter 8 serving as the carrier 10.
17B shows the phase reference signal 4 and FIG. 17C shows the gate pulse 13 obtained by comparing the signal wave 2 and the carrier 10. Here, the number of bits of the up / down counter 8 is 12 bits, the upper limit predetermined value is 4095, and the lower limit predetermined value is 0. Further, the phase reference signal 4 output from the PLL circuit 1 is assumed to be output when the signal wave reference signal 3 is 0 °.
It is assumed that a pulse which is a 2 × 15 clock is also generated. Further, for example, the CPU 5 stores the division ratio 1/3 in the register 6 as the set value,
Is set to 2048.

When the phase reference signal 4 is received from the PLL circuit 1, the counter value of the up / down counter 8 is forcibly set to the value 2048 of the phase register 9, and the counting operation is continued from that value. The pulse output from the PLL circuit 1 passes through the frequency divider 7 having a frequency division ratio of 1/3, and is supplied to the up / down counter 8 by the signal wave reference signal 3 of 4096.
A pulse having a frequency of × 2 × 5 times is input. for that reason,
The up / down counter 8 repeats up / down counting five times between 0 and 4095, and when the phase reference signal 4 is received from the PLL circuit 1 next, the value of the up / down counter 8 is inevitably set to 2048. This means that the value of the up / down counter 8 automatically becomes 2048 regardless of whether the value of the phase register 9 is forcibly set or not.

By the above operation, the up / down counter 8 continues counting while keeping the relative phase difference with the signal wave reference signal 3 constant. That is, the carrier 10 whose frequency is five times the frequency of the signal wave reference signal 3 and whose phase difference is always 0 °.
Is obtained. A signal wave 2 serving as a voltage command is shown in FIG.
If the signal is output as shown in FIG. 17A, the signal wave 2 and the carrier wave 10 are compared by the comparator 12, and a gate pulse 13 can be obtained as shown in FIG. 17C. By the way, FIG.
As shown in FIG. 8, 0 is set in the phase register 9 in order to make the signal wave 2 a signal whose phase is shifted by 90 ° with respect to the carrier wave 10 with respect to the carrier wave 10. When the phase reference signal 4 is output from the PLL circuit 1, the value 0 of the phase register 9 is set in the up / down counter 8, so that the signal wave 2 is a signal obtained by shifting the phase of the carrier 10 by 90 °.

In order to prevent the frequency of the carrier 10 from increasing with the increase in the frequency of the signal wave reference signal 3, for example, the carrier wave 1 having a frequency five times that of the signal wave reference signal 3 is used.
The output of 0 is switched three times. This is CP
This can be realized by changing the frequency division ratio from U5 to the register 6 and changing the set value from 1/3 to 1/5. When 2048 is set in the phase register 9 and the frequency division ratio is set to 1/5 in the register 6, the PLL circuit 1 outputs 409 of the signal wave reference signal 3.
A pulse having a frequency of 6 × 2 × 3 is input to the up / down counter 8, and a PWM circuit having a carrier 10 having a frequency three times that of the signal reference signal 3 can be realized in the same manner.

[0011]

Since the conventional PWM circuit is configured as described above, in order to prevent the frequency of the carrier wave 10 from rising due to the rise of the frequency of the signal wave reference signal 3, the signal wave reference signal 3 As shown in FIG. 19, when the frequency magnification of the carrier 10 is changed with respect to the frequency, the setting of the frequency division ratio is changed at an arbitrary time, for example, at the time A, asynchronously with the carrier 10, and when the next phase reference signal 4 is received, up/
The value of the down counter 8 is not always 2048. Therefore, at this time, the value 2 of the phase register 9 is forcibly set.
When the up / down counter 8 is set to 048,
The carrier 10 becomes discontinuous as shown in the figure. as a result,
The gate pulse 13 also generates an incorrect pulse 14, and the ON / OF of the switching element of the inverter device is turned on
There is a problem that the reliability of the F control is deteriorated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and when changing the magnification of the frequency of a carrier wave and a signal wave, the continuity of the carrier wave is always maintained, and the gate pulse is not changed. It is an object of the present invention to provide a highly reliable PWM circuit that does not generate an illegal pulse.

[0013]

According to a first aspect of the present invention, there is provided a PWM circuit comprising: a first register for temporarily storing a frequency division ratio of a frequency divider set by a CPU; A second register is provided which inputs and holds the frequency ratio at the timing of the phase reference signal from the PLL circuit and reflects the frequency ratio on the frequency divider.

According to a second aspect of the present invention, there is provided a PWM circuit, comprising: a FIFO capable of holding a plurality of frequency division ratios of a frequency divider set by a CPU; and a phase reference signal from a PLL circuit as an input. Controlling the timing of sequentially reflecting the frequency division ratio held in the frequency divider on the frequency divider
And a control circuit.

According to a third aspect of the present invention, in the PWM circuit, at the timing of the phase reference signal from the PLL circuit,
The division ratio is input from the CPU to the register.

According to a fourth aspect of the present invention, in the PWM circuit, a counter output of the PLL circuit is input to a CPU, and a predetermined value is set in an up / down counter based on phase information corresponding to the counter output. , And the timing of inputting the frequency division ratio from the CPU to the register.

According to a fifth aspect of the present invention, there is provided a PWM circuit, comprising: a frequency detector for inputting a pulse from a PLL circuit to detect a frequency of the pulse; And a dividing ratio table for searching and outputting a dividing ratio corresponding to the above. The dividing ratio output from the dividing ratio table is input to a register at the timing of the phase reference signal from the PLL circuit. Things.

According to a sixth aspect of the present invention, in the PWM circuit according to any one of the first to fifth aspects, the frequency divider is a rate multivibrator.

According to a seventh aspect of the present invention, there is provided a PWM circuit for outputting a signal wave as a command value based on a signal wave reference signal inputted from the outside and setting control information.
U and a PLL that receives the signal wave reference signal as input, and outputs a pulse whose frequency is a multiple of the frequency of the signal wave reference signal and a phase reference signal indicating that the signal wave reference signal has a specific phase. A counter that counts pulses output from the PLL circuit and resets the counter value at the timing of the phase reference signal from the PLL circuit; and a plurality of types that have different frequency magnifications from the signal wave reference signal. A carrier wave pattern is stored for each address consisting of the counter output and identification information corresponding to the type of the carrier wave pattern, and a desired carrier wave is output according to the identification information set in advance by the CPU.
OM, a first register for temporarily holding the identification information set by the CPU, and the identification information once held at the timing of the phase reference signal from the PLL circuit and holding the same. And a second register for reflecting the carrier wave and the signal wave, and turning on / off the switching element of the power converter according to the magnitude of the comparison.
And a comparator that outputs a switching signal for performing F control.

A PWM circuit according to claim 8 of the present invention is a PWM circuit for outputting a signal wave as a command value based on a signal wave reference signal input from the outside and setting control information.
U and a PLL that receives the signal wave reference signal as input, and outputs a pulse whose frequency is a multiple of the frequency of the signal wave reference signal and a phase reference signal indicating that the signal wave reference signal has a specific phase. A counter that counts pulses output from the PLL circuit and resets the counter value at the timing of the phase reference signal from the PLL circuit; and a plurality of types that have different frequency magnifications from the signal wave reference signal. The carrier wave pattern is stored together with the magnification switching timing data at an address consisting of the counter output and the identification information corresponding to the type of the carrier wave pattern, and a desired one is obtained by the identification information set in advance by the CPU. ROM for outputting a carrier wave together with the timing data, and the identification information set by the CPU are temporarily stored. A first register, a second register for inputting and holding the identification information once held at the timing of the generation of the timing data from the ROM, and reflecting the information on the ROM; And a comparator that outputs a switching signal for performing ON / OFF control of the switching element of the power converter according to the magnitude of the comparison.

According to a ninth aspect of the present invention, there is provided a PWM circuit which generates a pulse which becomes an output of the circuit at a frequency which is twice as high as that of a signal wave reference signal inputted from the outside to the circuit, and A counter that counts
A phase comparator that compares the phase of the output signal of the counter and the signal wave reference signal, and outputs a voltage corresponding to the phase difference;
And a loop filter for smoothing the output of the phase comparator and inputting the output signal to the voltage controlled oscillator.
Circuit, a CPU for outputting a signal wave serving as a command value based on the signal wave reference signal and setting control information, and a plurality of types of carrier wave patterns having different frequency magnifications from the signal wave reference signal, A ROM that stores a counter output and an address including identification information corresponding to the type of the carrier wave pattern, and that outputs a desired carrier according to the identification information set in advance by the CPU;
And a first register for temporarily storing the identification information set in step (1), and the once-held identification information are input and held by timing control based on phase information from the counter of the PLL circuit, and are reflected in the ROM. A second register for comparing the carrier wave and the signal wave, and turning on / off a switching element of the power converter according to the magnitude of the comparison.
And a comparator that outputs a switching signal for performing control.

The PWM according to claim 10 according to the present invention.
The circuit includes a voltage-controlled oscillator that generates a pulse to be output from the circuit at a frequency that is twice as high as a signal wave reference signal input to the circuit from the outside, a counter that counts the pulses, and a counter output that is set in advance. A frequency divider that divides the frequency by the held frequency division ratio, a phase comparator that compares a phase of an output signal of the frequency divider with the signal wave reference signal, and outputs a voltage corresponding to a phase difference; A PLL circuit having a loop filter for smoothing the output of the phase comparator and inputting the output signal to the voltage-controlled oscillator; and outputting a signal wave serving as a command value based on the signal wave reference signal and controlling the control information. The CPU that performs the setting and the basic pattern of the carrier wave are stored.
A ROM that counts the basic pattern at a predetermined number of times with the counter output of the L circuit as an input and outputs a desired carrier, and compares the carrier with the signal to compare the magnitude of the signal with the signal. ON / O of switching element
A comparator that outputs a switching signal for performing FF control;
It has.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration of a PWM circuit according to Embodiment 1 of the present invention. In the figure, reference numeral 15 denotes a PLL circuit, which operates with a signal wave reference signal 17 including frequency and phase information serving as a basis of a PWM signal wave 16 as an input. PLL circuit 1
In step 5, a pulse having a frequency which is twice the frequency of the signal wave reference signal 17 is generated, and a phase reference signal 18 indicating a specific phase of the signal wave reference signal 17 is also output. Also,
Reference numeral 19 denotes a CPU which sets various control information and outputs a signal wave 16 serving as a voltage command with the signal wave reference signal 17 as an input.

The pulse output from the PLL circuit 15 is
The frequency is divided by the frequency divider 20 according to the frequency division ratio set in advance by the CPU 19. This frequency division ratio is set by the CPU 19 and once held in the first register 21, and then the second register 2 is synchronized with the phase reference signal 18 from the PLL circuit 15.
2 and is reflected as the frequency division ratio of the frequency divider 20.
The pulse divided by the frequency divider 20 is input to the up / down counter 23. The up / down counter 23 performs a down operation when the value of the counter operating up reaches a predetermined upper limit value, and starts an up operation when the value of the counter operating down reaches a predetermined lower limit value. repeat. Further, upon receiving the phase reference signal 18 from the PLL circuit 15, the counter value of the up / down counter 23 is
It is forcibly set to a predetermined value set at 19 and held at the phase register 24. The operation of the up / down counter 23 becomes a triangular wave which is the carrier wave 25 in the PWM circuit of the inverter device.

The signal wave 16 output from the CPU 19 is input to a voltage command register 26, and the voltage command register 26
Is input to the comparator 27, and the comparator 27 compares the value of the signal wave 16 with the value of the carrier wave 25, When the signal wave 16 is larger than the carrier wave 25, it outputs 1 and when it is smaller, it outputs 0. This output is the output of the switching element of the inverter device.
It becomes a gate pulse 28 as a switching signal for performing N / OFF control, and controls the output of the inverter device.

The frequency of the carrier wave 25 can be changed by changing the frequency division ratio of the frequency divider 20. The frequency division ratio is set by the CPU 19 and is temporarily stored in the first register 21. Is actually used as a frequency dividing ratio.
Is reflected when the phase reference signal 18 is received and transferred to the second register 22. This division ratio is
By changing the frequency at 19, the frequency of the carrier 25 of the inverter can be arbitrarily changed. The original purpose of the change of the frequency division ratio is to prevent the frequency of the carrier wave 25 from increasing due to the increase in the frequency of the signal wave reference signal 17, that is, to keep the carrier wave 25 constant regardless of the frequency of the signal wave reference signal 17. The frequency is set within the range, but can be achieved by changing to a predetermined frequency division ratio in the same manner as the above method.

In the PWM circuit configured as described above, the carrier wave 25 is used as the signal wave reference signal 17, that is, the signal wave 1
6 will be described with reference to FIG. FIG. 2 (a)
FIG. 2B shows the signal wave 16 serving as a voltage command output from the CPU 19 based on the signal wave reference signal 17 and the operation of the up / down counter 23 serving as the carrier wave 25. FIG. FIG. 2C shows a gate pulse 28 obtained by comparing the signal wave 16 and the carrier wave 25 with the phase reference signal 18. Here, the number of bits of the up / down counter 23 is 12 bits, the upper limit predetermined value is 4095, and the lower limit predetermined value is 0. PLL circuit 1
5 is the signal reference signal 1
It is assumed that the signal is output when 7 is 0 °, and that a pulse which is 4096 × 2 × 15 times the clock of the signal wave reference signal 17 is also generated. Further, for example, the CPU 19 sets 2048 in the phase register 24 and further sets a frequency division ratio of 1/3, and this frequency division ratio is held in the second register 22 and the frequency divider 20 generates the frequency division ratio of 1 / 3
It works on

When the phase reference signal 18 is received from the PLL circuit 15, the counter value of the up / down counter 23 is forcibly set to the value 2048 of the phase register 24, and the counting operation is continued from that value. A pulse output from the PLL circuit 15 passes through a frequency divider 20 having a frequency division ratio of 1/3, and a pulse having a frequency of 4096 × 2 × 5 times the signal wave reference signal 17 is supplied to an up / down counter 23. Is entered. Therefore, the up / down counter 23 repeats up / down counting five times between 0 and 4095, and when the phase reference signal 18 is received next from the PLL circuit 15, the up / down counter 23 necessarily starts counting up. The value will be 2048. This means that the value of the up / down counter 23 is automatically 2048 regardless of whether the value of the phase register 24 is forcibly set or not.

With the above operation, the up / down counter 23 continues counting while keeping the relative phase difference with the signal wave reference signal 17 constant. That is, a carrier wave 25 having a frequency five times that of the signal wave reference signal 17 and a phase difference of 0 ° is always obtained. When the signal wave 16 serving as a voltage command is output as shown in FIG. 2A, the comparator 27 compares the signal wave 16 with the carrier wave 25, and as shown in FIG. Can be obtained.

When the frequency division ratio is switched, for example, A in FIG.
At this point, the CPU 19 changes the frequency division ratio from 1/3 to 1/5. However, the frequency division ratio is temporarily held in the first register 21 and does not immediately become a new frequency division ratio used for the frequency divider 20. At the time B when the next phase reference signal 18 is received, the first frequency division ratio is set. The value of the register 21 is transferred to the second register 22, and the frequency division ratio used for the frequency divider 20 becomes １ ／ for the first time. That is, after the setting of the frequency division ratio is changed by the CPU 19, the frequency divider 20 operates at the frequency division ratio before the change until the next time the phase reference signal 18 is received from the PLL circuit 15; When the value of the phase register 24 is forcibly set in the up / down counter 23 by the signal 18, the value of the up / down counter 23 is necessarily 20.
48. At this time, since the frequency division ratio used for the frequency divider 20 becomes new, the up / down counter 23
Counting is continued with a pulse that has been frequency-divided at a new frequency division ratio from 8. As described above, since the carrier 25 obtained by the operation of the up / down counter 23 is continuous, no illegal pulse is generated even in the gate pulse 28.

Embodiment 2 In the first embodiment, the frequency divider 20 uses the frequency division ratio 1 / n (n: integer). However, as shown in FIG. 3, a rate multivibrator 29 is used as the frequency divider. . The rate multivibrator 29 changes the frequency of the input pulse to m / n.
(M, n: integer). In the case of the 4-bit rate multivibrator 29, the frequency is m / 16, and when the carrier wave 25 having a frequency three times, five times and seven times the frequency of the signal wave reference signal 17 is generated, the CPU 1
This can be realized by setting 3, 5 and 7 as m according to 9.

In the frequency divider 20 having a normal frequency division ratio of 1 / n as used in the first embodiment, for example, by switching the frequency division ratio, the signal wave reference signal 17 is tripled, five times and seven times.
In the case of generating the carrier wave 25 of double frequency, respectively, P
The LL circuit 15 must generate a pulse having a frequency higher than the least common multiple of the magnification (3, 5, 7) required to generate the carrier wave 25. Since the least common multiple of 3, 5, and 7 is 105, a 12-bit up / down
In the case of the counter 23, 4096 × 2 of 25 frequencies of the carrier wave
It is necessary to generate a pulse having a frequency of × 105 from the PLL circuit 15. The frequency of the signal wave reference signal 17 is 60
In the case of Hz, the PLL circuit 15 needs to generate a pulse of as much as 50 MHz. At this time, when the carrier wave 25 has a frequency three times, five times and seven times the frequency of the signal wave reference signal 17, the frequency division ratios are set to 1/35, 1/21 and 1/15, respectively.

On the other hand, in this embodiment, since the rate multivibrator 29 is used as the frequency divider, for example, in the case of the 4-bit rate multivibrator 29, the input frequency is set to m / 16. Therefore, the output from the PLL circuit 15 need only output a pulse having a frequency of 4096 × 2 × 16 times. Signal wave reference signal 17 is 60H
In the case of z, the frequency of the output pulse from the PLL circuit 15 is 7.7 MHz. By using the rate multivibrator 29 as the frequency divider in this manner, the effect of preventing the generation of the illegal pulse of the gate pulse 28 and the frequency of the signal in the circuit can be suppressed similarly to the first embodiment. Therefore, it is possible to suppress the occurrence of an EMC problem due to the influence of noise, and it is possible to easily design a printed wiring board.

Embodiment 3 Next, a PWM circuit according to a third embodiment of the present invention will be described with reference to FIG. In the first embodiment, the frequency division ratio of frequency divider 20 is set to CP
In the present embodiment, when the setting is made in U19, the data is temporarily stored in the first register 20, and then transferred to the second register 22, the change timing of the frequency division ratio and the transition of the switching are known in advance. FIFO (First In First Out) without using the first and second registers 21 and 22
The frequency division ratio of the frequency divider 20 is set in advance by the CPU 19 in accordance with the switching transition and stored in advance.
Further, by providing the FIFO control circuit 31 to generate the change timing of the frequency division ratio, the frequency division ratio is automatically output from the FIFO 30 and changed in a preset order. When the FIFO control circuit 31 receives the phase reference signal 18 output from the PLL circuit 15 as an input and generates the change timing, the division ratio is changed when the phase reference signal 18 is generated. Since the carrier 25 is continuous as in the case of
Can prevent the generation of illegal pulses. Further, the CPU 19 only performs initial setting at the time of starting the apparatus, and thereafter, a PWM circuit in which the frequency division ratio is automatically changed can be realized, and the load on the CPU 19 is reduced.

Embodiment 4 FIG. Next, a PWM circuit according to a fourth embodiment of the present invention will be described with reference to FIG. As shown in the figure, a phase reference signal 18 output from the PLL circuit 15 is input to a CPU 19. The frequency divider 20 divides the frequency of the pulse output from the PLL circuit 15 using the frequency division ratio set in advance by the CPU 19 and held by the register 32. When it is necessary to change the magnification of the carrier wave reference signal 17 with respect to the frequency of the carrier wave 25 frequency, the CPU 19 receives the phase reference signal 18 generated from the PLL circuit 15 as an interrupt signal, Is input to the register 32. In this embodiment, when the interrupt processing time of the CPU 19 is sufficiently shorter than the operation of the carrier 25,
After receiving the phase reference signal 18 from the PLL circuit 15 as an interrupt signal, the frequency division ratio is immediately input to the register 32, and the effect can be obtained when the phase reference signal 18 can be used in the frequency divider 20 almost at the time of generation. Thus, the carrier wave 25 becomes continuous as in the first embodiment, and the occurrence of an illegal pulse of the gate pulse 28 can be prevented. Further, unlike the first embodiment, there is no need to have two registers for setting the frequency division ratio, and only one register 32 is required, so that the circuit configuration can be simplified.

Embodiment 5 Next, a PWM circuit according to a fifth embodiment of the present invention will be described with reference to FIG. In general, the PLL circuit 15 is
A voltage-controlled oscillator 33 for generating a pulse having a frequency twice as high as the signal wave reference signal 17 input to the
A counter 34 for counting pulses output from
The signal output from the counter 34 and the signal wave reference signal 17 are compared in phase with each other, and a phase comparator 35 that outputs a voltage corresponding to the phase difference, and the output of the phase comparator 35 is smoothed. A loop filter 36 for inputting an output signal to the voltage controlled oscillator 33 is provided.

By the way, the signal reference signal 1 of the carrier 25
7 is changed, the carrier 25 before and after the change is compared by making the phase of the signal wave reference signal 17 0 ° and making the value of the up / down counter 23 coincide with each other. There is a phase where the values of 23 coincide and the gradient directions also coincide. As will be described in detail later in an eighth embodiment, at least 0 ° and 180 ° of the signal wave reference signal satisfy this condition. At this time, the frequency division ratio is switched to change the frequency of the carrier wave 25 with respect to the signal wave reference signal 17. Even if the magnification is changed, continuity of the carrier wave 25 can be ensured. Further, the phase satisfying the above condition can be calculated in advance by a combination of the magnification of the frequency of the carrier wave 25 with respect to the signal wave reference signal 17 before and after the change.

In this embodiment, the output of the counter 34 in the PLL circuit 15 is input to the CPU 19. The value of the counter 34 in the PLL circuit 15 matches the phase of the signal wave reference signal 17. For example, if the counter 34 has 12 bits, if the value of the counter 34 is 0, the signal wave reference signal 17 becomes 0 °. The value of the counter 34 and the phase of the signal wave reference signal 17 correspond to 1: 1 such that the angle of 2048 is 180 °. Therefore, the counter 34
By inputting the output to the CPU 19, the phase of the signal wave reference signal 17 can be detected. Therefore, the timing calculated by the CPU 19 as described above is a timing calculated and set in advance as described above so that the continuity of the carrier wave 25 can be ensured. Change the circumference ratio. As a result, the carrier 25 is continuous and no illegal pulse is generated. The timing at which the value of the phase register 24 is forcibly set in the up / down counter 23 when the signal wave reference signal 17 has a specific phase is also controlled by the CPU 19 capable of detecting the phase of the signal wave reference signal 17. .

In this embodiment, the signal wave reference signal 17
Since the division ratio can be changed even at a timing other than 0 °, the timing at which the division ratio can be changed increases,
The magnification of the frequency of the carrier wave 25 with respect to the signal wave reference signal 17 can be changed efficiently. Further, unlike the first embodiment, there is no need to have two registers for setting the frequency division ratio, and only one register 32 is required, so that the circuit configuration can be simplified.

Embodiment 6 FIG. Next, a PWM circuit according to Embodiment 6 of the present invention will be described with reference to FIG. As described above, the original purpose of the change in the division ratio is to prevent the frequency of the carrier wave 25 from increasing with the increase in the frequency of the signal wave reference signal 17, that is, regardless of the frequency of the signal wave reference signal 17, the carrier 25 Is always within a certain range. Therefore, there is a 1: 1 relationship between the frequency of the signal wave reference signal 17 and the frequency magnification of the carrier wave 25 with respect to the signal wave reference signal 17, and it is extremely easy to calculate it in advance. That is, the frequency division ratio of the frequency divider 20 to the frequency of the signal wave reference signal 17 can be determined to be 1: 1.

In this embodiment, the pulse detector 37 receives a pulse from the PLL circuit 15 and detects the frequency of the pulse. The frequency detector 37 has a 1: 1 relationship as described above.
A memory such as a ROM for storing the relationship between the frequency of the signal wave reference signal 17 and the frequency division ratio of the frequency divider 20 as a frequency division ratio table 38 is provided, and a pulse output from the PLL circuit 15 is supplied to the frequency divider 20. The frequency is input to the frequency detector 37, and the output is input to the frequency division ratio table 38 to output the frequency division ratio. Since the frequency of the pulse output from the PLL circuit 15 and the frequency of the signal wave reference signal 17 are in a fixed proportional relationship, the frequency of the pulse is
The frequency division ratio corresponding to the frequency of the signal wave reference signal 17 can be selected by retrieving the frequency division ratio data corresponding to the pulse frequency from the frequency division ratio table 38. When the phase reference signal 18 is generated from the PLL circuit 15 after this frequency division ratio is selected, the frequency division ratio selected in the frequency division ratio table 38 is transferred to the register 32 at that timing, and the frequency divider 20 It is reflected as a division ratio. At the same time, a predetermined value set in advance by the CPU 19 and held in the phase register 24 is forcibly up / down.
It is set in the counter 23, and the counting operation is continued from the value.

In this embodiment, as in the first embodiment, the carrier wave 25 is continuous, so that the generation of an illegal pulse of the gate pulse 28 can be prevented and the CPU 1
9 is a frequency division ratio, that is, a signal wave reference signal 1 of the carrier wave 25.
Since it is not necessary to control the magnification of the frequency with respect to 7, and the frequency of the carrier wave 25 can be automatically kept within a certain range, the load on the CPU 19 is greatly reduced.

It should be noted that Embodiments 3 to 6 above are described.
Also, the rate multivibrator 29 can be used for the frequency divider 20 by applying the second embodiment, and the frequency of the signal in the circuit can be suppressed low. Generation can be suppressed,
Effects such as easy design of the printed wiring board can be obtained.

Embodiment 7 FIG. Next, a PWM circuit according to a seventh embodiment of the present invention will be described with reference to FIG. In the first to sixth embodiments, the frequency divider 20 and the up / down counter 23 are used. However, in this embodiment, the mere up-only or down-only counter 3 is used.
9 and the one in which the carrier wave patterns 41a and 41b are stored in the ROM 40 are used. In the counter 39, the PLL circuit 1
The pulse output from 5 is input and counted, and this counter value is reset at the timing of the phase reference signal 18 from the PLL circuit 15. A plurality of types of carrier wave patterns 41 having different magnifications from the signal wave reference signal 17 are stored in the ROM 40.
a, 41 b are the output of the counter 39 and the carrier wave pattern 41.
a and 41b are respectively stored in addresses composed of identification information corresponding to the types.

For example, it is assumed that carrier patterns 41a and 41b three times and five times the signal wave reference signal 17 are stored in the ROM 40 in advance as shown in FIG. RO
It is assumed that M40 has a 13-bit address and 12-bit data, and addresses 0H (hexadecimal 0) to 0F
At address FFH, five times the signal wave reference signal 17, 1000H
From the address to the address 1FFFH, triple data of the carrier 25 (carrier patterns 41a and 41b) are stored. Also, the PLL circuit 15 outputs 409 of the signal wave reference signal 17.
It is set to generate six times the frequency. Counter 39
Output is 12 bits (000H to FFFH), and R
The upper one bit address is assigned to the lower address of the OM 40, and the identification information 0 or 1 corresponding to the type of the carrier wave patterns 41a and 41b set in advance by the CPU 19.
Assign. Since the counter 39 is 12 bits, 000
Count from H to FFFH is repeated.

The identification information is set in advance by the CPU 19, and once stored in the first register 42, is transferred to the second register 43 upon receiving the phase reference signal 18 from the PLL circuit 15, and is stored in the ROM 40. Will be reflected. If a carrier 25 that is five times as large as the signal wave reference signal 17 is required, C
The PU 19 sets 0 as identification information, and temporarily holds the value in the first register 42. When the value of the second register 43 becomes 0 at the timing of the phase reference signal 18, the data from the address 0000H to the address 0FFFH of the ROM 40 is repeatedly output using the output of the counter 39 as an input. As a result, a carrier wave 25 having a period five times that of the signal wave reference signal 17 can be obtained. Phase reference signal 18
Is input, the counter 39 is reset to 000H. However, since the counter 39 has 12 bits and the frequency of the output pulse from the PLL circuit 15 is 4096 times the signal wave reference signal 17, the phase reference signal 18 The counter value automatically becomes 000H when the phase reference signal 18 is automatically input regardless of whether or not it is input.

In order to prevent an increase in the frequency of the carrier wave 25 due to an increase in the frequency of the signal wave reference signal 17, the output of the carrier wave 25 whose frequency is five times that of the signal wave reference signal 17 is reduced to three times. If it is necessary to switch, the CPU
19, the identification information is set to 1, and 1 is temporarily held in the first register 42. However, immediately this identification information 1
Is not part of the read address of the ROM 40, and P
At the timing when the phase reference signal 18 is received from the LL circuit 15, the value of the first register 42 is transferred to the second register 43 and the counter 39 is reset, so that the counter value becomes 000H. At this time, ROM4
The upper one bit of the read address of “0” becomes “1”. Therefore, after that, from ROM 40, it is 1F from address 1000H.
The data at the address FFH is repeatedly output.
That is, the carrier wave 2 having a frequency three times that of the signal wave reference signal 17
5 can be generated.

In this embodiment, when the magnification of the frequency of the carrier wave 25 with respect to the signal wave reference signal 17 is switched from 5 to 3, the read address of the ROM 40 is set to FFFH.
Is next to 1000H, so that the carrier 25 is continuous. Also, even if you switch from 5 times to 3 times,
Since the actual switching is performed at the time when the lower address of the ROM 40 is 000H, that is, at the start address of the carrier patterns 41a and 41b, the carrier 25 is continuous. When it is desired to make the phase difference between the carrier wave 25 and the signal wave 16 90 ° with respect to the carrier wave 25, it can be realized by using a ROM 40 as shown in FIG. 10, and by changing the data stored in the ROM 40, an arbitrary phase difference can be obtained. Obtainable.

In this embodiment, as in the first embodiment, the carrier wave 25 is continuous, and the occurrence of an illegal pulse of the gate pulse 28 can be prevented. Also, the triple frequency data (carrier pattern 41a) and the five times frequency data (carrier pattern 41b) are both 1000H, that is, 409.
6 is stored in the address space. The carrier patterns 41a and 41b of any magnification frequency are the same 1000H.
In this case, the PLL circuit 15 only needs to generate a pulse having a constant frequency as low as 4096 times the signal wave reference signal 17 from the PLL circuit 15, so that the frequency of the signal in the circuit can be significantly reduced. In addition, it is possible to suppress the occurrence of the EMC problem due to the influence of noise, and to facilitate the design of the printed wiring board.

In this embodiment, since the carrier patterns 41a and 41b are two patterns having a frequency of three times and five times, the identification information set and held by the CPU 19 is one.
Although it was bit data, for example, in the case of 8 patterns, 3
Bit data may be set. When the combination of the carrier patterns 41a and 41b is changed, the combination can be easily changed by replacing the ROM 40 with the necessary carrier pattern.

Embodiment 8 FIG. Next, a PWM circuit according to an eighth embodiment of the present invention will be described with reference to FIG. In the present embodiment, the carrier wave patterns 41a and 41b having different frequency magnifications from the signal wave reference signal 17 in the seventh embodiment are stored in the ROM together with the switching command data 44 as the magnification switching timing data.
The identification information stored in the CPU 40, set in advance by the CPU 19, and held once in the first register 42 is the timing at which the switching command data 44 is generated from the ROM 40.
The data is transferred to the second register 43 which is reflected on the OM 40.

Carrier wave pattern 4 stored in ROM 40
Assuming that 1a and 41b are the same as in the seventh embodiment,
Comparing the two carrier wave patterns 41a and 41b, as shown in FIG. 12, there are always some places where the lower 12 bits of the ROM 40 address are the same and the data is the same. Among them, there are places where the direction of the gradient further satisfies the condition that the gradient direction is the same, that is, both gradients are upward or both gradients are downward. Two carrier wave patterns 41a, 41
Regardless of the combination of b, in the carrier wave patterns 41a and 41b of the carrier wave 25 synchronized with the signal wave 16, at least the lower 12 bits of the ROM 40 address are 000H and 800H, the address and the data match, and The gradient directions match. That is, at least 0 ° and 180 ° of the signal wave reference signal 17 satisfies this condition, and the determination data as to whether this condition is satisfied is used as the switching command data 44 as the carrier wave pattern 41.
One bit is added to the ROM 40 in addition to the data of a and 41b, and when the above condition is satisfied, a value of 1 is stored in the corresponding address, and a value of 0 is stored in the other address. In FIG. 12, only when the switching command data 44 is 1 (hereinafter, referred to as when the switching command data 44 is generated), it is indicated by ↑.

As described above, when the lower 12 bits of the address and the data of the ROM 40 coincide with each other and the gradient directions coincide, that is, when the switching command data 44 is generated, the magnification of the frequency with respect to the signal wave reference signal 17 is changed. However, the continuity of the carrier wave 25 can be secured and the gate pulse 2
8 can be prevented from being generated. Such an address can be calculated in advance and stored in the ROM 40 by a combination of the magnification of the frequency of the carrier wave 25 with respect to the signal wave reference signal 17 before and after the change. In this embodiment, the carrier wave patterns 41a, 41a set in advance by the CPU 19 and once held in the first register 42 are used.
The identification information (0 or 1) corresponding to the type b is stored in the ROM
At the time of generation of the switching command data 44 output from the
In this case, the continuity of the carrier wave 25 can be ensured as described above, and the effect of preventing the generation of an illegal pulse of the gate pulse 28 can be obtained.

In the seventh embodiment, even if the CPU 19 changes the type of the carrier wave patterns 41a and 41b at an arbitrary timing, the phase reference signal 17
Since it occurs only once in 0 °, the signal wave 16 has a maximum length of 36
Only with a time delay of 0 ° is the carrier pattern 41a,
41b may not be switched. However, in this embodiment, since the switching command data 44 is generated at least at 0 ° and 180 °, the same effect as that of the seventh embodiment can be obtained, and the CPU 19 can be arbitrarily selected.
Changes the types of the carrier patterns 41a and 41b,
With a delay of only 180 ° at worst, high-speed switching becomes possible. Further, depending on the combination of the carrier wave patterns 41a and 41b, there are two or more points within 360 ° where the condition is satisfied, so that the switching can be performed in a shorter time, and the frequency magnification of the carrier wave 25 with respect to the signal wave reference signal 17 can be changed. However, it can be performed quickly and efficiently.

Embodiment 9 FIG. Next, a PWM circuit according to a ninth embodiment of the present invention will be described with reference to FIG. In the seventh embodiment, the pulses output from the PLL circuit 15 are counted by the counter 39. In the present embodiment, the counter 34 inside the PLL circuit 15 is used, and the output of the counter 34 is input to the ROM 40.
The PLL circuit 15, as described in the fifth embodiment,
Signal wave reference signal 1 externally input to PLL circuit 15
A voltage-controlled oscillator 33 for generating a pulse having a frequency which is a multiple of 7, a counter 34 for counting the pulses output from the oscillator 33, and the phase of the signal output from the counter 34 and the signal wave reference signal 17 , And outputs a voltage corresponding to the phase difference, and a loop filter 36 that smoothes the output of the phase comparator 35 and inputs the output signal to the voltage controlled oscillator 33. You.

In the PLL circuit 15 having such a configuration, the PL
The counter 34 in the L circuit 15 has the same function as the counter 39 used in the seventh embodiment. PLL circuit 1
The value of the counter 34 inside 5 coincides with the phase of the signal wave reference signal 17. For example, if the counter 34 has 12 bits, the signal wave reference signal 17
Is 0 ° and 2048 is 180 °, so that the value of the counter 34 and the phase of the signal wave reference signal 17 correspond to 1: 1. Therefore, since the phase of the signal wave reference signal 17 can be detected from the output of the counter 34, the identification information corresponding to the types of the carrier wave patterns 41a and 41b set in advance by the CPU 19 and once held in the first register 42 is stored in the second register. The transfer timing to the counter 43 is controlled by the phase information corresponding to the output of the counter 34. As a result, the same effect as in the seventh embodiment can be obtained, and the circuit configuration can be simplified since a new counter is not required.

Embodiment 10 FIG. Next, a PWM circuit according to Embodiment 10 of the present invention will be described with reference to FIG. In this embodiment, the carrier wave basic pattern 45 as shown in FIG. 15 is stored in the ROM 40 that outputs the carrier wave 25, and a frequency divider 46 is arranged inside the PLL circuit 15 on the output side of the counter 34. The output is used as a comparison signal with the signal wave reference signal 17 of the phase comparator 35. The frequency division ratio of the frequency divider 46 is set in advance by the CPU 19 and is used by the register 32.

For example, when the frequency division ratio is set to 1/5 and the counter 34 is a 12-bit counter, 000H
Frequency divider 4 only after counting 5 times from FFFH to
The signal is generated once from 6 times. As a function of the PLL circuit 15, the operation is performed so that the phase and frequency of the signal generated from the frequency divider 46 and the signal wave reference signal 17 coincide with each other. Will count. That is, the carrier wave basic pattern 45 shown in FIG. 15 is read five times from the ROM 40, and the carrier wave 2 whose frequency magnification with respect to the signal wave reference signal 17 is 5 times.
5 is output.

For example, when the frequency division ratio is changed to 1/3 by the CPU 19, the counter 34 changes from 000H to FF.
Only after counting up to FH three times, the frequency divider 46-1
A time signal will be generated. Since the PLL circuit 15 always operates so that the phase and frequency of the signal wave reference signal 17 and the output of the frequency divider 46 match, as a result, the voltage control oscillator 33 according to the response speed of the loop filter 36
, Gradually decreases and shifts to the synchronized state. Then, the counter 34 counts three cycles for one cycle of the signal wave reference signal 17, that is, the carrier wave basic pattern 45 is read three times from the ROM 40, and the frequency magnification with respect to the signal wave reference signal 17 is tripled. Change.

In this embodiment, since the frequency magnification changes gradually and the value of the counter 34 is continuous, the carrier 25
Is also continuous, and there is no occurrence of an illegal pulse of the gate pulse 28. Further, the change in the frequency magnification depends on the response speed of the loop filter 36, and by reducing the response speed, the transition can be performed continuously and smoothly, and the frequency magnification can be changed gently.

[0061]

As described above, in the PWM circuit according to the first aspect of the present invention, the first register for temporarily storing the frequency division ratio of the frequency divider set by the CPU, and the first register for temporarily storing the frequency division ratio. A second register for inputting and holding the frequency division ratio at the timing of the phase reference signal from the PLL circuit and reflecting the input to the frequency divider; therefore, when changing the frequency magnification of the carrier with respect to the signal wave reference signal, Since the carrier is continuous, generation of an incorrect pulse of the switching signal can be prevented, and the reliability of ON / OFF control of the switching element of the power converter is improved.

A PW according to claim 2 of the present invention.
The M circuit receives a phase reference signal from the PLL circuit as an input and a FIFO capable of holding a plurality of frequency division ratios of the frequency divider set by the CPU, and divides the frequency division ratio held in the FIFO by the frequency division. FI that controls the timing of sequentially reflecting on the container
Since the FO control circuit is provided, when the frequency magnification of the carrier with respect to the signal wave reference signal is changed, the carrier is continuous, so that the occurrence of an incorrect pulse of the switching signal can be prevented and the switching element of the power converter is turned on. / OF
The reliability of the F control is improved, and a PWM circuit in which the frequency division ratio is automatically changed only by initial setting of the CPU can be realized, and the load on the CPU can be reduced.

The PW according to claim 3 of the present invention.
The M circuit inputs the frequency division ratio from the CPU to the register at the timing of the phase reference signal from the PLL circuit, so when changing the frequency magnification of the carrier with respect to the signal wave reference signal,
Since the carrier wave is continuous, it is possible to prevent the generation of an illegal pulse of the switching signal, and to improve the reliability of the ON / OFF control of the switching element of the power converter.
The circuit configuration can be simplified.

The PW according to claim 4 of the present invention.
The M circuit inputs a counter output of the PLL circuit to the CPU and sets a predetermined value in an up / down counter based on phase information corresponding to the counter output;
In order to control the timing of inputting the frequency division ratio from the CPU to the register, when changing the frequency magnification of the carrier with respect to the signal wave reference signal, the carrier is continuous, so that an incorrect pulse of the switching signal may be generated. ON / O of switching element of power converter
The reliability of the FF control is improved, the frequency division ratio can be changed efficiently, and the circuit configuration can be simplified.

The PW according to claim 5 according to the present invention.
The M circuit receives a pulse from the PLL circuit and detects the frequency of the pulse. The M circuit stores frequency division ratio data in advance and searches for and outputs a frequency division ratio corresponding to the detected frequency. A frequency division ratio table, wherein the frequency division ratio output from the frequency division ratio table is input to a register at the timing of the phase reference signal from the PLL circuit. When changing, the carrier is continuous, which prevents the generation of illegal pulses in the switching signal, improves the reliability of ON / OFF control of the switching element of the power converter, and greatly reduces the load on the CPU. it can.

The PW according to claim 6 of the present invention.
The M circuit according to any one of claims 1 to 5, wherein the frequency divider is a rate multivibrator, so that when changing the frequency magnification of the carrier with respect to the signal wave reference signal, the carrier becomes continuous. The occurrence of illegal pulses in the switching signal can be prevented, the reliability of the ON / OFF control of the switching element of the power converter can be improved, and the frequency of the signal in the circuit can be suppressed low. Can be suppressed, and the design of the printed wiring board becomes easy.

According to a seventh aspect of the present invention, there is provided a PWM circuit for outputting a signal wave as a command value based on a signal wave reference signal input from the outside and setting control information.
U and a PLL that receives the signal wave reference signal as input, and outputs a pulse whose frequency is a multiple of the frequency of the signal wave reference signal and a phase reference signal indicating that the signal wave reference signal has a specific phase. A counter that counts pulses output from the PLL circuit and resets the counter value at the timing of the phase reference signal from the PLL circuit; and a plurality of types that have different frequency magnifications from the signal wave reference signal. A carrier wave pattern is stored for each address consisting of the counter output and identification information corresponding to the type of the carrier wave pattern, and a desired carrier wave is output according to the identification information set in advance by the CPU.
OM, a first register for temporarily holding the identification information set by the CPU, and the identification information once held at the timing of the phase reference signal from the PLL circuit and holding the same. And a second register for reflecting the carrier wave and the signal wave, and turning on / off the switching element of the power converter according to the magnitude of the comparison.
And a comparator that outputs a switching signal for performing F control. Therefore, when changing the frequency magnification of the carrier with respect to the signal wave reference signal, the carrier is continuous, so that generation of an incorrect pulse of the switching signal can be prevented. In addition, the reliability of ON / OFF control of the switching element of the power converter is improved, and the frequency of the signal in the circuit can be significantly reduced. There are effects such as easy board design.

The PW according to claim 8 according to the present invention.
The M circuit includes a CPU that outputs a signal wave serving as a command value based on a signal wave reference signal input from the outside and sets control information, and receives the signal wave reference signal as an input and sets a frequency of the signal wave. A PLL circuit that outputs a pulse that is a multiple of the frequency of the reference signal and a phase reference signal indicating that the signal wave reference signal has a specific phase; a counter that counts pulses output from the PLL circuit; Value is PL
A counter that resets at the timing of the phase reference signal from the L circuit, and a plurality of types of carrier patterns having different frequency magnifications from the signal wave reference signal, together with the magnification switching timing data, output the counter output and the carrier wave pattern. A ROM that stores a desired carrier with the timing data according to the identification information set in advance by the CPU, and stores the identification information set by the CPU; And the identification information once held at the timing of generation of the timing data from the ROM, and held.
M, a second register for reflecting the carrier wave and the signal wave, and a comparator for outputting a switching signal for performing ON / OFF control of a switching element of the power converter according to the magnitude of the comparison. Therefore, when changing the frequency magnification of the carrier with respect to the signal wave reference signal, the carrier is continuous, so that the generation of an incorrect pulse of the switching signal can be prevented, and the O of the switching element of the power converter can be prevented.
The reliability of the N / OFF control is improved, and the frequency magnification can be changed efficiently at high speed.

The PW according to claim 9 according to the present invention.
The M circuit includes a voltage-controlled oscillator that generates a pulse that is output from the circuit at a frequency that is twice as high as a signal wave reference signal input from the outside to the circuit, a counter that counts the pulses, and an output signal of the counter. A phase comparator that compares the phase with the signal wave reference signal and outputs a voltage corresponding to the phase difference; and a loop filter that smoothes the output of the phase comparator and inputs the output signal to the voltage controlled oscillator. P with
An LL circuit, a CPU that outputs a signal wave serving as a command value based on the signal wave reference signal and sets control information, and a plurality of types of carrier wave patterns having different frequency magnifications from the signal wave reference signal, A ROM which stores a counter output and an identification information corresponding to the type of the carrier wave pattern and which outputs a desired carrier according to the identification information set in advance by the CPU;
A first register for temporarily storing the identification information set by the PU, and a PLL for temporarily storing the identification information once stored in the PLL;
A second register which is inputted and held by timing control based on the phase information from the counter of the circuit and reflected in the ROM, and the carrier wave and the signal wave are compared with each other, ON / O of switching element
A comparator that outputs a switching signal for performing FF control;
Because, when changing the frequency magnification of the carrier with respect to the signal wave reference signal, since the carrier is continuous,
It is possible to prevent the generation of illegal pulses of the switching signal, improve the reliability of ON / OFF control of the switching element of the power converter, and simplify the circuit configuration.

According to the tenth aspect of the present invention,
The WM circuit includes a voltage-controlled oscillator that generates a pulse serving as an output of the circuit at a frequency that is twice the frequency of the signal wave reference signal input from the outside, a counter that counts the pulse, and presets the counter output. A frequency divider that divides the frequency by the held frequency division ratio, a phase comparator that compares the phases of the output signal of the frequency divider and the signal wave reference signal, and outputs a voltage corresponding to the phase difference, A PLL circuit having a loop filter for smoothing the output of the phase comparator and inputting the output signal to the voltage-controlled oscillator; output of a signal wave serving as a command value based on the signal wave reference signal; And a basic pattern of a carrier wave are stored.
A ROM that counts the basic pattern at a predetermined number of times with the counter output of the LL circuit as an input and outputs a desired carrier, and compares the carrier with the signal wave to determine the magnitude of the signal. ON / OFF of switching element
And a comparator that outputs a switching signal for performing the OFF control, so that when changing the frequency magnification of the carrier with respect to the signal wave reference signal, the carrier is continuous, thereby preventing generation of an incorrect pulse of the switching signal. ,
The reliability of the ON / OFF control of the switching element of the power converter is improved, and the change in the frequency magnification depends on the response speed of the loop filter, and the transition is performed continuously and smoothly by reducing the response speed. The frequency magnification can be changed gently.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a PWM circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an operation of the PWM circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a PWM circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a PWM circuit according to a third embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a PWM circuit according to a fourth embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a PWM circuit according to a fifth embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a PWM circuit according to a sixth embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a PWM circuit according to a seventh embodiment of the present invention.

FIG. 9 is a diagram showing data in a ROM of a PWM circuit according to a seventh embodiment of the present invention.

FIG. 10 is a diagram showing another example of the data of the ROM of the PWM circuit according to the seventh embodiment of the present invention.

FIG. 11 is a diagram showing a configuration of a PWM circuit according to an eighth embodiment of the present invention.

FIG. 12 is a diagram showing data in a ROM of a PWM circuit according to an eighth embodiment of the present invention.

FIG. 13 is a diagram showing a configuration of a PWM circuit according to a ninth embodiment of the present invention.

FIG. 14 is a diagram showing a configuration of a PWM circuit according to a tenth embodiment of the present invention.

FIG. 15 is a diagram showing data in a ROM of a PWM circuit according to a tenth embodiment of the present invention.

FIG. 16 is a diagram showing a configuration of a conventional PWM circuit.

FIG. 17 is a diagram illustrating the operation of a conventional PWM circuit.

FIG. 18 is a diagram illustrating the operation of a conventional PWM circuit.

FIG. 19 is a diagram illustrating a problem of a conventional PWM circuit.

[Explanation of symbols]

Reference Signs List 15 PLL circuit, 16 signal wave, 17 signal wave reference signal, 18 phase reference signal, 19 CPU, 20 frequency divider, 21 first register, 22 second register, 2
3 up / down counter, 25 carriers, 27
Comparator, 28 gate pulse as switching signal, 29 rate multivibrator, 30 FI
FO, 31 FIFO control circuit, 32 registers, 33
Voltage controlled oscillator, 34 counter, 35 phase comparator, 36 loop filter, 37 frequency detector, 38
Frequency division ratio table, 39 counter, 40 ROM, 4
1a, 41b carrier pattern, 42 first register, 43 second register, 44 switching command data as timing data of magnification switching, 45 carrier wave basic pattern, 46 frequency divider.

Claims (10)

[Claims] 1. A CPU for outputting a signal wave serving as a command value based on a signal wave reference signal input from the outside and setting control information, and receiving the signal wave reference signal as an input and changing the frequency of the signal. A PLL circuit that outputs a pulse that is a multiple of the frequency of the wave reference signal and a phase reference signal indicating that the signal wave reference signal has a specific phase; and the pulse that is output from the PLL circuit, A frequency divider for dividing the frequency by the frequency division ratio set by the CPU, and an output of the frequency divider as an input, set to a predetermined value preset at the timing of the phase reference signal from the PLL circuit, An up / down counter that repeats up and down counting between predetermined values separately set from the value and outputs a carrier wave; and compares the carrier wave and the signal wave to each other, and according to the magnitude thereof, a power converter. No In a PWM circuit having a comparator for outputting a switching signal for performing ON / OFF control of the switching element, a first register for temporarily holding a frequency division ratio of the frequency divider set by the CPU, and a once register A second register for inputting and holding the obtained frequency division ratio at the timing of the phase reference signal from the PLL circuit, and reflecting the input to the frequency divider.
M circuit. 2. A CPU for outputting a signal wave serving as a command value based on a signal wave reference signal input from the outside and setting control information, and receiving the signal wave reference signal as an input and changing the frequency of the signal. A PLL circuit that outputs a pulse that is a multiple of the frequency of the wave reference signal and a phase reference signal indicating that the signal wave reference signal has a specific phase; and the pulse that is output from the PLL circuit, A frequency divider for dividing the frequency by the frequency division ratio set by the CPU, and an output of the frequency divider as an input, set to a predetermined value preset at the timing of the phase reference signal from the PLL circuit, An up / down counter that repeats up and down counting between predetermined two values separately set from the value and outputs a carrier wave, and compares the carrier wave with the signal wave, and according to the magnitude thereof, a power converter No In a PWM circuit having a comparator for outputting a switching signal for performing ON / OFF control of the switching element, a FIFO capable of holding a plurality of frequency division ratios of the frequency divider set by the CPU, and the PL
The phase reference signal from the L circuit is input and the FI
And a FIFO control circuit for controlling timing for sequentially reflecting the frequency division ratio held in the FO to the frequency divider. 3. A CPU for outputting a signal wave serving as a command value based on a signal wave reference signal input from the outside and setting control information, and receiving the signal wave reference signal as an input and changing the frequency of the signal. A PLL circuit that outputs a pulse that is a multiple of the frequency of the wave reference signal and a phase reference signal indicating that the signal wave reference signal has a specific phase; and the pulse that is output from the PLL circuit, A frequency divider that divides the frequency by the frequency division ratio set by the CPU and held by the register, and an output of the frequency divider as an input, which is set to a predetermined value set in advance by the timing of the phase reference signal from the PLL circuit. Set up from that value between predetermined two values set separately,
An up / down counter that repeats down-counting and outputs a carrier wave, and compares the carrier wave with the signal wave and outputs a switching signal for performing ON / OFF control of a switching element of a power converter according to the magnitude of the signal wave. A PWM circuit, comprising: inputting the frequency division ratio from the CPU to the register at a timing of the phase reference signal from the PLL circuit. 4. A voltage-controlled oscillator for generating a pulse to be output from the circuit at a frequency which is twice as high as a signal wave reference signal input from the outside to the circuit, a counter for counting the pulses, and an output signal of the counter And a phase comparator for comparing the phase of the signal wave reference signal and outputting a voltage corresponding to the phase difference, and a loop filter for smoothing the output of the phase comparator and inputting the output signal to the voltage controlled oscillator And a CPU for outputting a signal wave serving as a command value based on the signal wave reference signal and setting control information
A frequency divider that divides the pulse output from the PLL circuit by a frequency division ratio set in advance by the CPU and held in a register, and an output of the frequency divider as an input, and the signal wave reference signal An up / down counter that sets a predetermined value at a timing at which the phase becomes a specific phase, repeats up and down counting between predetermined two values separately set from the value, and outputs a carrier wave; A comparator that compares a carrier wave with the signal wave and outputs a switching signal for performing ON / OFF control of a switching element of the power converter according to the magnitude of the signal wave. Is input to the CPU, and the phase information corresponding to the counter output is used to set a predetermined value in the up / down counter. PWM circuit the dividing ratio and controls respectively the timing of input to the register from the CPU. 5. A CPU for outputting a signal wave serving as a command value based on a signal wave reference signal input from the outside and setting control information, and receiving the signal wave reference signal as an input and changing the frequency of the signal. A PLL circuit that outputs a pulse that is a multiple of the frequency of the wave reference signal and a phase reference signal indicating that the signal wave reference signal has a specific phase; and sets the pulse output from the PLL circuit in advance. A frequency divider that divides the frequency by the frequency division ratio held by the register and an output of the frequency divider are set as inputs, and set to a predetermined value preset at the timing of the phase reference signal from the PLL circuit, An up / down counter that repeats up and down counting between predetermined values separately set from the value and outputs a carrier wave; and compares the carrier wave and the signal wave to each other, and according to the magnitude thereof, a power converter. ON / OFF of switching element
A PWM circuit having a comparator that outputs a switching signal for performing control; a frequency detector that receives the pulse from the PLL circuit and detects the frequency of the pulse; A frequency division ratio table for retrieving and outputting a frequency division ratio corresponding to the frequency, wherein the frequency division ratio output from the frequency division table at the timing of the phase reference signal from the PLL circuit. Is input to the register.
circuit. 6. The PWM circuit according to claim 1, wherein the frequency divider is a rate multivibrator. 7. A CPU for outputting a signal wave serving as a command value based on a signal wave reference signal input from the outside and setting control information, and receiving the signal wave reference signal as an input and setting the frequency to the signal A PLL circuit that outputs a pulse that is a multiple of the frequency of the wave reference signal and a phase reference signal indicating that the signal wave reference signal has a specific phase; and counts pulses output from the PLL circuit. A counter for resetting a counter value at the timing of the phase reference signal from the PLL circuit, and a plurality of types of carrier wave patterns having different frequency magnifications from the signal wave reference signal correspond to the counter output and the type of the carrier wave pattern. Is stored for each address consisting of the identification information,
A ROM for outputting a desired carrier according to the identification information set by the PU, a first register for temporarily holding the identification information set by the CPU, and a first register for storing the identification information once held by the PLL circuit. A second register which is inputted and held at the timing of the phase reference signal and reflected in the ROM, and which compares the carrier wave with the signal wave and determines whether or not the switching element of the power converter is in accordance with the magnitude thereof.
And a comparator that outputs a switching signal for performing N / OFF control. 8. A CPU for outputting a signal wave serving as a command value based on a signal wave reference signal input from the outside and setting control information, and receiving the signal wave reference signal as an input and changing the frequency of the signal. A PLL circuit that outputs a pulse that is a multiple of the frequency of the wave reference signal and a phase reference signal indicating that the signal wave reference signal has a specific phase; and counts pulses output from the PLL circuit. A counter for resetting a counter value at the timing of the phase reference signal from the PLL circuit, and a plurality of types of carrier wave patterns having different frequency magnifications from the signal wave reference signal, together with the magnification switching timing data and the counter output, The identification information stored for each address composed of the identification information corresponding to the type of the carrier wave pattern and set in advance by the CPU. A ROM for outputting a desired carrier together with the timing data, a first register for temporarily storing the identification information set by the CPU, and a method for generating the timing data from the ROM by temporarily storing the identification information. A second register which is inputted and held at a timing and reflected in the ROM, and which compares the carrier wave and the signal wave and performs ON / OFF control of a switching element of a power converter according to the magnitude of the comparison. And a comparator for outputting a signal. 9. A voltage controlled oscillator for generating a pulse which is output from the circuit at a frequency which is twice as high as a signal wave reference signal inputted from the outside to the circuit, a counter for counting the pulse, and an output signal of the counter And a phase comparator for comparing the phase of the signal wave reference signal and outputting a voltage corresponding to the phase difference, and a loop filter for smoothing the output of the phase comparator and inputting the output signal to the voltage controlled oscillator And a CPU for outputting a signal wave serving as a command value based on the signal wave reference signal and setting control information
And a plurality of types of carrier patterns having different frequency magnifications with respect to the signal wave reference signal are respectively stored for addresses composed of the counter output and identification information corresponding to the type of the carrier wave pattern, and set in advance by the CPU. A ROM for outputting a desired carrier wave according to the identified identification information,
A first register for temporarily holding the identification information set by the CPU; and the identification information once held by the timing control based on phase information from the counter of the PLL circuit. And a second register for reflecting the carrier wave and the signal wave, and according to the magnitude thereof, the O of the switching element of the power converter is changed.
And a comparator that outputs a switching signal for performing N / OFF control. 10. A voltage controlled oscillator for generating a pulse which is output from the circuit at a frequency which is twice as high as a signal wave reference signal inputted from the outside to the circuit, a counter for counting the pulses, and A frequency divider that divides the frequency by the set and held frequency division ratio, a phase comparator that compares the phases of the output signal of the frequency divider and the signal wave reference signal, and outputs a voltage corresponding to the phase difference; Smoothing the output of the phase comparator,
A PLL circuit having a loop filter for inputting the output signal to the voltage-controlled oscillator, a CPU for outputting a signal wave serving as a command value based on the signal wave reference signal and setting control information, and a carrier wave. A basic pattern is stored, a ROM that receives the counter output of the PLL circuit as an input, counts the basic pattern at a predetermined number of times, and outputs a desired carrier, Accordingly, the O of the switching element of the power converter is
And a comparator that outputs a switching signal for performing N / OFF control.