JP2000036749A - D/a conversion circuit and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a D/A conversion circuit within a small area by dividing a digital signal into high-order bits and low-order bits, selecting two adjacent gradation voltage lines corresponding to the high-order bits, preparing plural gradation voltages from the gradation voltages of these gradation voltage lines, and supplying the correspondent gradation voltage among the prepared gradation voltages corresponding to the low-order bits. SOLUTION: Two adjacent gradation voltage lines are always selected by swA and swB. Thus, even when any digital signal of 2 bits is inputted, two adjacent gradation voltage lines are selected by swA and swB, and the gradation voltage is supplied to a first output line 108 (108-1 and 108-2). In this case, the first output line to be selected by four internal switches of swA is made into first output lines (H) 108-1, and the first output line to be selected by four internal switches of swB is made into first output line (L) 108-2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD OF THE INVENTION

[0002] The present invention relates to a D / A conversion (digital / analog conversion) circuit. In particular, the present invention relates to a D / A conversion circuit used for a driving circuit of a semiconductor device.

[0003]

[Prior art]

Recently, a semiconductor device in which a semiconductor thin film is formed on an inexpensive glass substrate, for example, a thin film transistor (TFT)
The technology for fabricating is rapidly developing. The reason is that the demand for active matrix type semiconductor display devices (particularly, active matrix type liquid crystal display devices) has been increasing.

An active matrix type liquid crystal display device is
TFTs are arranged in several tens to millions of pixel regions arranged in a matrix, and electric charges entering and exiting each pixel electrode are controlled by a switching function of the TFTs.

[0006] Among them, a digital drive type active matrix type liquid crystal display device which can be driven at a high speed has been receiving attention as the display device has been improved in definition and image quality.

FIG. 14 shows a conventional digital matrix type active matrix type liquid crystal display device. A conventional digital drive type active matrix type liquid crystal display device includes a source signal line side shift register 140 as shown in FIG.
1. Address lines (ad) 140 of the digital decoder
2. Latch circuit (LAT1) 1403, latch circuit (L
AT2) 1404, latch pulse line 1405, D / A conversion circuit 1406, gradation voltage line 1407, source signal line 1
408, gate signal line side shift register 1409, gate signal line (scanning line) 1410, and pixel TFT 141
1 and the like. Here, a 4-bit digital drive type active matrix liquid crystal display device is taken as an example. In the latch circuits (LAT1 and LAT2), four latch circuits are collectively shown for convenience.

Address lines (ad) of the digital decoder
A digital signal (digital gradation signal) supplied to 1402 is sequentially written to the LAT1 group by a timing signal from the source signal line side shift register.

[0009] The time until the writing of the digital signal to the LAT1 group is completely completed is called one line period. That is, the time interval from the time when the writing of the digital signal from the digital decoder to the leftmost LAT1 is started to the time when the writing of the digital signal from the digital decoder to the rightmost LAT1 is completed is determined. This is one line period.

After the writing of the digital signals to the LAT1 group is completed, the digital signals written to the latch1 group are simultaneously transmitted to the LAT2 group when the latch pulse flows through the latch pulse line in accordance with the operation timing of the shift register. Dispatched and written.

The digital signal supplied to the digital decoder is sequentially written into the LAT1 group, which has finished sending the digital signals to the LAT2 group, by the signal from the source signal line side shift register.

During the second line period, a voltage corresponding to the digital signal sent to the LAT2 group is supplied to the source signal line at the start of the second line period. The driving circuit described here as an example executes conversion of a digital signal into a gradation voltage by selecting one of 16 gradation voltages by a D / A conversion circuit.

The selected gradation voltage is supplied to the corresponding source signal line for one line period. The corresponding TFT is switched by a scanning signal from the gate signal line side shift register, and the liquid crystal molecules are driven.

By repeating the above operation for the number of scanning lines, one screen (one frame) is formed. Generally, in an active matrix type liquid crystal display device, 1
Rewriting of an image of 60 frames per second is performed.

[0015]

[Problems to be solved by the invention]

Here, a conventional D / A conversion circuit used in the above-described digital drive circuit will be described. Referring to FIG.

A conventional 4-bit D / A conversion circuit includes a plurality of switches (sw0 to sw15) and a gray scale voltage line (V
0 to V15). A plurality of switches (sw) are switched by a 4-bit digital signal supplied from the LAT2 group.
0 to sw15) is selected, and the source signal line 14 is connected to the gray scale voltage line connected to the selected switch.
07 is supplied with a voltage.

One such D / A conversion circuit is provided for one source signal line.

The conventional 4-bit D / D described here
In the case of the A conversion circuit, the number of switches is 16, and the number of gradation voltage lines is 16. In an actual active matrix type liquid crystal display device, the area of the switch is large, and the area of the entire driving circuit is increased.

Here, a conventional 4-bit D is used.
Take another example of the / A conversion circuit. Please refer to FIG. The 4-bit D / A conversion circuit shown in FIG. 16 uses a plurality of switches (4-bit digital signals) supplied from the LAT2 group similarly to the 4-bit D / A conversion circuit described above. sw0 to sw15)
One is selected, and a voltage is supplied to the source signal line from the gray scale voltage line connected to the selected switch.

In the D / A conversion circuit shown in FIG. 16, the number of gradation voltage lines is five (V0 to V4), and the 4-bit D / A shown in FIG. Less than the conversion circuit. However, the number of switches is sixteen.
Therefore, the area of the entire driving circuit cannot be reduced.

Here, a D / A conversion circuit that handles a 4-bit digital signal is described. However, as the number of bits increases, the number of switches increases exponentially. In other words, a conventional D / A conversion circuit that handles an n-bit digital signal requires 2 ⁿ switches. Therefore, the area of the driving circuit becomes large.

The large area of the driving circuit as described above is one of the factors that hinder the miniaturization of semiconductor display devices, particularly active matrix liquid crystal display devices.

In order to increase the definition of the semiconductor display device, it is necessary to increase the number of pixels, that is, to increase the number of source signal lines. However, as described above, when the number of source signal lines increases, the number of D / A conversion circuits also increases, and the area of the drive circuit increases, which is one of the causes of hindering high definition. Has become.

For the above-mentioned reason, the D / A having a small area is used.
There is a long-felt need for a conversion circuit.

The present invention has been made in view of the above-mentioned problems, and has as its object to provide a D / A conversion circuit having a small area.

[0027]

[Means for Solving the Problems]

According to an embodiment of the present invention, there is provided a D / A conversion circuit for supplying a gradation voltage corresponding to an input n-bit (n is a natural number of 2 or more) digital signal to an output line, The n-bit digital signal is divided into upper x bits and lower y bits (x + y = n; x and y are both natural numbers), and (2 ^x +1) levels are determined by the upper x bits of the n-bit digital signal. Two adjacent gradation voltage lines are selected from the adjustment voltage lines, and 2 ^y gradation voltages are generated from the selected gradation voltages of the two adjacent gradation voltage lines. There is provided a D / A conversion circuit, wherein a corresponding gray scale voltage among the 2 ^y gray scale voltages is supplied to an output line by lower y bits of the digital signal of bits. This achieves the above object.

[0029] The D / A conversion circuit may be formed on an insulating substrate using a thin film transistor.

According to an embodiment of the present invention, there is provided a D / A conversion circuit for supplying a gradation voltage corresponding to an input n-bit (n is a natural number of 2 or more) digital signal to an output line. Then, the n-bit digital signal is divided into upper x bits and lower y bits (x + y = n; x and y are both natural numbers), and (2 ^x +1) bits are determined by the upper x bits of the n-bit digital signal. Of the gray scale voltage lines
The z-th and (z + 1) -th gradation voltage lines to which higher voltages are supplied toward the (2 ^x +1) -th gradation voltage line are selected (1 ≦ z ≦ 2 ^x ; z is a natural number) , from the gradation voltage gradation voltage lines of the z and the said selected (z + 1), the gradation voltage of 2 ^y Road created, by the lower y bits of the digital signal of the n bits, the 2 ^y Street A D / A conversion circuit is provided in which a corresponding one of the gray scale voltages is supplied to an output line. This achieves the above object.

[0031] The D / A conversion circuit may be formed on an insulating substrate using a thin film transistor.

According to an embodiment of the present invention, a plurality of TFTs arranged in a matrix and the plurality of T
1. A semiconductor device comprising a source signal line side driving circuit and a gate signal line side driving circuit for driving an FT, wherein the source signal line side driving circuit has n input bits (n is a natural number of 2 or more). And a D / A conversion circuit that supplies a gray scale voltage corresponding to the digital signal to the output line, and divides the n-bit digital signal into upper x bits and lower y bits (x + y = n; x , Y are natural numbers), the upper x bits of the n-bit digital signal (2 ^x +
1) Two adjacent grayscale voltage lines are selected from the two grayscale voltage lines, and 2 ^y grayscale voltages are obtained from the selected grayscale voltages of the two adjacent grayscale voltage lines. A semiconductor device is provided, wherein a corresponding gray scale voltage of the 2 ^y gray scale voltages is supplied to an output line according to the lower y bits of the generated n-bit digital signal.
This achieves the above object.

According to one embodiment of the present invention, a plurality of TFTs arranged in a matrix and the plurality of T
A semiconductor device comprising a source signal line side driving circuit and a gate signal line side driving circuit for driving an FT, wherein the source signal line side driving circuit has n input bits (n is a natural number of 2 or more). And a driving circuit including a D / A conversion circuit for supplying a gray scale voltage corresponding to the digital signal to an output line, wherein the n-bit digital signal is converted into upper x bits and lower y bits Divide (x + y = n;
x, y are natural numbers), the by upper x bits of the n bit digital signals (2 ^x +1) of the gradation voltage lines, toward the first to the gradation voltage line of the (2 ^x +1) The z-th and (z + 1) th gradation voltage lines to which a higher voltage is supplied are selected (1 ≦ z ≦ 2 ^x ; z is a natural number), and the selected z-th and (z + 1) -th gradations are selected. From the gray scale voltages of the voltage lines, 2 ^y gray scale voltages are generated, and the n
The lower 2 bits of the digital signal of
A semiconductor device is provided in which a corresponding gray scale voltage among ^y gray scale voltages is supplied to an output line. This achieves the above object.

According to one embodiment of the present invention, there is provided a semiconductor device including a plurality of TFTs, a source signal line side driving circuit and a gate signal line side driving circuit for driving the plurality of TFTs, The source signal line side driving circuit has a driving circuit including a D / A conversion circuit for supplying a gradation voltage corresponding to an inputted n-bit (n is a natural number of 2 or more) digital signal to an output line. In the semiconductor device, the n-bit digital signal is divided into upper x bits and lower y bits (x + y = n; x and y are both natural numbers), and (2 + 2) is determined by upper x bits of the n-bit digital signal.
^x +1) of the gradation voltage lines, the first to (2 ^x +1)
And the (z + 1) th gray scale voltage line to which a higher voltage is supplied toward the gray scale voltage line is selected (1 ≦
z ≦ 2 ^x ; z is a natural number), 2 ^y gradation voltages are generated from the selected gradation voltages of the z-th and (z + 1) -th gradation voltage lines, and the n-bit digital signal is A semiconductor device is provided in which the lower y bits supply a corresponding gray scale voltage among the 2 ^y gray scale voltages to an output line. This achieves the above object.

[0035] The plurality of TFTs, the source signal line side drive circuit, and the gate signal line side drive circuit may be integrally formed on an insulating substrate using a thin film transistor.

Here, the D of the present invention will be described with reference to the following examples.
The details of the / A conversion circuit will be described. However, the D / A conversion circuit described in the following examples is an embodiment of the present invention, and the D / A conversion circuit of the present invention is not limited to these.

[0037]

【Example】

(Example 1)

In this embodiment, an embodiment of the D / A conversion circuit of the present invention will be described. In this embodiment, a digital signal provided in the source signal line side driving circuit is converted into an analog gray scale signal (gray scale voltage) by using an active matrix type liquid crystal display device having 800 × 600 pixels. The details of the D / A conversion circuit for conversion will be described.

In this embodiment, a D / A conversion circuit for processing a 4-bit digital signal will be described as an example.
The D / A conversion circuit of the present invention is not limited to this, and a D / A conversion circuit that processes a digital signal of 2 bits or more is realized.

First, reference is made to FIG. 1 and FIG. FIGS. 1 and 29 are schematic structural views of the active matrix type liquid crystal display device of the present embodiment. The active matrix type liquid crystal display device of the present embodiment includes a first source signal line side shift register 101, a digital decoder address line (a, b) 102, a latch circuit (LAT1, 0 to LA).
T1, 799) 103, a latch circuit (LAT2, 0 to L)
AT2, 799) 104, latch pulse line 105, first
D / A conversion circuit (1st-D / A, 0-799) 10
6, gradation voltage lines (V0 to V4) 107, first output line 1
08, the second source signal line side shift register 109, the address lines (c, d) 110 of the digital decoder, the latch circuits (LAT3, 0 to LAT3, 799) 111, and the latch circuits (LAT4, 0 to LAT4, 799) 112 , Latch pulse line 113, second D / A conversion circuit (2nd-
D / A, 0 to 2nd-D / A, 799) 114, second output line 115, gate signal line side shift register 116 as a gate signal line side driving circuit, source signal line 117, gate signal line (scanning line) 118 and the pixel TFT 119
It is constituted by such as.

Although omitted in FIGS. 1 and 29, other buffers and analog switches are provided as appropriate.

Of the 4-bit digital signals supplied from the outside, the upper 2 bits of the digital signal are
02, and the lower two bits of the digital signal are supplied to the address lines 110 c and d.

The five gradation voltage lines (V0 to V4) 107 are supplied with different voltages by dividing the voltage applied between V0 and V4 by resistance.
Also, the highest voltage is applied to V4 and the lowest voltage is applied to V0.

Here, the gradation voltage line to which the lowest voltage is supplied is referred to as a first gradation voltage line, and the gradation voltage line to which the highest voltage is supplied is referred to as a fifth gradation voltage line. Therefore, it is understood that higher voltages are supplied to the five gradation voltage lines toward the first to fifth gradation voltage lines.

First source line side shift register 101
Supplies a latch signal (timing signal) to the latch circuits LAT1, 0 to LAT1, 799 sequentially. The latch circuits LAT1, 0 to LAT1, 799 sequentially fetch and hold digital signals from a and b of the address lines 102 in response to a latch signal supplied from the first source line side shift register.

At the moment when the capture of the digital signal into the latch circuits LAT1, 799 is completed, the latch pulse line 10
5 is supplied with a latch signal, and LAT2, 0 to LAT2,
LAT1,0 to LAT
1, 799, and digital signals are simultaneously captured and held. The digital signal captured by LAT2,0 to LAT2,799 is sent to the first D / A conversion circuit 106 for one line period.

Here, one latch circuit (LAT1, 0)
And LAT2,0) are shown in FIG. Latch circuit (LAT1, 0) and latch circuit (LAT2, 0)
Are composed of the same circuit.

LAT1,0 are clocked inverters 2
01, 203, 204 and 206, and inverters 202 and 205.
And a digital signal is taken in from b and held. Clocked inverters 201, 203, 204 and 206
In this switching, the latch signal (lat1,0) from the first source signal line side shift register 101 and its inverted signal (lat1,0) are used.

LAT2,0 is the clocked inverter 2
07, 209, 210 and 212, and inverters 208 and 211, and fetches and holds digital signals from LAT1,0. Clocked inverter 2
07, 209, 210 and 212, the latch signal (lat) from the latch pulse line 105 is used.
2) and its inverted signal (inverted lat2) are used. LAT2,0 sends a digital signal to the first D / A conversion circuit.

Since the digital signals supplied to a and b of the address line 102 are supplied to the first D / A conversion circuit 106 via the two-stage latch circuit, in this embodiment, for convenience of explanation, , The signal lines connected to the first D / A conversion circuit are called a and b.

The first D / A conversion circuit (1st-D / A,
0 to 1st-D / A, 799) 106 has LAT2,
2-bit digital signals are supplied from 0 to LAT2,799. First D / A conversion circuit (1st-D
/ A, 0 to 1st-D / A, 799) 106 converts the supplied 2-bit digital signal into an analog signal (grayscale voltage), and outputs the first output line 108 (108-1 and 108-2). ) Through the second D / A conversion circuit (2nd-
D / A, 0-2nd-D / A, 799) 114.

In synchronization with the timing when the first source line side shift register 101 sequentially sends out the latch signals to the LATs 1, 0 to 799, the second source line side shift register 1
09 sequentially sends a latch signal to LAT3,0 to 799. In other words, the timing at which the first source signal line side shift register sends out the latch signal to LAT1,0 is the same as the timing at which the second source signal line side shift register sends out the latch signal to LAT3,0. Also,
The timing at which the first source signal line side shift register sends out the latch signal to LAT1,1 is the same as the timing at which the second source signal line side shift register sends out the latch signal to LAT3,1.

Second source signal line side shift register 10
9, LAT3, 0 to LAT
3.799 sequentially captures and holds 2-bit digital signals from c and d of the address line 110. At the moment the capture of the digital signal into the latch circuits LAT3, 799 is completed, the latch signal is supplied to the latch pulse line 113, and all the latch circuits LAT4, 0 to LAT4, 799 output the digital signals from LAT3, 0 to LAT3, 799. Are simultaneously captured and retained. LAT4, 0-LAT
4, 799, the digital signal captured by the second D /
The signal is sent to the A conversion circuit 114.

The second D / A conversion circuit (2nd-D / A,
0 to 2nd-D / A, 799) are connected to the source signal line based on the gradation voltage supplied from the output line 108 of the first D / A conversion circuit and the supplied 2-bit digital signal. A gradation voltage is supplied to the second output line 115.

The gradation voltage supplied to the second output line 115 is supplied to the source signal line 1 through a buffer (not shown) or the like.
17 is supplied. Gate signal line side shift register 11
6 according to the scanning signal from the corresponding gate signal line 11
The pixel TFT 119 connected to 8 is turned on, and a gradation voltage is applied to the liquid crystal molecules.

As described above, all the pixel TFTs connected to the selected scanning line are turned ON at once, and the liquid crystal molecules are driven. Then, all the scanning lines are sequentially selected, and an image of one frame is formed. In this embodiment, 1
An image of 60 frames is formed per second.

Here, the first D / A conversion circuit 106 and the second D / A conversion circuit 114 of this embodiment will be described in detail with reference to FIGS.

Referring to FIG. FIG. 3 is a schematic diagram of the first D / A conversion circuit 106 and the second D / A conversion circuit 114. First, the first D / A conversion circuit 1 will be described with reference to FIG.
06 and the operation of the second D / A conversion circuit 114 will be described.

The first D / A conversion circuit 106 includes a switch circuit swA including four internal switches (swA1 to swA4) and four internal switches (swB1 to swB4).
And the gray scale voltage line 107 (V0
To V4). The second D / A conversion circuit 114 has four internal switches (swC1 to swC4).
And four resistors (R1 to R
4). Here, the specific resistance of the wiring itself is not considered for convenience.

In this embodiment, swA4 is connected to V4. swA3 and swB4 are connected to V3. swA2 and swB3 are connected to V2. swA1 and swB2 are connected to V1. Also, swB1 is connected to V0.

In the first D / A conversion circuit 106,
A 2-bit digital signal supplied from the address lines a and b via the latch circuit controls swA and swB. According to the digital signal supplied from the address lines a and b via the latch circuit, only one of the four internal switches (swA1 to swA4) of swA is designed to be closed, and at the same time, two switches are switched. These switches do not close. Also, the address line a
SwB depending on the digital signal supplied from
Of the four internal switches (swB1 to swB4),
Only one of the switches is designed to be closed, and none of these switches can be closed at the same time. Furthermore, four internal switches of swA (swA1
To swA4) and four internal switches (swB1)
To swB4) have the following relationship. That is, when swA1 is closed, swB1 is closed, when swA2 is closed, swB2 is closed, and swA3 is closed.
When sw is closed, swB3 is closed, and when swA4 is closed, swB4 is closed. Therefore, s
Two adjacent gradation voltage lines are always selected by wA and swB. Thus, no matter what 2-bit digital signal is input, swA
And swB select two adjacent gray scale voltage lines, and the gray scale voltages are supplied to the first output lines 108 (108-1 and 108-2). Here, the first output line selected by the four internal switches of swA will be referred to as a first output line (H) 108-1, and the first output line selected by the four internal switches of swB The line will be referred to as a first output line (L) 108-2.

In the second D / A conversion circuit 114,
A 2-bit digital signal supplied from the address lines c and d via the latch circuit controls swC. In response to digital signals supplied from the address lines c and d via the latch circuit, four internal switches of swC (swC
1 to swC4), only one of the switches is designed to be closed. First output line (H) 10
The gradation voltage supplied to 8-1 and the first output line (L) 108-2 is applied to the second D / A conversion circuit 114. The first output line (H) 108-1 and the first output line (L) 108-2 are connected by four series-connected resistors (R1 to R4). From the gray scale voltages supplied to the first output line (H) 108-1 and the first output line (L) 108-2, the four resistors (R1 to R4) of the second D / A conversion circuit are used. ) Produces four different gray scale voltages. Therefore, when any one of the four internal switches of swC (swC1 to swC4) is closed, the corresponding gray scale voltage is output to the second output line 115.
Supplied to The gray scale voltage supplied to the second output line 115 is supplied to the source signal line 117 through a buffer (not shown) or the like.

Next, the first D of this embodiment will be described with reference to FIG.
/ A conversion circuit 106 and second D / A conversion circuit 114
Will be described. However, the circuit configuration shown in FIG. 4 includes a first D / A conversion circuit and a second D / A
This is merely one embodiment for realizing the conversion circuit, and is not limited to this.

As shown in FIG. 4, the first D
/ A conversion circuit 106 includes 16 N-channel TFTs
(Tr4,1, Tr4,2, Tr3,1, Tr3,2, Tr3,5, Tr3,6,
Tr2,1, Tr2,2, Tr2,5, Tr2,6, Tr1,1, Tr1,2, Tr
1,5, Tr1,6, Tr0,1 and Tr0,2) and 16 Ps
Channel type TFT (Tr4,3, Tr4,4, Tr3,3, Tr3,4,
Tr3,7, Tr3,8, Tr2,3, Tr2,4, Tr2,7, Tr2,8, Tr
1,3, Tr1,4, Tr1,7, Tr1,8, Tr0,3, and Tr0,4
) And five gradation voltage lines (V0 to V4).

In the five gradation voltage lines (V0 to V4) 107, the highest voltage is applied to V4, and the lowest voltage is applied to V0.

A voltage may be independently supplied to the five gradation voltage lines (V0 to V4) 107. However, also in this case, it is necessary to apply the highest voltage to V4 and the lowest voltage to V0.

Focusing on the gradation voltage line V4, a circuit in which two N-channel TFTs (Tr4,1 and Tr4,2) are connected in series and two P-channel TFTs (Tr4,3 and Tr4,3)
Tr4,4) are connected in series, and both ends of the circuit formed by connecting the two circuits in series are connected in parallel to the gradation voltage line V4. Also,
Since the digital signals from the address lines a and b are supplied to the first D / A conversion circuit via the latch circuit,
Here, for convenience of explanation, signal lines supplied from the latch circuit are a and b, and their inverted signals (a and b) are considered. The signal lines a and b, the inverted a and the inverted b are connected to the gate electrodes of Tr4,1, Tr4,2, Tr4,3 and Tr4,4, respectively. By the digital signals supplied to these signal lines a and b, the inverted a and the inverted b,
The switching of Tr4,1, Tr4,2, Tr4,3, Tr4,4 is controlled, and when all of these TFTs are turned on, the voltage supplied to the gradation voltage line V4 is applied to the first output line (H ) 108-
1 is supplied.

Next, paying attention to the gradation voltage line V3, a circuit in which two N-channel TFTs (Tr3,1 and Tr3,2) are connected in series and two P-channel TFTs (Tr3,3) are connected. And a circuit in which Tr3,4) are connected in series, and both ends of the circuit formed by connecting the two circuits in series are connected in parallel to the gradation voltage line V3. The signal lines a and b from the latch circuit, the inverted a and the inverted b are connected to the gate electrodes of Tr3,1, Tr3,4, Tr3,3 and Tr3,2, respectively. The switching of Tr3,1, Tr3,2, Tr3,3, Tr3,4 is controlled by digital signals supplied to these signal lines a, b, inverted a, and inverted b, and all the TFTs are turned ON. At this time, the voltage supplied to the gradation voltage line V3 is changed to the first output line (H) 10
8-1.

In the gradation voltage line V3, two N
A circuit in which channel TFTs (Tr3,5 and Tr3,6) are connected in series and a circuit in which two P-channel TFTs (Tr3,7 and Tr3,8) are connected in series are connected in series Both ends of the circuit formed by connecting the two circuits in series are further connected in parallel to the gradation voltage line V3. The signal lines a and b from the latch circuit and the inverted a and the inverted b are Tr3,5, Tr3,6, Tr3,7, Tr3,8, respectively.
Is connected to the gate electrode. When all these TFTs are turned on, the voltage supplied to the gradation voltage line V3 is supplied to the first output line (L) 108-2.

Next, focusing on the gradation voltage line V2, a circuit in which two N-channel TFTs (Tr2,1 and Tr2,2) are connected in series and two P-channel TFTs (Tr2,3) are connected. And a circuit in which Tr2,4) are connected in series, and both ends of the circuit formed by connecting the two circuits in series are connected in parallel to the gradation voltage line V2. The signal lines a and b from the latch circuit and the inverted a and inverted b are connected to the gate electrodes of Tr2,3, Tr2,2, Tr2,1 and Tr2,4, respectively. When all these TFTs are turned on, the voltage supplied to the gradation voltage line V2 is supplied to the first output line (H) 108-1.

In the gradation voltage line V2, two N
A circuit in which channel TFTs (Tr2,5 and Tr2,6) are connected in series and a circuit in which two P-channel TFTs (Tr2,7 and Tr2,8) are connected in series are connected in series Both ends of a circuit formed by connecting the two circuits in series are further connected in parallel to the gradation voltage line V2. The signal lines a and b from the latch circuit and the inverted a and the inverted b are Tr2,5, Tr2,8, Tr2,7, Tr2,6, respectively.
Is connected to the gate electrode. When all of these TFTs are turned on, the voltage supplied to the gradation voltage line V2 is supplied to the first output line (L) 108-2.

The circuit having the above-described configuration is also connected in parallel to the gradation voltage line V1. The signal lines a and b from the latch circuit and the inverted a and inverted b are connected to the gate electrodes of Tr1,3, Tr1,4, Tr1,1 and Tr1,2, respectively. When all these TFTs are turned on,
The voltage supplied to the gradation voltage line V1 is the first output line (H)
108-1. The signal lines a and b from the latch circuit, the inverted a and the inverted b are Tr1,7 and Tr, respectively.
1, 6, Tr1, 5, and Tr1, 8 are connected to the gate electrodes.
When all of these TFTs are turned on, the gradation voltage line V1
Is supplied to the first output line (L) 108-2.

The circuit having the above-described configuration is also connected in parallel to the gradation voltage line V0. The signal lines a and b from the latch circuit and the inverted a and inverted b are connected to the gate electrodes of Tr0,3, Tr0,4, Tr0,1, and Tr0,2, respectively. When all these TFTs are turned on,
The voltage supplied to the gradation voltage line V0 is the first output line (L)
108-2.

Table 1 below shows the combinations of the digital signals supplied to the signal lines a and b and the inverted a and the inverted b.
First output lines (H) 108-1 and (L) 108-2
Shows the combinations of the gray scale voltage lines output in FIG.

[0076]

[Table 1]

Two adjacent gray scale voltage lines are selected by the digital signals input to the signal lines a and b and the inverted a and the inverted b, and the first output line (H) 108-1 and the first Table 1 shows that the signal is supplied to the output line (L) 108-2.

On the other hand, the second D / A conversion circuit 114
N-channel TFTs (Tr5,1, Tr5,2, Tr6,1, Tr6,
2, Tr7,1, Tr7,2, Tr8,1, Tr8,2) and eight P-channel TFTs (Tr5,3, Tr5,4, Tr6,3, Tr6,4, Tr7,3)
, Tr7,4, Tr8,3, Tr8,4) and four resistors (R1-R
4).

In the second D / A conversion circuit 114,
First output line (H) 10 of first D / A conversion circuit 106
8-1 and the first output line (L) 108-2 are connected by four serially connected resistors (R1 to R4). With such a configuration, the second D / A conversion circuit 1
14 produces four different voltages.

Focusing on the connection point between the resistors R1 and R2, two N-channel TFTs (Tr8,1 and Tr8,2)
Connected in series and two P-channel TFTs
(Tr8,3 and Tr8,4) are connected in series, and both ends of the circuit formed by connecting the two circuits in series are connected to the connection point between the resistors R1 and R2. It is connected. Since the digital signals from the address lines c and d are supplied to the second D / A conversion circuit via the latch circuit, the signal lines supplied from the latch circuit are referred to as c and d for convenience of explanation. Let d be these inverted signals (inverted c and d).

The signal lines c and d from the latch circuit, the inverted c and the inverted d are Tr8,1, Tr8,2, Tr8,3 respectively.
, Tr8,4. When all these TFTs are turned on, the first output line (H) 108
A voltage obtained by subtracting only the voltage drop at the resistor R1 from the voltage supplied to −1 is supplied to the second output line 115. In other words, the voltage supplied to the second output line 115 is
The voltage is obtained by adding the voltage supplied to the first output line (L) 108-2 by the voltage drop by the resistor (R2 + R3 + R4). Therefore, the voltage supplied to the second output line is
It is kept constant irrespective of the potential of the output pixel TFT.

Next, focusing on the connection point between the resistors R2 and R3, two N-channel TFTs (Tr7,1 and Tr7,2
) Are connected in series, and two P-channel T
A circuit in which FTs (Tr7,3 and Tr7,4) are connected in series is connected in series, and both ends of the circuit formed by connecting the two circuits in series are connected to a connection point between resistors R2 and R3. It is connected to the. Also, a signal line c from the latch circuit,
d, inverted c and inverted d are Tr7,1, Tr7,4,
It is connected to the gate electrodes of Tr7,3 and Tr7,2. When all these TFTs are turned on, the first output line (H) 1
A voltage obtained by subtracting only the voltage drop by the resistor (R1 + R2) from the voltage supplied to 08-1 is supplied to the second output line 115. In other words, the voltage supplied to the second output line 115 is a voltage obtained by adding the voltage supplied to the first output line (L) 108-2 by the voltage drop by the resistor (R3 + R4). Therefore, also in this case, the voltage supplied to the second output line is kept constant irrespective of the potential of the output destination pixel TFT.

Next, focusing on the connection point between the resistors R3 and R4, two N-channel TFTs (Tr6,1 and Tr6,
2) are connected in series, and two P-channel T
A circuit in which FTs (Tr6,3 and Tr6,4) are connected in series is connected in series, and both ends of the circuit formed by connecting the two circuits in series are connected to a connection point between resistors R3 and R4. It is connected to the. Also, a signal line c from the latch circuit,
d, inverted c and inverted d are Tr6,4, Tr6,2,
It is connected to the gate electrodes of Tr6,1 and Tr6,3. When all these TFTs are turned on, the first output line (H) 1
08-1 to the resistor (R1 + R2 + R
The voltage obtained by subtracting only the voltage drop in 3) is supplied to the second output line 115. In other words, the second output line 11
5 is supplied to the first output line (L) 108-2.
Is obtained by adding only the voltage drop by the resistor R4 to the voltage supplied to the resistor R4. Therefore, also in this case, the voltage supplied to the second output line is kept constant irrespective of the potential of the output destination pixel TFT.

Next, the resistor R4 and the first output line (L) 10
8-2, two N-channel type T
A circuit in which FTs (Tr5,1 and Tr5,2) are connected in series, and two P-channel TFTs (Tr5,3 and Tr5,4)
Are connected in series with each other, and both ends of a circuit formed by connecting the two circuits in series are connected to a connection point between a resistor R4 and a first output line (L) 108-2. It is connected to the. Also, signal lines c, d,
Inversion c and inversion d are Tr5,4, Tr5,3, Tr5,2, respectively.
, Tr5,1 are connected to the gate electrodes. When all these TFTs are turned on, the first output line (H) 108
-1 to the resistor (R1 + R2 + R3 + R
The voltage obtained by subtracting only the voltage drop in 4) is supplied to the second output line 115. In other words, the second output line 11
5 is supplied to the first output line (L) 108-2.
Is the voltage supplied to Therefore, also in this case, the voltage supplied to the second output line is kept constant irrespective of the potential of the output destination pixel TFT.

Note that the first D / A conversion circuit 106
Of the second D / D signal by the combination of the gradation voltage lines output from the output lines (H) 108-1 and (L) 108-2.
The current flowing through the A conversion circuit 114 changes. Therefore, the current flowing through the second D / A conversion circuit 114 is shown in Table 2 as I ₁ to I ₁ .
It is defined as I _4.

[0086]

[Table 2]

Here, the signal lines a, b, and
It shows the voltage finally output to the second output line 115 by the combination of the digital signals supplied to c, d, inverted a, inverted b, inverted c, and inverted d.

[0088]

[Table 3]

Signal lines a, b, c, d, inverted a, inverted b,
Table 3 shows that 16 different voltages are output to the second output line 115 according to the digital signals input to the inverted c and the inverted d.

Therefore, in the present embodiment, four gradation voltages can be selected by the upper two-bit digital signal of the four-bit digital signal, and four more gradation voltages are selected from the gradation voltage selected by the lower four bits. It is possible to output different gray scale voltages. Therefore, 4 (upper 2 bits) × 4
(Lower 2 bits) = 16 gradation voltages can be arbitrarily selected.

The D / A conversion circuit of this embodiment is similar to that of FIG.
As can be understood from the above, the number of gradation voltage lines is 5, and the number of switches is 12. This requires a smaller area as compared with a conventional D / A conversion circuit, and can realize a reduction in the size of the entire driving circuit. further,
Since the size of the D / A conversion circuit can be reduced, high definition of the active matrix liquid crystal display device can be realized.

Further, as described above, the D / A conversion circuit of the present embodiment is capable of performing the second D / A conversion even when the potential of the pixel TFT changes.
Since the voltage supplied from the second output line of the A conversion circuit is always stable, a stable voltage can be supplied to the pixel TFT.

In this embodiment, the 4-bit digital signal is divided into upper 2 bits and lower 2 bits, each of which controls the switching between swA, swB and swC. The division of the signal is not limited to this.

For example, the upper 3 bits are swA and sw
B can be used for switching, and the lower 1 bit can be used for swC switching. In this case, swA
The number of internal switches for swB and swB is eight (swA1 to swA8, swB1 to swB8), respectively, and the number of gray scale voltage lines is nine (V0 to V8). Also, sw
C has two internal switches (swC1 and swC
2), and the number of resistors is two (R1 and R2). A 3-bit digital signal is input to swA, and sw
One of the eight internal switches of A is closed, one gray scale voltage line is selected, and the voltage is supplied to the first output line (H). Also, a 3-bit digital signal is input to swB, one of the eight internal switches of swB is closed, one gray scale voltage line is selected, and the voltage is supplied to the first output line (L). You. A 1-bit digital signal is input to swC, one of the two internal switches of swC is closed, and the corresponding gray scale voltage is supplied to the second output line. The gray scale voltage supplied to the second output line is supplied to a source signal line through a buffer or the like.

In this embodiment, the D / A conversion circuit for handling a 4-bit digital signal has been described. However, according to the present invention, a D / A for handling an n-bit (n is a natural number of 2 or more) digital signal is used. A conversion circuit can be realized. in this case,
An n-bit digital signal can be divided into upper x bits and lower y bits and captured (x + y = n). In this case, the number of swA internal switches is 2 ^x (swA1
To swA2 ^x ), and the number of swB internal switches is also 2 ^x (swB1 to swB2 ^x ). Further, the number of gradation voltage lines is (2 ^× + 1). Furthermore, sw
The number of internal switches of C is 2 ^y (swC1 to swC
2 ^y ), and the number of resistors is also 2 ^y (R1 to R2 ^y ).

Here, (2)^x+1) gradation voltage lines
And the grayscale voltage line to which the lowest voltage is applied
Gradation voltage line, and the gradation to which the highest voltage is applied
Connect the voltage line to the (2^x+1) gradation voltage line
You. In this case, the first and second (2 ^x+1)
Thus, a higher voltage is supplied.

The z-th and (z + 1) -th gradation voltage lines are selected from among (2 ^x +1) gradation voltage lines by the upper x bits of the n-bit digital signal (1 ≦ z ≦ 2 ^x ;
z is a natural number), and assuming that the grayscale voltages are output to the first output lines (H) and (L), the grayscale voltages are supplied to the selected zth and (z + 1) th grayscale voltage lines. The 2 ^y resistors (R1 to R1) of the second D / A conversion circuit
2 ^y ) produces different 2 ^y gray scale voltages. Then, by the lower y bits of the n-bit digital signal,
Corresponding voltage of 2 ^y voltages is selected and supplied to the second output line.

As described above, when an n-bit digital signal is divided into upper x bits and lower y bits and used, the number of selectable gradation voltages is 2 ^x (upper x bits) × 2 ^y (lower y bits) = 2 ^{(x + y)} = 2 ⁿ , and also in this case, the number of gradation voltages is not reduced.

Here, a method of manufacturing an active matrix type liquid crystal display device having the D / A conversion circuit of this embodiment will be described below. The following manufacturing method is merely an example of the present invention, and the D / A conversion circuit of the present invention can be realized by another manufacturing method.

Here, a plurality of TFTs are formed on a substrate having an insulating surface, and a pixel matrix circuit and the D /
FIGS. 10 to 13 show examples in which a drive circuit including an A conversion circuit, a logic circuit, and the like are monolithically configured. In this embodiment, it is assumed that one pixel of the pixel matrix circuit and a CMOS circuit which is a basic circuit of another circuit (a driving circuit including a D / A conversion circuit, a logic circuit, and the like) are formed at the same time. Show. In this embodiment, the manufacturing process of a case where each of the P-channel TFT and the N-channel TFT has one gate electrode will be described. However, a plurality of gate electrodes such as a double gate type and a triple gate type are described. A CMOS circuit using a TFT having a gate electrode can be manufactured in the same manner.

Referring to FIG. First, a quartz substrate 1001 is prepared as a substrate having an insulating surface. A silicon substrate on which a thermal oxide film is formed can be used instead of the quartz substrate. Alternatively, a method may be employed in which an amorphous silicon film is formed once on a quartz substrate and then completely thermally oxidized to form an insulating film. Further, a quartz substrate, a ceramics substrate, or a silicon substrate on which a silicon nitride film is formed as an insulating film may be used.

Reference numeral 1002 denotes an amorphous silicon film having a final film thickness (thickness in consideration of film reduction after thermal oxidation) of 10 to 75.
nm (preferably 15 to 45 nm). It is important to thoroughly control the impurity concentration in the film when forming the film.

In the case of this embodiment, in the amorphous silicon film 1002, C (carbon) and N, which are impurities that inhibit crystallization, are used.
The concentration of (nitrogen) was 5 × 10 ¹⁸ atoms / cm
Less than ³ (typically 5 × 10 ¹⁷ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less);
O (oxygen) is controlled to be less than 1.5 × 10 ¹⁹ atoms / cm ³ (typically 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 5 × 10 ¹⁷ atoms / cm ³ or less). This is because, if each impurity is present at a higher concentration, it will have an adverse effect on the subsequent crystallization and cause a deterioration in the film quality after the crystallization. In this specification, the above-mentioned impurity element concentration in a film is defined by a minimum value in a measurement result of SIMS (Secondary Mass Ion Analysis).

In order to obtain the above structure, it is desirable that the reduced pressure thermal CVD furnace used in this embodiment is periodically subjected to dry cleaning to clean the film forming chamber. Dry cleaning is performed in a furnace heated to about 200 to 400 ° C.
A film formation chamber may be cleaned by flowing ClF ₃ (chlorine fluoride) gas at a flow rate of 00 to 300 sccm and using fluorine generated by thermal decomposition.

According to the knowledge of the present applicant, the furnace temperature 3
00 ° C. and the flow rate of ClF ₃ (chlorine fluoride) gas is 30
When the thickness is set to 0 sccm, it is possible to completely remove the attached matter (mainly composed mainly of silicon) having a thickness of about 2 μm in 4 hours.

The hydrogen concentration in the amorphous silicon film 1002 is also a very important parameter, and a film having a good crystallinity can be obtained by suppressing the hydrogen content to a low level. Therefore, the amorphous silicon film 1002 is preferably formed by a low-pressure thermal CVD method. Note that the plasma CVD method can be used by optimizing the film formation conditions.

Next, a crystallization step of the amorphous silicon film 1002 is performed. As a means for crystallization, JP-A-7-130652
The technology described in Japanese Patent Application Publication No. H10-260926 is used. Although any of the means of Embodiment 1 and Embodiment 2 of the publication may be used, in this embodiment, the technical contents described in Embodiment 2 of the publication (Japanese Patent Laid-Open No. 8-7832) will be described.
No. 9 is preferred).

The technique described in Japanese Patent Application Laid-Open No. H8-78329 is based on a technique of first using a mask insulating film 1 for selecting a region to which a catalytic element is added.
003 is formed. The mask insulating film 1003 has a plurality of openings for adding a catalyst element. The position of the crystal region can be determined by the position of the opening.

Then, a solution containing nickel (Ni) as a catalyst element for promoting crystallization of the amorphous silicon film is applied by spin coating to form a Ni-containing layer 1004. In addition, as a catalyst element, in addition to nickel, cobalt (Co), iron (Fe), palladium (Pd), germanium (Ge), platinum (Pt), copper (Cu), and gold (A
u) and the like can be used (FIG. 10A).

In the step of adding the catalyst element, an ion implantation method using a resist mask or a plasma doping method can be used. In this case, the reduction of the occupied area of the addition region and the control of the growth distance of the lateral growth region are facilitated, so that this is an effective technique when configuring a miniaturized circuit.

Next, when the step of adding the catalyst element is completed,
After dehydrogenation at 450 ° C for about 1 hour, inert atmosphere,
500 to 700 in a hydrogen atmosphere or an oxygen atmosphere
The amorphous silicon film 1002 is crystallized by applying a heat treatment at a temperature of 550C (typically 550 to 650C) for 4 to 24 hours. In this embodiment, heat treatment is performed at 570 ° C. for 14 hours in a nitrogen atmosphere.

At this time, the crystallization of the amorphous silicon film 1002 proceeds preferentially from the nuclei generated in the nickel-added regions 1005 and 1006, and the crystal region grown almost parallel to the substrate surface of the substrate 1001. 1007 and 100
8 are formed. These crystal regions 1007 and 1008
Is called a lateral growth region. Since individual crystals are aggregated in a relatively uniform state in the lateral growth region, there is an advantage that the overall crystallinity is excellent (FIG. 10B).

When the technique described in the first embodiment of JP-A-7-130652 is used, an area which can be microscopically called a lateral growth area is formed. However, since nucleation occurs unevenly in the plane, there is a difficulty in controllability of crystal grain boundaries.

After the heat treatment for crystallization is completed, the mask insulating film 1003 is removed and patterning is performed to form island-like semiconductor layers (active layers) 1009, 1010, and 1011 composed of the lateral growth regions 1007 and 1008. (FIG. 10C).

Here, reference numeral 1009 denotes an active layer of an N-channel TFT forming a CMOS circuit, 1010 denotes an active layer of a P-channel TFT forming a CMOS circuit, and 1011 denotes an N-channel TFT (pixel TFT) forming a pixel matrix circuit. ) Of the active layer.

Active layers 1009, 1010, and 101
After forming the gate insulating film 1, a gate insulating film 1012 made of an insulating film containing silicon is formed thereon (FIG. 10C).

Next, as shown in FIG. 10 (D), a heat treatment (a catalytic element gettering process) for removing or reducing the catalytic element (nickel) is performed. In this heat treatment, a halogen element is contained in the treatment atmosphere, and the gettering effect of the metal element by the halogen element is used.

In order to sufficiently obtain the gettering effect by the halogen element, it is preferable that the heat treatment is performed at a temperature exceeding 700 ° C. Below this temperature, the decomposition of the halogen compound in the processing atmosphere becomes difficult, and the gettering effect may not be obtained.

For this reason, in this embodiment, this heat treatment is
It is carried out at a temperature exceeding 0 ° C., preferably 800 to 1000
° C (typically 950 ° C) and the treatment time is 0.1 to 6
hr, typically 0.5 to 1 hr.

In this embodiment, in an atmosphere containing hydrogen chloride (HCl) at a concentration of 0.5 to 10% by volume (3% by volume in this embodiment) with respect to an oxygen atmosphere, 9%
An example in which heat treatment is performed at 50 ° C. for 30 minutes will be described. When the HCl concentration is equal to or higher than the above concentration, the active layers 1009, 101
This is not preferable because irregularities having a thickness of about 0 and 1011 occur on the surface.

Further, as a compound containing a halogen element, HC
Although the example using 1 gas was shown, as other gas,
Typically, HF, NF ₃ , HBr, Cl ₂ , ClF ₃ ,
One or more compounds selected from compounds containing halogen such as BCl ₂ , F ₂ , and Br ₂ can be used.

In this step, the active layers 1009, 109
It is considered that nickel in 10 and 1011 is gettered by the action of chlorine, becomes volatile nickel chloride, escapes to the atmosphere and is removed. By this step, the concentration of nickel in the active layers 1009, 1010, and 1011 is reduced to 5 × 10 ¹⁷ atoms / cm ³ or less.

The value of 5 × 10 ¹⁷ atoms / cm ³ is the lower detection limit of SIMS (Secondary Mass Ion Analysis). As a result of analyzing a TFT manufactured by the present applicant, 1 × 1
0 ¹⁸ atoms / cm ³ or less (preferably 5 × 10 ¹⁷ a
(toms / cm ³ or less), the effect of nickel on the TFT characteristics was not confirmed. However, the impurity concentration in this specification is defined by the minimum value of the measurement result of the SIMS analysis.

The active layer 100 is formed by the above heat treatment.
9, 1010, and 1011 and gate insulating film 1012
A thermal oxidation reaction proceeds at the interface with the gate insulating film 1012, and the thickness of the gate insulating film 1012 increases by the amount of the thermal oxide film. When a thermal oxide film is formed in this manner, a semiconductor with a very low interface state
An insulating film interface can be obtained. Further, there is also an effect of preventing formation failure (edge thinning) of a thermal oxide film at an end of the active layer.

The catalytic element gettering process may be performed after removing the mask insulating film 1003 and before patterning the active layer. Further, the gettering process of the catalytic element may be performed after patterning the active layer. Further, any gettering process may be performed in combination.

Note that the catalyst element gettering process can also be performed by using P (phosphorus). The phosphorus gettering process may be combined with the above-described gettering process. Alternatively, only the gettering process using phosphorus may be used.

It is also effective to improve the film quality of the gate insulating film 1012 by performing a heat treatment at 950 ° C. for about 1 hour in a nitrogen atmosphere after the heat treatment in the halogen atmosphere.

Note that the active layer 100 was determined by SIMS analysis.
In 9, 10, 10 and 1011, the halogen element used for the gettering treatment was 1 × 10 ¹⁵ atoms / c.
It has also been confirmed that it remains at a concentration of m ³ to 1 × 10 ²⁰ atoms / cm ³ . At that time, the active layer 100
It has been confirmed by SIMS analysis that the above-mentioned halogen element is distributed at a high concentration between 9, 10, 10 and 1011 and the thermal oxide film formed by the heat treatment.

[0129] SIMS analysis of other elements showed that typical impurities C (carbon), N (nitrogen), O (oxygen), and S (sulfur) were all 5 × 10 ¹⁸ a.
less than toms / cm ³ (typically 1 × 10 ¹⁸ atoms
s / cm ³ or less).

Then, a metal film (not shown) containing aluminum as a main component is formed and patterned to form prototypes of gate electrodes 1013, 1014, and 101 later.
5 is formed. In this embodiment, an aluminum film containing 2 wt% of scandium is used (FIG. 11A).

Instead of the metal film containing aluminum as a main component, a polycrystalline silicon film in which impurities are added to the gate electrode may be used.

Next, a porous anodic oxide film 1016, 1017,
And 1018, non-porous anodic oxide films 1019 and 102
0 and 1021, gate electrodes 1022, 1023,
And 1024 (FIG. 11B).

When the state shown in FIG. 11B is obtained, gate electrodes 1022, 1023, and 1022 are next obtained.
4. Porous anodic oxide films 1016, 1017, and 1
The gate insulating film 1012 is etched using 018 as a mask. Then, the porous anodic oxide films 1016 and 101
7 and 1018 are removed to obtain the state of FIG. Note that in FIG. 11C, 1025, 1026,
Reference numerals 1027 and 1027 denote the processed gate insulating films.

Next, a step of adding an impurity element imparting one conductivity is performed. As an impurity element, P (phosphorus) or As (arsenic) may be used for an N-channel type, and B (boron) or Ga (gallium) may be used for a P-type.

In this embodiment, the impurity addition for forming the N-channel and P-channel TFTs is performed in two steps.

First, an impurity is added for forming an N-channel TFT. First, the first impurity addition (in this embodiment, P (phosphorus) is used) is performed at a high accelerating voltage 80.
This is performed at about keV to form an n ^- region. This n ⁻ region has a P ion concentration of 1 × 10 ¹⁸ atoms / cm ³ to 1
Adjust so as to be × 10 ¹⁹ atoms / cm ³ .

Further, the second impurity addition is performed at a low acceleration voltage of about 10 keV to form an n ⁺ region. At this time, since the acceleration voltage is low, the gate insulating film functions as a mask. The n ⁺ region has a sheet resistance of 500
It is adjusted so as to be Ω or less (preferably 300 Ω or less).

Through the above steps, a source region 1028, a drain region 1029, a low-concentration impurity region 1030, and a channel formation region 1031 of an N-channel TFT forming a CMOS circuit are formed. In addition, a source region 1032, a drain region 1033, a low-concentration impurity region 1034, and a channel formation region 1035 of an N-channel TFT forming a pixel TFT are determined (FIG. 11D).

In the state shown in FIG.
The active layer of the P-channel TFT forming the S circuit has the same configuration as the active layer of the N-channel TFT.

Next, as shown in FIG. 12A, a resist mask 1036 is provided to cover the N-channel type TFT.
Addition of an impurity ion imparting P-type (boron is used in this embodiment) is performed.

This step is also performed in two steps, similarly to the above-described impurity doping step. However, since it is necessary to invert the N-channel type to the P-channel type, the concentration is about several times the above-mentioned P ion addition concentration. B (boron) ion is added.

Thus, the source region 1037 and the drain region 103 of the P-channel TFT constituting the CMOS circuit
8, low concentration impurity region 1039, channel formation region 10
40 are formed (FIG. 12A).

When the active layer is completed as described above, activation of impurity ions is performed by a combination of furnace annealing, laser annealing, lamp annealing and the like. At the same time, the damage of the active layer in the addition step is also repaired.

Next, a stacked film of a silicon oxide film and a silicon nitride film is formed as an interlayer insulating film 1041, a contact hole is formed, and source electrodes 1042, 1043, and 1044, and drain electrodes 1045 and 1046 are formed. Thus, the state shown in FIG. The interlayer insulating film 10
As 41, an organic resin film can be used.

When the state shown in FIG. 12B is obtained, the first interlayer insulating film 1047 made of an organic resin film is
It is formed to a thickness of ３3 μm. As the organic resin film, polyimide, acrylic, polyimide amide or the like is used. The advantage of the organic resin film is that the film formation method is simple,
There are a point that the film thickness can be easily increased, a point that the parasitic capacitance can be reduced because the relative dielectric constant is low, and a point that the flatness is excellent. Note that an organic resin film other than those described above can be used.

Next, a black mask 1048 made of a light-shielding film is formed on the first interlayer insulating film 1047 by 100 n.
m. Although a titanium film is used as the black mask 1048 in this embodiment, a resin film or the like containing a black pigment may be used.

[0147] When a titanium film is used for the black mask 1048, part of a wiring in a driver circuit and other peripheral circuit portions can be formed using titanium. This titanium wiring can be formed at the same time when the black mask 1048 is formed.

After the formation of the black mask 1048, any one of a silicon oxide film, a silicon nitride film, an organic resin film or a laminated film thereof is formed to a thickness of 0.1 to 0.3 μm as the second interlayer insulating film 1049. Form. Then, a contact hole is formed in the interlayer insulating film 1047 and the interlayer insulating film 1049, and the pixel electrode 1050 is formed to a thickness of 120 nm. According to the configuration of the present embodiment, the black mask 10
An auxiliary capacitance is formed in a region where the pixel electrode 48 overlaps the pixel electrode 1050 (FIG. 12C). Note that since this embodiment is an example of a transmission type active matrix liquid crystal display device, a transparent conductive film such as ITO is used as a conductive film forming the pixel electrode 1050.

Next, the entire substrate is heated in a hydrogen atmosphere at 350 ° C. for 1 to 2 hours, and hydrogenation of the entire device is performed, whereby dangling bonds (unpaired bonds) in the film (especially in the active layer) are formed.
To compensate. Through the above steps, a CMOS circuit and a pixel matrix circuit can be manufactured over the same substrate.

Next, as shown in FIG. 13, based on the active matrix substrate manufactured by the above steps,
A process for manufacturing an active matrix liquid crystal display device will be described.

An orientation film 1051 is formed on the active matrix substrate in the state shown in FIG. In this embodiment, polyimide is used for the alignment film 1051. Next, a counter substrate is prepared. The counter substrate includes a glass substrate 1052, a transparent conductive film 1053, and an alignment film 1054.

In this embodiment, a polyimide film in which liquid crystal molecules are aligned parallel to the substrate is used as the alignment film. After the alignment film was formed, a rubbing treatment was performed so that the liquid crystal molecules were aligned in parallel with a certain pretilt angle.

Next, the active matrix substrate and the counter substrate that have undergone the above-described steps are subjected to a well-known cell assembling step.
It is bonded via a sealing material or a spacer (both not shown). Thereafter, a liquid crystal material 1055 is injected between the two substrates, and completely sealed with a sealing agent (not shown). Thus, a transmission type active matrix liquid crystal display device as shown in FIG. 13 is completed.

In this embodiment, the liquid crystal panel performs display in a TN (twisted nematic) mode. Therefore, a pair of polarizing plates (not shown) are arranged so as to sandwich the liquid crystal panel in a crossed Nicols state (a state in which the pair of polarizing plates makes their polarization axes orthogonal to each other).

Therefore, in this embodiment, it is understood that the display is performed in a so-called normally white mode, which is a white display when no voltage is applied to the liquid crystal display device.

In the liquid crystal panel of this embodiment, only the end face on which the FPC is mounted has the active matrix substrate exposed outside, and the remaining three end faces are aligned.

According to the manufacturing method described above, the D
It is understood that the / A conversion circuit can be integrally formed on an insulating substrate such as a quartz substrate or a glass substrate together with other driving circuits and other peripheral devices of the active matrix liquid crystal display device. Further, two P-channel TFTs and two N-channel TFTs connected to the respective gradation voltage lines of the D / A conversion circuit of the present embodiment may be formed on the same semiconductor layer. . Alternatively, two independent P-channel TFs
T and two independent N-channel TFTs may be connected by metal wiring or the like via contacts. However, the former case is preferable because the area of the D / A conversion circuit can be further reduced.

Here, a semiconductor thin film manufactured by the manufacturing method of this embodiment will be described. According to the manufacturing method of this embodiment described above, the amorphous silicon film is crystallized to form continuous grain silicon (so-called continuous grain silicon).
n: CGS) can be obtained.

The lateral growth region of the semiconductor thin film obtained by the manufacturing method of this embodiment has a unique crystal structure composed of an aggregate of rod-shaped or flat rod-shaped crystals. The features are described below.

[Knowledge on Crystal Structure of Lateral Growth Region]

The lateral growth region formed according to the manufacturing process of the above embodiment has a crystal structure in which a plurality of rod-shaped (or flat rod-shaped) crystals are microscopically arranged substantially parallel to each other with regularity in a specific direction. . This can be easily confirmed by observation with a TEM (transmission electron microscope).

The present inventors have found that the crystal grain boundary of the semiconductor thin film obtained by the above-described manufacturing method of the present embodiment is HR-
It was observed in detail by TEM (high resolution transmission electron microscopy) (FIG. 24). However, in this specification, a crystal grain boundary is defined as a grain boundary formed at a boundary where different rod-shaped crystals are in contact with each other unless otherwise specified. Therefore, for example, it is considered separately from a grain boundary in a macro sense such that separate lateral growth regions are formed by collision.

By the way, the above-mentioned HR-TEM (high-resolution transmission electron microscopy) means that a sample is irradiated with an electron beam perpendicularly, and the atomic / molecular arrangement is made utilizing the interference of transmitted electrons and elastically scattered electrons. It is a technique to evaluate. By using the same technique, it is possible to observe the arrangement state of the crystal lattice as lattice fringes. Therefore, by observing the crystal grain boundaries, it is possible to estimate the bonding state between atoms at the crystal grain boundaries.

In the TEM photograph (FIG. 24) obtained by the present applicant, a state where two different crystal grains (rod-shaped crystal grains) were in contact at the crystal grain boundary was clearly observed. At this time, although the two crystal grains have a slight shift in the crystal axis, the difference is approximately {1}.
It has been confirmed by electron beam diffraction that the orientation is 10 °.

In the lattice fringe observation using the TEM photograph as described above, lattice fringes corresponding to the {111} plane were observed in the {110} plane. Note that the lattice fringe corresponding to the {111} plane indicates a lattice fringe such that a {111} plane appears in a cross section when a crystal grain is cut along the lattice fringe.
What plane the lattice pattern corresponds to can be simply confirmed by the distance between the lattice patterns.

At this time, as a result of observing the TEM photograph of the semiconductor thin film obtained by the above-described manufacturing method of the present embodiment in detail, the applicants obtained a very interesting finding. In each of the two different crystal grains seen in the photograph, lattice fringes corresponding to the {111} plane were visible. And it was observed that the grids of each other were running clearly parallel.

Further, regardless of the existence of the crystal grain boundaries, lattice fringes of two different crystal grains were connected so as to cross the crystal grain boundaries. That is, it was confirmed that most of the lattice fringes observed so as to cross the crystal grain boundaries were linearly continuous in spite of the lattice fringes of different crystal grains. This was similar at any grain boundaries.

Such a crystal structure (accurately, a structure of a crystal grain boundary) indicates that two different crystal grains are bonded to each other with extremely high consistency at the crystal grain boundary. That is, the crystal lattice is continuously connected at the crystal grain boundary, and it is very difficult to form a trap level due to a crystal defect or the like. In other words, it can be said that the crystal lattice has continuity at the crystal grain boundaries.

In FIG. 25, the present inventors also analyzed a conventional polycrystalline silicon film (a so-called high-temperature polysilicon film) by electron beam diffraction and HR-TEM observation as a reference. As a result, the lattice fringes of the two different crystal grains ran completely differently from each other, and there was hardly any joint that continued with good consistency at the crystal grain boundaries. That is, it was found that there were many portions where the lattice fringes were interrupted at the crystal grain boundaries, and that there were many crystal defects.

The present applicants refer to the bonding state of atoms when lattice fringes correspond with good matching like a semiconductor thin film used in a liquid crystal panel of an active matrix type liquid crystal display device of the present invention. A bond is called a matching bond. On the other hand, the bonding state of atoms when lattice fringes do not correspond with good consistency, as is often seen in conventional polycrystalline silicon films, is called a mismatched bond, and the bond at that time is a mismatched bond (or unpaired bond). Hand).

Since the semiconductor thin film used in the present invention has extremely excellent matching at the crystal grain boundaries, the above-mentioned mismatching bonds are extremely small. As a result of investigation by the present inventors on an arbitrary plurality of crystal grain boundaries, the proportion of mismatched bonds to the entire bonds is 10% or less (preferably 5% or less, more preferably 3% or less). . That is, 90% or more of the total bonds (preferably 95% or more, more preferably
(97% or more) are composed of matching bonds.

FIG. 26 shows the result of observing the lateral growth region produced according to the production steps of this embodiment by electron beam diffraction.
(A). FIG. 26B is an electron diffraction pattern of a conventional polysilicon film (called a high-temperature polysilicon film) observed for comparison.

In the electron beam diffraction patterns shown in FIGS. 26A and 26B, the diameter of the irradiation area of the electron beam is 4.25 μm, and information of a sufficiently wide area is picked up. The photograph shown here is a representative diffraction pattern as a result of examining arbitrary plural places.

In the case of FIG. 26A, diffraction spots (diffraction spots) corresponding to <110> incidence appear relatively clearly, and almost all crystal grains are oriented {110} in the electron beam irradiation area. Can be confirmed. On the other hand, FIG.
In the case of the conventional high-temperature polysilicon film shown in FIG. 6B, no clear regularity was observed in the diffraction spot, and it was found that crystal grains having a plane orientation other than the {110} plane were irregularly mixed.

As described above, the semiconductor thin film used in the present invention is characterized by exhibiting an electron beam diffraction pattern having a regularity specific to {110} orientation while being a semiconductor thin film having a crystal grain boundary. The difference from the conventional semiconductor thin film is clear when the line diffraction patterns are compared.

As described above, the semiconductor thin film manufactured in the manufacturing process of this embodiment was a semiconductor thin film having a crystal structure completely different from a conventional semiconductor thin film (more precisely, a structure of crystal grain boundaries). The present applicants have analyzed the results of the analysis of the semiconductor thin film used in the present invention and filed Japanese Patent Application Nos. 9-55633 and 9-165216.
No. 9-212428.

Further, since 90% or more of the crystal grain boundaries of the semiconductor thin film used in the present invention are constituted by matching bonds, the function as a barrier that hinders the movement of carriers is as follows. Almost no. That is, it can be said that the semiconductor thin film used in the present invention has substantially no crystal grain boundaries.

In the conventional semiconductor thin film, the crystal grain boundary has functioned as a barrier to hinder the movement of carriers. However, in the semiconductor thin film used in the present invention, since such a crystal grain boundary does not substantially exist, high carrier migration occurs. Degree is realized. Therefore, the electrical characteristics of the TFT manufactured using the semiconductor thin film used in the present invention show extremely excellent values. This is shown below.

[Knowledge on Electrical Characteristics of TFT]

Since the semiconductor thin film used in the present invention can be regarded as substantially a single crystal (substantially, there is no crystal grain boundary), a TFT using the active layer as an active layer is equivalent to a MOSFET using single crystal silicon. Show characteristics. The following data is obtained from the TFT prototyped by the present inventors.

(1) Switching performance of TFT (on /
The subthreshold coefficient as an index of the agility of switching off operation is 60 to 100 mV / decade (typically 60 to 85 mV) for both the N-channel TFT and the P-channel TFT.
/ decade) and small. (2) The field effect mobility (μ _FE ) as an index of the operation speed of the TFT is 200 to 650 cm ² / Vs for the N-channel TFT.
(Typically 250-300cm ² / Vs), P-channel type TFT
In as large as 100 ~300cm ² / Vs (typically 150 ~200cm ² / Vs). (3) The threshold voltage (V
_th ) is as small as -0.5 to 1.5 V for an N-channel TFT and -1.5 to 0.5 V for a P-channel TFT.

As described above, it has been confirmed that extremely excellent switching characteristics and high-speed operation characteristics can be realized.

In forming the CGS, the annealing step at a temperature higher than the crystallization temperature (700 to 1100 ° C.) plays an important role in reducing defects in crystal grains. This will be described below.

FIG. 27A is a TEM photograph in which the crystalline silicon film at the time when the above-mentioned crystallization step is completed is magnified 250,000 times. Defects appearing on the zigzag as shown by arrows are confirmed.

Such defects are mainly stacking faults in which the stacking order of atoms on the silicon crystal lattice plane is different, but there are also cases such as dislocations. FIG. 27A is considered to be a stacking fault having a defect plane parallel to the {111} plane. This can be confirmed from the fact that the zigzag-shaped defect is bent at an angle of about 70 °.

On the other hand, as shown in FIG. 27B, the crystal silicon film used in the present invention viewed at the same magnification has almost no defects caused by stacking faults or dislocations in the crystal grains. It can be confirmed that the crystallinity is very high. This tendency is true for the entire film surface. Although it is difficult at present to reduce the number of defects, it can be reduced to a level that can be regarded as substantially zero.

That is, in the crystalline silicon film used for the liquid crystal panel of the active matrix type liquid crystal display device of the present invention, the defects in the crystal grains are reduced to almost negligible level and the crystal grain boundaries have high continuity. Cannot be a barrier to carrier movement, and thus can be regarded as a single crystal or substantially a single crystal.

As described above, both the crystalline silicon films shown in the photographs of FIGS. 27A and 27B have almost the same continuity at the crystal grain boundaries, but the number of defects in the crystal grains does not increase. There is a big difference. The crystalline silicon film shown in FIG.
The reason for exhibiting much higher electrical characteristics than the crystalline silicon film shown in FIG. 7A is largely due to the difference in the number of defects.

From the above, it can be understood that the gettering process of the catalytic element is an indispensable step in producing CGS. The present inventors have considered the following model for the phenomenon caused by this process.

First, in the state shown in FIG. 27A, a catalytic element (typically, nickel) is segregated in a defect (mainly, stacking fault) in a crystal grain. That is, it is considered that there are many Si—Ni—Si bonds.

However, when the Ni present in the defect is removed by performing the catalytic element gettering process,
-Ni bond is broken. As a result, the remaining bonds of silicon immediately form Si-Si bonds and stabilize. Thus, the defect disappears.

It is of course known that thermal annealing at a high temperature eliminates defects in the crystalline silicon film. However, recombination of silicon occurs because the bond with nickel is broken and many dangling bonds are generated. Can be presumed to be performed smoothly.

In addition, the present inventors performed a heat treatment at a temperature higher than the crystallization temperature (700 to 1100 ° C.) to fix the gap between the crystalline silicon film and the underlying layer, and to improve the adhesion to improve the defect. We are thinking of a model that will disappear.

The crystalline silicon film thus obtained (FIG. 27)
(B)) has a feature that the number of defects in crystal grains is remarkably smaller than that of a crystalline silicon film obtained by merely crystallization (FIG. 27A). Means Electron Spin Resonance (ES)
R) appears as a difference in spin density. At present, the spin density of the crystalline silicon film used in the present invention is at least 1 × 10 ¹⁸ / cm ³ or less (typically 5 × 10 ¹⁷ / cm ³ or less).

The crystalline silicon film used in the present invention having the above-described crystal structure and characteristics is called continuous grain silicon (CGS).

(Example 2)

In this embodiment, another embodiment of the D / A conversion circuit of the present invention will be described. In this embodiment, 8
A bit D / A conversion circuit will be described as an example, but the present invention is not limited to this, and a D / A conversion circuit that handles signals of 2 bits or more is realized.

In this embodiment, a D / A conversion circuit provided in a drive circuit of a liquid crystal display device having 1920 × 1080 pixels will be described as an example.

Referring to FIG. FIG. 5 is a schematic configuration diagram of the liquid crystal display device of the present embodiment. The liquid crystal display device according to the present embodiment includes a first source signal line side shift register 50.
1. Digital decoder address lines (a, b, c, d)
502, latch circuit (LAT1, 0-LAT1, 191)
9) 503, latch circuit (LAT2, 0 to LAT2, 1)
919) 504, latch pulse line 505, switching circuit 506, first D / A conversion circuit (1st-D / A,
0 to 1st-D / A, 479) 507, gradation voltage line (V
0 to V16) 508, first output lines 509 (509-1 and 509-2) of the first D / A conversion circuit, second source signal line side shift register 510, and address lines (e, f, g, h) 511, latch circuit (LAT3, 0 to LAT3, 1919) 512, latch circuit (LAT4, 0 to LAT4, 1919) 513, latch pulse line 514, switching circuit 515, second D / A conversion Circuit (2nd-D / A, 0-2nd-D /
A, 479) 516, a second output line 517 of the second D / A conversion circuit, a switching circuit 518, a gate signal line side shift register 519, a source signal line 520, a gate signal line (scanning line) 521, and a pixel. It is composed of a TFT 522 and the like.

Of the 8-bit digital signals supplied from the outside, the upper 4 bits of the digital signal are supplied to the address lines a, b, c and d, and the lower 4 bits of the digital signal are the address lines e, f and g. And h.

17 gradation voltage lines (V0 to V16) 50
8 are supplied with different voltages by dividing the voltage applied between V0 and V16 by resistance. Further, a voltage higher than V0 is applied to V16. That is, also in this embodiment, as in the first embodiment, the higher voltages are applied in the order of V16, V15,..., V1, V0.

First source signal line side shift register 50
1 is a latch circuit 503 (LAT1, 0 to LAT1, 1
919) are sequentially supplied with a latch signal, and the latch circuit 503 operates the address line 50 at the timing when the latch signal is input.
2 (a, b, c, d) to fetch a digital signal,
Holding step, and latch circuit 504 (LA
2, 0 to LAT2, 1919), a digital signal is fetched from the latch circuit 503,
The steps to be held are the same as those in the first embodiment, and will not be described here.

The latch circuit 504 (LAT2, 0 to LAT)
2, 1919), and the held 4-bit digital signal is input to the switching circuit 506. In this embodiment, the first D / A conversion circuit 501 and the second D / A conversion circuit 510 are provided for four source signal lines at a ratio of one. Therefore, it is necessary to select a latch circuit by the switching circuit 506. Actually, each latch circuit is selected for each quarter line period. The switching circuit 506
For details of the functions described in Japanese Patent Application No.
Reference is made to Example 1 of 86098.

In this embodiment, since one set of D / A conversion circuits (first D / A conversion circuit and second D / A conversion circuit) is provided for four source signal lines, In each of the four latch circuits LAT2, LAT3, LAT0, LAT3, LAT2, LAT3, LAT2, LAT3, LAT3, LAT3, LAT3, LAT3, LAT3, LAT3, LAT3, LAT3, LAT2, LAT3
06, the first D / A conversion circuit (1st
-D / A, 0) is supplied with a 4-bit digital signal.

The 4-bit digital signal is converted to the first D / A
The data is converted into a gradation voltage by the conversion circuit 507 and supplied to the second D / A conversion circuit 516.

Second source line side shift register 510
Are latch circuits 512 (LAT3, 0 to LAT3, 19).
19) are sequentially supplied with a latch signal, and the address line 511 (e, f, g, h) is input at the timing when the latch signal is input.
And latching the digital signal from the latch circuit 513 (LAT4, 0 to LAT4, 19).
The step of inputting the latch signal to 19), taking in the digital signal from the latch circuit 512, and holding the digital signal follows the first embodiment, and thus the description thereof is omitted here. Also in this embodiment, the timing at which the first source signal line side shift register sends a latch signal to the latch circuit 503 (LAT1, 0 to LAT1, 1919) and the timing at which the second source signal line side shift register sends the latch signal Circuit 512 (LAT3, 0
To LAT3, 1919).

The latch circuit (LAT4, 0 to LAT4, 1)
919), and the retained 4-bit digital signal is input to the switching circuit 515. Here, the selection of the latch circuit by the switching circuit 506 is required. Again, the latch circuit is selected for each quarter line period. Thus, the second D / A
The conversion circuit 516 sequentially receives a 4-bit digital signal from the latch circuit.

The second D / A conversion circuit 516 supplies a gradation voltage corresponding to the input digital signal to the output line 517.

Here, the first and second D / D of this embodiment are
The A conversion circuit will be described. Please refer to FIG. FIG.
FIG. 3 is a schematic diagram of a first D / A conversion circuit 507 and a second D / A conversion circuit 516. First, referring to FIG.
D / A conversion circuit 507 and second D / A conversion circuit 5
Operation 16 will be described.

The first D / A conversion circuit 507 includes a switch circuit swA including 16 switches (swA1 to swA16) and a switch circuit swA including 16 switches (swB1 to swB16).
, And 17 gray scale voltage lines (V
0 to V16). The second D / A conversion circuit 516 includes 16 switches (swC1 to swC1).
6) and 16 resistors (R1
To R16). Here, the specific resistance of the wiring itself is not considered for convenience.

In the first D / A conversion circuit 507, a 4-bit digital signal supplied from the address lines a, b, c and d via the latch circuit selected by the switching circuit 506 controls swA and swB. I do. swA 16 switches (swA1 to swA1)
6) In the address line a, b, c via the latch circuit
Only one of the switches is closed according to the digital tone signal supplied from and d.
No two or more switches close at the same time. Also, s
Also in the 16 switches of wB (swB1 to swB16), only one of the switches is closed according to the digital signal supplied from the address lines a, b, c and d via the latch circuit. No more than one switch can be closed at the same time. In addition, swA 4
The timing at which the four switches and the four switches of swB are closed has the following relationship. That is, swA
SwB1 is closed when 1 is closed, swB2 is closed when swA2 is closed, swB3 is closed when swA3 is closed, and swB4 is closed when swA4 is closed. Regarding other switches, swAn and swBn (1 ≦ n ≦ 16; n is a natural number) are simultaneously closed. Therefore, two adjacent gradation voltage lines are always selected by swA and swB. In this way, two adjacent gradation voltage lines are selected by swA and swB, and the first output line (H)
509-1 and a first output line (L) 509-2.

In the second D / A conversion circuit 516, a 4-bit digital signal supplied from the address lines e, f, g and h via the latch circuit controls the swC.
In 16 switches of swC (swC1 to swC16), only one of the switches is closed according to the digital signal supplied from the address lines e, f, g, and h.

[0213] From the gray scale voltage supplied to the first output line (H) 509-1 and the gray scale voltage supplied to the first output line (L) 509-2, 16 resistors ( R1 to R1
6) produces 16 different gray scale voltages. swC
One of the 16 switches is closed, and the corresponding gray scale voltage is supplied to the second output line 517. The gray scale voltage supplied to the second output line 517 is supplied to the source signal line 520 through a buffer (not shown) or the like.

Therefore, in this embodiment, 16 gradation voltages can be selected by the upper 4 bits of the 8-bit digital signal, and 16 more gradation voltages can be selected from the gradation voltages selected by the lower 4 bits. A regulated voltage can be output. Therefore, 16 (upper 4 bits) × 16 (lower 4 bits) = 256 gradation voltages can be selected.

FIGS. 7 and 8 show the first D of the present embodiment.
/ A conversion circuit 507 and second D / A conversion circuit 516
An example of the circuit configuration is described.

Next, reference is made to FIG. FIG. 9 shows a part of the circuit pattern of the D / A conversion circuit of the present embodiment shown in FIGS. 7 and 8 (the circuit 507 pattern of the first D / A conversion circuit shown in FIG. 7). Is shown). In FIG. 9, reference numerals 901 to 905 are semiconductor active layers to which N-type impurities are added. 906 to 910 are semiconductor active layers to which P-type impurities are added. 911-914
Is a gate electrode wiring, and in this embodiment, 2 wt% Sc
Al (aluminum) containing (scandium) is used. Reference numerals 915 to 917 and 918 to 931 denote second wirings, and in this embodiment, Al is used.
932 and 933 are third wirings. Typically 934
The part that is blacked out as shown by
It is a portion that makes a connection (contact) between the gate electrode and the second wiring or between the second wiring and the third wiring.

It is assumed that wirings having the same pattern in the drawing are in the same wiring layer. Further, a portion shown by a broken line in the drawing indicates a lower wiring hidden by the upper wiring.

Incidentally, reference numeral 915 denotes a gradation voltage line V16,
Reference numeral 916 denotes a gradation voltage line V15, and 917 denotes a gradation voltage line V14.

In this embodiment, the third wiring is formed at the same time when the BM (black mask) layer on the active matrix substrate side of the liquid crystal display device is formed, but is formed using another wiring layer. Is also good. In that case, it is desirable to change the line width and film thickness depending on the material (Al, Ti, etc.) used. For example, when Ti is used as the material of the third wiring, since Ti has a higher resistivity than Al, it is desirable to increase the line width or increase the film thickness. Further, a laminated structure of two or more kinds of metals such as Al and Ti may be used for the third wiring.

Here, the D / A conversion circuit of this embodiment will be compared with a conventional D / A conversion circuit. As can be understood from FIG. 6, the 8-bit D / A conversion circuit of this embodiment has 17 gradation voltage lines and 48 switches. The conventional 8-bit D / A conversion circuit has 256 or 17 gray scale voltages and 256 switches. Therefore, as compared with the conventional D / A conversion circuit, the number of switches can be extremely reduced, the area can be reduced, and the whole drive circuit can be reduced in size. Further, since the size of the D / A conversion circuit can be reduced, high definition of the active matrix liquid crystal display device can be realized.

In this embodiment, the 8-bit digital signal is divided into upper 4 bits and lower 4 bits, each of which controls switching between swA, swB and swC. The division of the signal is not limited to this. For example, an 8-bit digital signal may be divided into upper 6 bits and lower 2 bits, each of which controls switching between swA, swB and swC.

In the D / A conversion circuit of this embodiment, the voltage supplied from the second output line of the second D / A conversion circuit is always stable even if the potential of the pixel TFT changes. Therefore, a stable voltage can be supplied to the pixel TFT.

The D / A conversion circuit of this embodiment can be integrally formed on an insulating substrate such as a quartz substrate or a glass substrate together with other driving circuits and other peripheral devices of the liquid crystal display device.
The D / A conversion circuit of the present invention can be created by the manufacturing method of the first embodiment. It can also be created by other manufacturing methods.

Also, four P-channel TFTs connected to each gradation voltage line of the D / A conversion circuit of this embodiment
And four N-channel TFTs are formed on the same semiconductor layer, but four independent P-channel TFTs and four independent N-channel TFTs are connected to each other via a metal wiring or the like via a contact. May be connected. However, the former case is preferable because the area of the D / A conversion circuit can be further reduced.

Here, FIG. 21 shows a photograph of the active matrix type liquid crystal display device of this embodiment. FIG. 21A shows that a good check pattern is displayed. Further, according to FIG.
It can be seen that the gradation display of No. 6 is performed.

FIGS. 22 and 23 show the D / A of the present embodiment.
FIG. 4 is an oscilloscope diagram when data is measured by operating a conversion circuit.

FIG. 22 shows voltage data of the gradation voltage lines V0 to V16 (see FIG. 6) supplied to the first D / A conversion circuit of this embodiment. One of the gradation voltage lines V0 to V16
It can be seen that seven stable voltages are supplied.

FIG. 23 shows voltage data output to the second output line of the second D / A conversion circuit of this embodiment. From the lower 4 bits, it can be seen that 16 stable voltages are output to the second output line by the digital signal. Note that the glitch seen in the output signal is due to the DE signal and does not affect the charging of the analog data signal on the source signal line.

(Example 3)

In this embodiment, an example of a specific circuit configuration of the switch circuit described in Embodiment 1 will be described. In this embodiment, a block diagram of a main part of an active matrix type liquid crystal display device which handles 4-bit digital video data is shown. Embodiment 1 can be referred to for the shift register circuit, the latch circuit, the D / A conversion circuit, and the like. The switch circuit described in the present embodiment can be used for the active matrix liquid crystal display device described in the second embodiment.

Referring to FIG. FIG. 17 is a block diagram of a main part of the active matrix type liquid crystal display device of this embodiment. What is different from Example 1 is that
The source signal line side drive circuit is used vertically above and below the pixel matrix circuit, the gate signal line side drive circuit is used right and left across the pixel matrix circuit, and the source signal line side drive circuit In some cases, a level shifter circuit is used, and a digital video data dividing circuit is provided. Further, the level shifter circuit may be used as needed, and may not necessarily be used.

The active matrix type liquid crystal display device of this embodiment comprises a source signal line side drive circuit A1701, a source signal line side drive circuit A1702, a gate signal line side drive circuit A1712, a source signal line side drive circuit A1715, and a pixel matrix circuit. 1716 and a digital video data dividing circuit 1710.

The source signal line side driving circuit A 1701 includes a shift register circuit 1702, a buffer circuit 1702, a latch circuit (1) 1704, a latch circuit (2) 1705,
A selector (switch) circuit (1) 1708, a level shifter circuit 1707, a D / A conversion circuit 1708, and a selector (switch) circuit (2) 1709 are provided. The source signal line side driving circuit A101 supplies a video signal (grayscale voltage signal) to the odd-numbered source signal lines. In this embodiment, a circuit corresponding to the switch circuit described in the first embodiment is referred to as a selector circuit. For convenience of explanation, the first and second D / A conversion circuits are collectively described as a D / A conversion circuit 1708.

For the operation up to the latch circuit (2) 1705 in the source signal line side driving circuit, Embodiment 1 or Embodiment 2 can be referred to.

The upper 2 bits of the 4-bit digital video data selected by the selector circuit (1) 1706 are supplied to the level shifter 1707 from the 4-bit digital video data. The voltage level of the digital video data is raised by the level shifter 1707, and D / D
The signal is supplied to the first D / A conversion circuit of the A conversion circuit 1708. The D / A conversion circuit 1708 converts 2-bit digital video data into an analog signal (grayscale voltage),
To the D / A conversion circuit. The second D / A conversion circuit further selects a gray scale voltage from the gray scale voltage supplied from the first D / A conversion circuit based on the lower two bits of the digital video data of the four bits, and selects the selector. The circuit (2) 1709 is supplied. The signal is sequentially supplied to the source signal line selected by the selector circuit (2) 1709. The analog signal supplied to the source signal line is supplied to a source region of a pixel TFT of a pixel matrix circuit connected to the source signal line. Refer to the first embodiment for this series of operations.

Reference numeral 1711 denotes a source signal line side driving circuit B, which has the same structure as the source signal line side driving circuit A 1701. The source signal line side driver circuit B1711 supplies a video signal to even-numbered source signal lines.

Reference numeral 1715 denotes a gate signal line side driving circuit B, which has the same configuration as the gate signal line side driving circuit A 1712. In this embodiment, by providing the gate signal line side drive circuits at both ends of the pixel matrix circuit 1716 and operating both the gate signal line side drive circuits, display defects can be caused even when one of them does not operate. There is no.

Reference numeral 1710 denotes a digital video data dividing circuit. The digital video data dividing circuit 1710 reduces the frequency of digital video data input from the outside by 1 /
It is a circuit for dropping it to m. By dividing the digital video data, the frequency of the signal required for the operation of the driving circuit can be reduced to 1 / m. The integral formation of the digital video data dividing circuit on the same substrate as the pixel matrix circuit and other driving circuits is disclosed in Japanese Patent Application No. 9-356238 filed by the present applicant. The operation of the digital video data division circuit is described in detail in the patent application, and should be referred to for understanding the operation of the digital video data division circuit of the present embodiment.

Here, the selector circuit (1) 1 of this embodiment
The configuration and operation of the 706 and the selector circuit (2) 1709 will be described. The basic concept of the selector circuit is
This is the same as the switch circuit described in the first embodiment. In this embodiment, one selector circuit (1) and one selector circuit (2) are used for every four source signal lines. Therefore, 240 selector circuits (1) and 240 selector circuits (2) are used for the source signal line side driving circuit (A), and 240 source circuits are used for the source signal line side driving circuit (B). Selector circuits (1) and 24
Zero selector circuits (2) are used.

Referring to FIG. FIG. 18 shows only the leftmost selector circuit (1) of the source signal line side drive circuit (A) for convenience of explanation. 240 selector circuits are used in the actual source signal line side drive circuit.

One of the selector circuits (1) of the present embodiment is as follows.
As shown in FIG. 18, it has eight 3-input NAND circuits, two 4-input NAND circuits, and two inverters. A signal from the latch circuit (2) 1505 is input to the selector circuit (1) 1506 of this embodiment,
Signal lines L0, 0, L from the latch circuit (2) 1505
0, 1, L1, 0, L1, 1,. . . , L1919,
0, L1919, 1 among the signal lines L0, 0, L0,
1, L1, 0, L1, 1, L2, 0, L2, 1, L3,
0, L3, 1 are connected to the selector circuit (1) shown in FIG. The description “La, b” indicates the b of the digital video data supplied to the a-th source signal line from the left.
This means that the bit-th signal is supplied. Further, a timing signal is input to the selector circuit (1) from the signal lines SS1 and SS2. The signal from the selector circuit (1) is input to the level shifter 1507, and then the signal
/ A conversion circuit 1508.

Here, reference is made to FIG. In FIG.
The selector circuit (2) is shown. FIG. 19 shows the leftmost selector circuit (2) for convenience of explanation. 240 selector circuits are used in the actual source signal line side drive circuit.

The selector circuit (2) of this embodiment is similar to that of FIG.
As shown in FIG. 1, the analog switch has four analog switches each having three P-channel TFTs and three N-channel TFTs, and three inverters. An analog video signal (grayscale voltage) converted into an analog signal by the D / A conversion circuit 1708 is input to the selector circuit (2).

FIG. 20 shows the selector circuit (1) 1706
Input 2-bit digital video data and selector circuit (1) 1706 and selector circuit (1) 1
A timing chart of the timing signal input to the input terminal 709 is shown. LS is a latch signal which is supplied to the latch circuit (2) at the start of one line period (horizontal scanning period). Bit-0 and bit-1 indicate the 0th and 1st bit data of the digital image signal output from the latch circuit (2), respectively. Here, digital signals A1 and A0 are supplied to the signal lines L0, 1 and L0, 0 from the latch circuit (2) connected to the selector circuit (1) shown in FIG. Digital signals B1 and B0 are supplied to the signal lines L1, 1 and L1, 0, respectively. Digital signals C1 and C0 are supplied to the signal lines L2, 1 and L2, 0, respectively. 1 and L3,0 are D
It is assumed that digital signals 1 and D0 are supplied.

In the selector circuit (1), bi is set based on the timing signals supplied to SS1 and SS2.
The signals output at t-1 and bit-0 are selected. That is, during the first (1/4) line period, the bit
A1 is output to -1 and A0 is output to bit-0. In the next (1/4) line period, bit-1
Output B1 and bit-0 outputs B0. In the next (1/4) line period, C1 is output to bit-1 and C0 is output to bit-0. In the last (1/4) line period, bit
D1 is output to -1 and D0 is output to bit-0. Thus, the data from the latch circuit (2) is supplied to the level shifter circuit every (1/4) line period.

The analog video signal supplied from the D / A conversion circuit is selected by the selector circuit (2) and supplied to the source signal line. Also in this case, the analog video signal is supplied to the corresponding source signal line for each (1/4) line period, but only when the voltage of the analog signal is completely determined by the decode enable signal (DE). An analog video signal is supplied to the signal line.

Although the present embodiment deals with 4-bit digital video data, digital video data of 4 bits or more can be handled.

Further, in this embodiment, since one D / A conversion circuit is provided for four source signal lines, a switch circuit is used and the number of D / A conversion circuits is reduced to one fourth of the conventional one. ,
The number of D / A conversion circuits can be other numbers.
For example, when one D / A conversion circuit is assigned to eight source signal lines, the number of D / A conversion circuits in the active matrix type liquid crystal display device of this embodiment is 240, and the area of the drive circuit can be further reduced. Is achieved. Thus, how many source signal lines are assigned to one D / A conversion circuit is not limited to the present embodiment.

In the above embodiment, an example in which the D / A conversion circuit of the present invention shown in Embodiment 1 or 2 is typically used for a driving circuit of a liquid crystal display device has been described. In this case, as a display method used in the liquid crystal display device, a TN mode using a nematic liquid crystal, a mode using electric field control birefringence,
It can also be used for a mixed layer of liquid crystal and polymer, so-called polymer dispersion mode. In the above embodiment, the case where the D / A conversion circuit of the present invention is used for the driving circuit of the transmission type active matrix type liquid crystal display device has been described. It can also be used for a driving circuit of a matrix type liquid crystal display device.

Further, the driving circuit of the digital driving system having the D / A conversion circuit of the present invention typically shown in Embodiment 1 or 2 performs the line-sequential scanning of the pixel TFT as described above. The number of pixels will be ATV (Advanced
d TV). Therefore, when used in an active matrix type liquid crystal display device using a thresholdless antiferroelectric liquid crystal having a fast response speed, the effect is further exhibited.

Also, the D / A conversion circuit of the present invention typically shown in Embodiment 1 or 2 can be replaced with a display device having any other display medium whose optical characteristics can be modulated in response to an applied voltage. May be used for the driving circuit of FIG. For example, it may be used for a driving circuit of a display device using an electroluminescence element or the like.

Also, the D / A conversion circuit of the present invention typically shown in the first or second embodiment can be used for a driving circuit of a semiconductor device such as an image sensor. In this case, the present invention can also be applied to an image sensor in which a light receiving unit of the image sensor and an image display unit that displays an image converted into an electric signal by the light receiving unit are integrally formed. Further, the image sensor can be applied to either a line sensor or an area sensor.

(Embodiment 4) In this embodiment, various electronic devices using the present invention will be described. Note that the electronic device described in this embodiment is defined as a product equipped with the D / A conversion circuit of the present invention.

Examples of such electronic devices include a video camera, a still camera, a projector, a projection TV, a head-mounted display, a car navigation, a personal computer (including a notebook type), a portable information terminal (a mobile computer, a mobile phone, and the like). Is mentioned. One example of them is shown in FIG. The display device using the D / A conversion circuit of the present invention of the above-described first to third embodiments can be used for these electronic devices.

FIG. 28 (A) shows a mobile phone,
01, audio output unit 2002, audio input unit 2003, display device 2004, operation switch 2005, antenna 200
6. The D / A conversion circuit of the present invention can be applied to the audio output unit 2002, the audio input unit 2003, the display device 2004, and the like.

FIG. 28B shows a video camera, which includes a main body 2101, a display device 2102, an audio input unit 2103, operation switches 2104, a battery 2105, and an image receiving unit 21.
06. The D / A conversion circuit of the present invention can be applied to the display device 2102, the audio input unit 2103, and the image receiving unit 2106.

FIG. 28C shows a mobile computer (mobile computer), which includes a main body 2201, a camera section 2202, an image receiving section 2203, and operation switches 220.
4. It comprises a display device 2205. The D / A conversion circuit of the present invention can be applied to the image receiving unit 2203, the display device 2205, and the like.

FIG. 28D shows a head mounted display, which comprises a main body 2301, a display device 2302, and a band 2303. The D / A conversion circuit of the present invention can be applied to the display device 2302.

FIG. 28E shows a rear type projector, in which a main body 2401, a light source 2402, a display device 2403,
Polarizing beam splitter 2404, reflector 240
5, 2406 and a screen 2407. The D / A conversion circuit of the present invention can be applied to the display device 2403.

FIG. 28F shows a CFC and a mold projector, which are a main body 2501, a light source 2502, and a display device 250.
3. It comprises an optical system 2504 and a screen 2505. The D / A conversion circuit of the present invention can be applied to the display device 2503.

As described above, the application range of the D / A conversion circuit of the present invention is extremely wide, and it can be applied to electronic devices in all fields. In addition, it can also be used for electric bulletin boards, displays for advertising, and the like.

[0262]

【The invention's effect】

According to the present invention, D / A with few switches
A conversion circuit can be realized. Further, as the number of bits of the digital signal increases, the number of switches can be extremely reduced as compared with the related art. Therefore, even in a large-screen, high-definition semiconductor display device, even a D / A conversion circuit that handles a digital signal with a large bit number can be realized with a small area.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an active matrix liquid crystal display device including a D / A conversion circuit of the present invention.

FIG. 2 is a circuit diagram of a latch circuit.

FIG. 3 is a configuration diagram of a D / A conversion circuit of the present invention.

FIG. 4 is a circuit example of a D / A conversion circuit of the present invention.

FIG. 5 is a configuration diagram of an active matrix type liquid crystal display device including the D / A conversion circuit of the present invention.

FIG. 6 is a configuration diagram of a D / A conversion circuit of the present invention.

FIG. 7 is a circuit example of a D / A conversion circuit of the present invention.

FIG. 8 is a circuit example of a D / A conversion circuit of the present invention.

FIG. 9 is a circuit pattern diagram of the D / A conversion circuit of the present invention.

FIG. 10 is a diagram illustrating a method for manufacturing a liquid crystal display device including the D / A conversion circuit of the present invention.

FIG. 11 is a diagram illustrating a method for manufacturing a liquid crystal display device including the D / A conversion circuit of the present invention.

FIG. 12 is a diagram illustrating a method for manufacturing a liquid crystal display device including the D / A conversion circuit of the present invention.

FIG. 13 is an embodiment of a liquid crystal display device provided with the D / A conversion circuit of the present invention.

FIG. 14 is a configuration diagram of a conventional digital drive type liquid crystal display device.

FIG. 15 shows a D / A conversion circuit used in a conventional digital drive type liquid crystal display device.

FIG. 16 shows a D / A conversion circuit used in a conventional digital drive type liquid crystal display device.

FIG. 17 is a block diagram of a semiconductor display device according to some embodiments of the present invention.

FIG. 18 is a circuit configuration diagram of a selector circuit (switch circuit) according to an embodiment of the present invention.

FIG. 19 is a circuit configuration diagram of a selector circuit (switch circuit) according to an embodiment of the present invention.

FIG. 20 is a timing chart of a selector circuit according to an embodiment of the present invention.

FIG. 21 is a photograph of an active matrix liquid crystal display device according to an embodiment of the present invention.

FIG. 22 is an oscilloscope diagram of an output signal of a D / A conversion circuit according to an embodiment of the present invention.

FIG. 23 is an oscilloscope diagram of an output signal of a D / A conversion circuit according to an embodiment of the present invention.

FIG. 24 is a TEM photograph of CGS.

FIG. 25 is a TEM photograph of high-temperature polysilicon.

FIG. 26 is a photograph showing electron diffraction patterns of CGS and high-temperature polysilicon.

FIG. 27 is a TEM photograph of CGS and high-temperature polysilicon.

FIG. 28 is a diagram of various electronic devices using the present invention.

FIG. 29 is a schematic configuration diagram of an active matrix liquid crystal display device including the D / A conversion circuit of the present invention.

[Explanation of symbols]

 106 first D / A conversion circuit 107 gradation voltage line 108-1 first output line (H) 108-2 first output line (L) 114 second D / A conversion circuit 115 second output line

Claims (10)

[Claims] 1. A D / A conversion circuit for supplying a gradation voltage corresponding to an input n-bit (n is a natural number of 2 or more) digital signal to an output line, wherein the n-bit digital signal is It is divided into upper x bits and lower y bits (x + y = n; both x and y are natural numbers), and the upper x bits of the n-bit digital signal are adjacent to (2 ^x +1) gray scale voltage lines Two gray scale voltage lines are selected, and 2 ^y gray scale voltages are generated from the selected gray scale voltages of the two adjacent gray scale voltage lines, and the lower y of the n-bit digital signal is generated. By bit
A D / A conversion circuit, wherein a corresponding gray scale voltage among the 2 ^y gray scale voltages is supplied to an output line. 2. The D / A converter according to claim 1, wherein the D / A conversion circuit is formed on an insulating substrate using a thin film transistor.
/ A conversion circuit. 3. A D / A conversion circuit for supplying a gradation voltage corresponding to an input n-bit (n is a natural number of 2 or more) digital signal to an output line, wherein the n-bit digital signal is Split into upper x bits and lower y bits (x + y = n; x and y are both natural numbers),
According to the upper x bits of the n-bit digital signal, among the (2 ^x +1) gradation voltage lines, the first to (2 ^x +
The z-th and (z + 1) th gray-scale voltage lines to which a higher voltage is supplied toward the gray-scale voltage line of 1) are selected (1 ≦ z ≦ 2 ^x ; z is a natural number). From the gray scale voltages of the z-th and (z + 1) -th gray scale voltage lines, 2 ^y types of gray scale voltages are generated, and by the lower y bits of the n-bit digital signal,
A D / A conversion circuit, wherein a corresponding gray scale voltage among the 2 ^y gray scale voltages is supplied to an output line. 4. The D / A converter according to claim 3, wherein the D / A conversion circuit is formed on an insulating substrate using a thin film transistor.
/ A conversion circuit. 5. A plurality of TFTs arranged in a matrix
And a source signal line side drive circuit and a gate signal line side drive circuit for driving the plurality of TFTs, wherein the source signal line side drive circuit comprises n bits (n: A D / A conversion circuit for supplying a gray scale voltage corresponding to a digital signal of 2 or more natural numbers to an output line, and dividing the n-bit digital signal into upper x bits and lower y bits ( x + y = n; x and y are natural numbers), and two adjacent gray scale voltage lines are selected from (2 ^x +1) gray scale voltage lines by the upper x bits of the n-bit digital signal. 2 ^y types of gray scale voltages are generated from the gray scale voltages of the two adjacent gray scale voltage lines, and the lower y bits of the n bit digital signal
A semiconductor device, wherein a corresponding gray scale voltage among the 2 ^y gray scale voltages is supplied to an output line. 6. A plurality of TFTs arranged in a matrix
And a source signal line side drive circuit and a gate signal line side drive circuit for driving the plurality of TFTs, wherein the source signal line side drive circuit has n bits (n: A semiconductor device having a drive circuit including a D / A conversion circuit for supplying a gray scale voltage corresponding to a digital signal of 2 or more natural numbers to an output line, wherein the n-bit digital signal is defined as upper x bits Divided into lower y bits (x + y = n; x and y are both natural numbers),
Wherein the upper x bits of the n bit digital signals (2 ^x +1) of the gradation voltage lines, the first to (2 ^x +
The z-th and (z + 1) th gray-scale voltage lines to which a higher voltage is supplied toward the gray-scale voltage line of 1) are selected (1 ≦ z ≦ 2 ^x ; z is a natural number). From the grayscale voltages of the zth and (z + 1) th grayscale voltage lines, 2 ^y types of grayscale voltages are generated, and by the lower y bits of the n-bit digital signal,
A semiconductor device, wherein a corresponding gray scale voltage among the 2 ^y gray scale voltages is supplied to an output line. 7. A semiconductor device comprising: a plurality of TFTs; and a source signal line side drive circuit and a gate signal line side drive circuit for driving the plurality of TFTs, wherein the source signal line side drive circuit comprises: A semiconductor device having a drive circuit including a D / A conversion circuit for supplying a grayscale voltage corresponding to an input n-bit (n is a natural number of 2 or more) digital signal to an output line, wherein the n-bit Is divided into upper x bits and lower y bits (x + y = n; x and y are both natural numbers),
According to the upper x bits of the n-bit digital signal, among the (2 ^x +1) gradation voltage lines, the first to (2 ^x +
The z-th and (z + 1) th gray-scale voltage lines to which a higher voltage is supplied toward the gray-scale voltage line of 1) are selected (1 ≦ z ≦ 2 ^x ; z is a natural number). From the gray scale voltages of the z-th and (z + 1) -th gray scale voltage lines, 2 ^y types of gray scale voltages are generated, and by the lower y bits of the n-bit digital signal,
A semiconductor device, wherein a corresponding gray scale voltage among the 2 ^y gray scale voltages is supplied to an output line. 8. The drive circuit according to claim 5, wherein the plurality of TFTs, the source signal line side drive circuit, and the gate signal line side drive circuit are integrally formed on an insulating substrate using a thin film transistor. A semiconductor device according to one of the above. 9. The semiconductor device according to claim 8, wherein the BM layer of the semiconductor device is used as a third wiring of the source signal line side drive circuit or the gate signal line side drive circuit. 10. The semiconductor device according to claim 9, wherein an Al film or a stacked film of Al and Ti is used for the BM layer of the semiconductor device.