JP2000035830A - Clock adjusting circuit for synchronous memory, and clock adjusting method for synchronous memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately read and write data from/to a synchronous memory and to accurately read and write the data even in a synchronous memory shared by two or more processors especially. SOLUTION: Clock delay selection circuits 9 delay clocks 14 which are outputted by processors 1 and 2 to a synchronous memory 4, and then the data is read and write to/from the memory 4. The circuit 9 is controlled by a host CPU 3 so as to give optimum delay quantity for data reading.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock adjusting circuit for a synchronous memory and a clock adjusting method for a synchronous memory, and more particularly to a synchronous adjusting circuit suitable for application when two or more processors share the synchronous memory. The present invention relates to a clock adjusting circuit for a synchronous memory and a clock adjusting method for a synchronous memory.

[0002]

2. Description of the Related Art At present, with the increase in demand for semiconductor integrated circuits, it is desired to improve the performance thereof. The performance of this semiconductor integrated circuit greatly depends on the accuracy of a clock signal input to the semiconductor integrated circuit, for example, in terms of operation speed and the like.

For this reason, various techniques for adjusting a clock signal in a semiconductor integrated circuit have been conventionally developed.

Here, as a first example of a conventional clock adjustment technique in a semiconductor integrated circuit, Japanese Patent Application Laid-Open No. 2-6189.
The “asynchronous memory” disclosed in Japanese Unexamined Patent Application Publication No. 4 (Kokai) No. 4 will be described with reference to FIG. FIG. 8 shows a block diagram of a configuration of a first example of a conventional clock adjustment technique in a semiconductor integrated circuit.

The conventional semiconductor integrated circuit shown in FIG.
Operating a memory by generating a clock signal from inside the memory block without using an external clock signal,
This is a semiconductor integrated circuit as an example of a so-called asynchronous memory.

FIG. 8 shows a first example of the clock adjustment technique in the conventional semiconductor integrated circuit. In the prior art of the first example, prior to the prior art, the time from the change of the address signal until the generation of the internal clock is generated. It is proposed to solve the problem that the skew time is fixed, and the timing of the surrounding system must be designed to be within the skew time of the asynchronous memory.

Therefore, a first example of the clock adjustment technique in the conventional semiconductor integrated circuit shown in FIG. 8 is to take in an address from an address input terminal 1000 and perform an EX-OR operation.
For a signal that changes with the output signal from 3000,
A delay circuit 700 for providing a delay amount corresponding to a delay amount corresponding to a desired clock width is provided.

The signal output from the delay circuit 700 is input to an AND circuit 1200 after being inverted by a latch circuit 900 and an inverter 800.
The output of the circuit 1200 becomes a word signal of the RAM cell array 1400. Here, the delay circuit 700 has a configuration in which a plurality of single delay circuits that provide a fixed delay amount are connected in series, and the delay amount can be arbitrarily adjusted.

Therefore, according to the first example of the clock adjustment technique in the conventional semiconductor integrated circuit shown in FIG. 8, even in the asynchronous memory, the time from the address change to the clock signal change is reduced. By making the delay circuit 700 variable by changing the delay amount,
It is no longer necessary to set the system timing within the skew time of the asynchronous memory, and the design period of the asynchronous memory according to the system timing can be shortened.

Next, as a second example of a conventional clock adjustment technique in a semiconductor integrated circuit, Japanese Patent Laid-Open Publication No.
The “delay circuit device” disclosed in Japanese Unexamined Patent Publication No. 1 will be described with reference to FIG. FIG. 9 is a block diagram showing a configuration of a second example of a conventional clock adjustment technique in a semiconductor integrated circuit.

A second example of the clock adjustment technique in the conventional semiconductor integrated circuit shown in FIG. 9 is to generate an internal clock having no phase difference with respect to an external clock over a small cycle, a wide frequency range, and a power supply voltage range. Technology that allows you to

A clock signal received from outside by a semiconductor integrated circuit is accompanied by a predetermined delay in the amplification process or the like. However, in the prior art shown in FIG. 9, the delay is applied to a phase locked loop (Phase Locked Loop). -Locked Loop,
Hereinafter, it is described as PLL. ) To correct it.

However, when phase synchronization is achieved by using a PLL, there has been a problem that this phase synchronization takes a long time. For example, the clock in the conventional semiconductor integrated circuit shown in FIG. The second example of the adjustment technique aims at generating a clock signal without delay with respect to an external clock signal without using a PLL.

For this purpose, in the second example of the clock adjustment technique in the conventional semiconductor integrated circuit, as shown in FIG. 9, a delay circuit array 10111 capable of extracting an output from an arbitrary position on a signal transmission path, A delay circuit array 10211 capable of receiving an input from an arbitrary position in a signal transmission path
And a control circuit 10311 including a signal input / output control terminal 10911. The delay circuit array 10111 and the delay circuit array 10211 are arranged side by side so that the signal transmission paths are opposite to each other, and the output of the delay circuit array 10111 and the input of the delay circuit array 10211 are controlled by the control circuit 1031.
1 are sequentially connected from the side near the input of the delay circuit array 10111 and the side near the output of the delay circuit array 10211, and the first signal is input to the delay circuit array 10111, and after an arbitrary time, A second signal is output to the control circuit 10311, and the first signal on the delay circuit row 10111 is transferred to the delay circuit row 10211.

Therefore, in the second example of the clock adjustment technique in the conventional semiconductor integrated circuit shown in FIG.
The phase difference between the external clock and the internal clock is made shorter than the delay of the internal amplification, and the internal clock having the desired phase
It is stated that effects such as being able to be obtained periodically can be exhibited.

Next, as a third example of a conventional clock adjustment technique in a semiconductor integrated circuit, Japanese Patent Laid-Open No. 8-31694 is disclosed.
The "phase adjustment circuit" disclosed in Japanese Patent Publication No. 4 (JP-A) No. 4 will be described with reference to FIG. FIG. 10 shows a block diagram of a configuration of a third example of a conventional clock adjustment technique in a semiconductor integrated circuit.

The third example of the clock adjustment technique in the conventional semiconductor integrated circuit shown in FIG. 10 relates to a technique for appropriately delaying the phase of an input data signal and outputting a data signal synchronized with the clock signal.

In the prior art of the third prior art,
The output line must be changed every time the amount of phase delay is changed, resulting in problems such as poor operability and a problem that the circuit scale increases due to the need for a dedicated circuit for phase delay. Was.

Therefore, in the third example of the clock adjustment technique in the conventional semiconductor integrated circuit shown in FIG. 10, a phase adjustment circuit having a simple configuration capable of controlling the phase delay of input data by external control data is provided. It is intended to be.

Therefore, in the third example of the prior art, as shown in FIG.
Self-load counter 10022 for counting the delay time, and a latch circuit 12 for inputting delay amount control data 22022 and delay amount control data latch signal 21022 from outside.
022, the delay amount control data output from the latch circuit 12022, and the data output from the synchronous self-load counter 10022, and when the delay amount matches the count value, the comparison result signal 25022 is output. FIF
The input data 26022 is delayed based on the comparator 11022 output to the O memory 13022 and the comparison result signal 25022 from the comparator
022 as the output.

As described above, in the third example of the clock adjustment technique in the conventional semiconductor integrated circuit shown in FIG. 10, an arbitrary delay amount x is externally set, and a synchronous operation is performed on the delay amount x and the clock. A comparison result signal 25022 of an arbitrary cycle is generated by comparing the count data of the synchronous self-load counter 10022 to be executed, and a delay amount of input / output data is controlled using the comparison result 25022 and the FIFO memory 13022. With this configuration, it is not necessary to change the output line every time the phase delay amount is changed as in a conventional circuit that requires a multi-stage shift register, or to change the circuit scale in accordance with the phase delay amount.

Next, as a fourth example of a conventional clock adjustment technique in a semiconductor integrated circuit, Japanese Patent Application Laid-Open No. 9-16511
The "conversion system between CPU bus and local bus" disclosed in Japanese Patent Application Laid-Open Publication No. H10-115,878 will be described with reference to FIG. FIG. 11 is a block diagram showing the configuration of a fourth example of the conventional clock adjustment technique in a semiconductor integrated circuit.

As shown in FIG. 11, in the fourth example of the clock adjustment technique in the conventional semiconductor integrated circuit, a high-speed operation CPU 10033, a CPU control gate array 10533, and a VL bus 13033 are provided as main members. CPU control gate array 1
By providing a synchronization circuit and a delay adjustment circuit (both not shown) in 0533, the bus cycle of the high-speed operation CPU 10033 and the VL bus 1303 can be performed without increasing the number of pins of the CPU control gate array 10533.
It is stated that synchronization between different buses can be achieved, for example, between three buses.

Next, as a fifth example of the conventional clock adjustment technique in a semiconductor integrated circuit, Japanese Patent Application Laid-Open No. 9-30448 is disclosed.
The "semiconductor memory device" disclosed in Japanese Patent Publication No. 4 (JP-A) No. 4 will be described with reference to FIG. FIG. 12 is a block diagram showing a configuration of a fifth example of a conventional clock adjustment technique in a semiconductor integrated circuit.

A fifth example of the conventional clock adjustment technique in a semiconductor integrated circuit shown in FIG. 12 is a method of controlling a delay value caused by a change in a process at the time of manufacturing a semiconductor integrated circuit.
This is a technique for automatically setting an optimum value at the time of setting an initial mode register.

For this purpose, as shown in FIG. 12, the fifth example of the prior art comprises a delay control block 11055 having a reference delay 11155 and a delay block 10055 having a main delay 10255 as main members. Is done.

By optimizing the internal delay value by comparing the reference delay value with the cycle of the external clock when the mode register is set, the process fluctuates at the time of manufacturing, resulting in a change in the delay value of the delay block 10055. Even in this case, the delay value of the delay block 10055 can be automatically optimized based on the cycle of the external clock when the mode register is set, so that the yield and the characteristics are always constant without depending on the process fluctuation, so that the stability is stable. Production is possible.

As described above, various techniques for adjusting a clock signal in a semiconductor integrated circuit have been developed.

On the other hand, in a semiconductor integrated circuit, a shared memory type semiconductor integrated circuit in which one memory is shared by two or more processors has been developed.

This shared memory type semiconductor integrated circuit is particularly effective for reducing the cost of the semiconductor integrated circuit.

Here, a conventional shared memory type semiconductor integrated circuit will be described with reference to FIG. FIG.
FIG. 1 is a block diagram showing an example of a configuration of a conventional memory sharing type semiconductor integrated circuit.

As shown in FIG. 13, this conventional memory-sharing type semiconductor integrated circuit comprises two processors such as a processor 11 and a processor 12, a synchronous memory 4 shared by these processors, a host CPU 3, The address 13, the clock 14, and the control signal 15 input to the synchronous memory 4 are output as signals from the processor 11.
It is composed of selectors 83, 84, and 85 for selecting whether the output is from the processor 12.

Here, as shown in FIG. 13, the processor 11 and the processor 12 are connected via the data bus 5 and the host bus 6, respectively. Also,
The data bus 5 is also connected to the synchronous memory 4.
Further, a host CPU 3 for controlling the operation of each processor is connected to the processors 11 and 12 via the host bus 6.

Next, the operation of the conventional memory sharing type semiconductor integrated circuit shown in FIG. 13 will be described. When reading / writing data from / to the synchronous memory 4, the processor 11 and the processor 12 do not operate at the same time. Therefore, when the processor 11 operates, the host CPU 3 stores the address, clock, The selectors 83, 84,
And 85, and when the processor 12 is operating, the synchronous memory 4 stores the address, clock,
And selectors 83, 84,
And 85.

As described above, by controlling the selector, in the semiconductor integrated circuit as shown in FIG. 13, one synchronous memory 4 can be shared by two processors, and the cost is reduced. I can do it.

[0036]

However, FIG.
In the example of the conventional memory-sharing type semiconductor integrated circuit as shown in (1), there is a problem that data transfer processing between the processor 11 or the processor 12 and the synchronous memory 4 cannot be performed accurately.

The reason why this problem occurs will be described below. Generally, the clocks output from the processors 11 and 12 are output with a fixed delay with respect to the internal clocks of the processors 11 and 12, and the delay value of this clock is Place synchronous memory in the immediate vicinity of the processor
The delay amount is suitable for directly connecting a clock.

However, when the synchronous memory 4 is shared by two or more processors as shown in FIG.
Since the clock 14 is usually as fast as 100 MHz or more, the phase difference between the internal operation clock and the clock 14 input to the synchronous memory 4 is increased by the increase in the delay due to the increase in the length of the wiring on the selector circuit and the substrate. It is difficult to satisfy the characteristics of

Here, the operation timing of the shared memory type semiconductor integrated circuit shown in FIG. 13 will be described with reference to FIGS. 7 and 14. 7 and 14 show timing charts of the operation of the conventional memory-shared semiconductor integrated circuit shown in FIG. However, the timing chart shown in FIG. 7 is the timing chart of the operation of the conventional memory sharing type semiconductor integrated circuit shown in FIG. 13, and in the clock adjustment circuit of the synchronous memory according to the present invention, It is also a timing chart when data is read from the memory.

The timing chart shown in FIG. 7 is an example of a timing chart when the data output from the synchronous memory 4 can be accurately read by the processor. As shown in FIG. In order to read the data on the data bus 5, an internal clock whose phase is advanced by a predetermined range from the clock 14 to satisfy the setup time Ts and the hold time Th is required. If these characteristics cannot be satisfied, the output of the synchronous memory 4 cannot be normally received by the processor 11 or the processor 12.

For example, as shown in the timing chart of FIG. 14 when the data output from the synchronous memory cannot be accurately read by the processor, FIG.
14A, the phase of the internal clock is too early, so that the data on the data bus 5 does not satisfy the hold time Th. In the case shown in FIG. Is too slow, the data on the data bus 5 does not satisfy the setup time Ts and the hold time Th, and the processor cannot read the data accurately.

As described above, in the conventional memory-integrated semiconductor integrated circuit shown in FIG. 13, since the delay of the clock output from each processor is fixed, for example, the characteristics of the processor and the load capacity in the middle thereof When the delay amount of the clock 14 changes due to the above, the processor 11,
Alternatively, there is a problem that the data transfer process between the processor 12 and the synchronous memory 4 cannot be performed accurately.

Here, the first example of the clock adjustment technique in the conventional semiconductor integrated circuit shown in FIG. 8 described above relates to a technique capable of making the time until a clock is variable. However, the generated clock is an internal clock, and therefore, is a technology applicable only to an asynchronous memory, and is not a technology applicable to a semiconductor integrated circuit of a synchronous memory sharing type.

In the second example of the conventional clock adjustment technique in the conventional semiconductor integrated circuit shown in FIG. 9, the internal clock signal having no phase difference from the external clock signal is processed at high speed without using the PLL. Although it is a technique that enables generation, it does not control the delay of a clock input to a synchronous memory.

In the third example of the clock adjusting technique in the conventional semiconductor integrated circuit shown in FIG. 10 described above, the phase of input data can be easily controlled by external control data. There are, for example, FI
It only controls the phase of data input to and output from the FO, and does not control the phase of a clock signal for controlling the operation of the FIFO.

In the above-described fourth example of the clock adjustment technique in the conventional semiconductor integrated circuit shown in FIG. 11, a semiconductor integrated circuit capable of switching the signal timing between a high-speed CPU and a local bus. Is a technique for connecting between different buses such as a CPU bus and a VL bus, and is not applied to a clock output to a synchronous memory.

Further, in the above-described fifth example of the clock adjusting technique in the conventional semiconductor integrated circuit shown in FIG. The purpose is to optimize by comparing the cycles, but not to optimize the clock output to the synchronous memory.

The present invention has been made in view of the above circumstances,
A clock adjustment circuit for a synchronous memory that can accurately execute reading and writing to the synchronous memory, and particularly can execute reading and writing accurately even in a synchronous memory shared by two or more processors. And a clock adjusting method for a synchronous memory.

[0049]

According to the first aspect of the present invention,
A first processor that reads and writes data from and to a synchronous memory; and a second processor that reads and writes data to and from the synchronous memory. A first clock delay selection circuit that delays and outputs a clock signal output to the synchronous memory, and wherein the second processor delays and outputs a clock signal output to the synchronous memory. It has two clock delay selection circuits.

According to a second aspect of the present invention, in the first aspect, at least one or more of the first clock delay selection circuit and the second clock delay selection circuit are connected in series. A delay element that applies a predetermined delay to the input clock signal and outputs the clock signal, and outputs the clock signal output from the delay element, the first clock delay selection circuit, or the second clock delay selection circuit. A selector is provided on each output side of the delay element for selecting whether to output a clock signal input to a circuit, and a control register for controlling an operation of the selector.

According to a third aspect of the present invention, in the first or second aspect of the present invention, a host CPU for controlling an operation of the first clock delay selection circuit and the second clock delay selection circuit is provided. It is characterized by.

According to a fourth aspect of the present invention, in the third aspect of the present invention, the number of delay elements provided in the first clock delay selecting circuit is defined as m1 where m1 is an arbitrary positive integer of 1 or more. In the case where the number is 1, the host CPU sets k1 as an integer having a value of 0 or more and m1 or less, and based on the k1th delayed clock signal given by the delay of k1 of the delay elements, the host CPU The first processor performs writing and reading to and from the memory, and performs a k-th determination operation to determine whether the written value matches the read value. From the j-th determination operation to the m-th determination operation, an average delay amount of the delay amounts giving the coincident values is calculated, and the delay amount closest to the average delay amount is calculated as the first delay amount. Clock delay selection circuit If the delay is assumed, the clock signal output from the first clock delay selection circuit is used as the clock signal delayed and output from the first clock delay selection circuit; When the number of delay elements provided in the circuit is m2, where m2 is an arbitrary positive integer of 1 or more, and when the number of delay elements is m2, k2 is an integer having a value of 0 to m2.
Causes the second processor to perform writing and reading to and from the synchronous memory based on a k2th delayed clock signal to which a delay of k2 of the delay elements has been given, and writes the written value and The k-th determination operation for determining whether or not the read value is consistent is sequentially performed from the 0-th determination operation to the m-th determination operation to provide the matched value. The average delay amount is calculated, and when the delay amount closest to the average delay amount is determined to be the delay amount in the second clock delay selection circuit, the output from the second clock delay selection circuit is determined. The clock signal to be output is a clock signal delayed and output from the second clock delay selection circuit.

According to a fifth aspect of the present invention, in the first aspect of the present invention, the first address, the first address, the output from the first processor to the synchronous memory,
A first clock signal, a first control signal, and the second
Output from the processor to the synchronous memory.
And selecting means for selecting any one of the address, the second clock signal, and the second control signal and outputting the selected signal to the synchronous memory.

According to a sixth aspect of the present invention, in the fifth aspect of the present invention, the selecting means comprises a selector.

The invention according to claim 7 is the invention according to claim 6, wherein the selector outputs the first address and the second processor which are output from the first processor to the synchronous memory. A first selector, to which the second address is input, which is output from the first processor to the synchronous memory; a first clock signal, which is output from the first processor to the synchronous memory; A second selector to which the second clock signal output from the second processor to the synchronous memory is input;
A third selector to which the first control signal output from the processor to the synchronous memory and the second control signal output to the synchronous memory from the second processor are input; The first address, the first clock signal, and the first control signal output from the first processor to the synchronous memory are output from the first processor to the synchronous memory. A selector of 1,
A second selector that controls the second selector and the third selector to select a signal output from the first processor, and that is output from the second processor to the synchronous memory. When outputting an address, a second clock signal, and a second control signal to the synchronous memory, the first selector, the second selector, and the third selector are connected to the second processor. And selecting a signal output to the synchronous memory by controlling so as to select a signal output from the synchronous memory.

According to an eighth aspect of the present invention, in the fifth aspect of the present invention, the selecting means comprises a three-state buffer.

According to a ninth aspect of the present invention, in the first aspect of the present invention, the three-state buffer is output from the first processor to the synchronous memory.
A first three-state buffer to which the first clock signal is inputted, a second three-state buffer to which the first clock signal is inputted, which is outputted from the first processor to the synchronous memory, and the first processor And the third control signal is input to the synchronous memory.
A third state buffer output from the second processor to the synchronous memory, a fourth three state buffer to which the second address is input, and an output from the second processor to the synchronous memory. A fifth three-state buffer to which the second clock signal is input, and a sixth three-state buffer to be output from the second processor to the synchronous memory and to which the second control signal is input. , And a first address, a first address, which is output from the first processor to the synchronous memory.
When outputting the clock signal and the first control signal to the synchronous memory, the fourth three-state buffer, the fifth three-state buffer, and the sixth three-state buffer are set to high.・ In the impedance state,
When outputting a second address, a second clock signal, and a second control signal from the second processor to the synchronous memory to the synchronous memory, the first three-state buffer And setting the second three-state buffer and the third three-state buffer in a high impedance state to select a signal to be output to the synchronous memory.

According to a tenth aspect of the present invention, there is provided at least one processor for reading and writing data from and to the synchronous memory, and the processor delays a clock signal output to the synchronous memory. And a clock delay selection circuit for outputting the output.

According to an eleventh aspect of the present invention, in the invention according to the tenth aspect, the clock delay selecting circuit applies a predetermined delay to at least one or more input clock signals which are connected in series. A delay element to be output, a selector provided on each output side of the delay element, for selecting whether to output the clock signal output from the delay element or to output the input clock signal, and the selector And a control register for controlling the operation of (1).

According to a twelfth aspect of the present invention, in accordance with the tenth or eleventh aspect, a host CPU for controlling the operation of the clock delay selecting circuit is provided.

According to a thirteenth aspect of the present invention, in the invention of the twelfth aspect, when the number of the delay elements is m, where m is an arbitrary positive integer of 1 or more, k is set to 0 or more. the host CPU as an integer taking a value up to m or less.
Is written to the synchronous memory based on a k-th delayed clock signal obtained by delaying k delay elements.
And the k-th determination operation to determine whether the written value matches the read value is sequentially performed from the 0-th determination operation to the m-th To determine the average delay amount of the delay amount that gives the matching value, and assume that the delay amount closest to the average delay amount is the delay amount in the clock delay selection circuit. In this case, the clock signal output from the clock delay selection circuit is a clock signal delayed and output from the clock delay selection circuit.

According to a fourteenth aspect of the present invention, a first clock delay selecting step of delaying a clock signal output from the first processor for reading and writing data to and from the synchronous memory to the synchronous memory. And a second clock delay selecting step of delaying a clock signal output to the synchronous memory from a second processor that reads and writes data to and from the synchronous memory. .

According to a fifteenth aspect of the present invention, in the invention of the fourteenth aspect, the first clock delay selecting step and the second clock delay selecting step each include at least one or more connected in series. A delay step of delaying and outputting the input clock signal by a delay element that applies a predetermined delay to the input clock signal and outputs the delayed clock signal;
A clock signal selecting step of selecting whether to output a clock signal output from the delay step, or to output a clock signal input to the first clock delay selecting step or the second clock delay selecting step. And a clock signal selection control step of controlling the operation of the clock signal selection step by a control register.

According to a sixteenth aspect of the present invention, in the invention according to the fourteenth or fifteenth aspect, a clock for controlling an operation of the first clock delay selecting step and the second clock delay selecting step by a host CPU. It has a delay selection control step.

According to a seventeenth aspect of the present invention, in the invention of the sixteenth aspect, the number of delay elements used in the first clock delay selecting step is such that m1 is an arbitrary positive integer of 1 or more. Where k1 is an integer having a value of 0 or more and m1 or less, the host CP
U causes the first processor to perform writing and reading to and from the synchronous memory based on a k1th delayed clock signal that is delayed by k1 delay elements,
The k-th determination operation for determining whether the written value matches the read value is sequentially performed from the 0-th determination operation to the m-th determination operation. Calculating an average delay amount of the delay amounts giving the matched values, and assuming that the delay amount closest to the average delay amount is the delay amount in the first clock delay selecting step, The clock signal output from the clock delay selecting step is a clock signal delayed and output from the first clock delay selecting step, and the number of delay elements used in the second clock delay selecting step is m
If 2 is an arbitrary positive integer of 1 or more and m2, and if k2 is an integer having a value of 0 or more and m2 or less, the host CPU gives a delay of k2 of the delay elements. The second processor writes and reads data to and from the synchronous memory based on the k2th delayed clock signal and determines whether the written value matches the read value. The k-th determination operation is sequentially performed from the 0-th determination operation to the m-th determination operation to calculate an average delay amount of the delay amounts that give the coincident values. Assuming that the delay amount closest to the delay amount is the delay amount in the second clock delay selecting step, the clock signal output from the second clock delay selecting step is changed to the second clock delay selecting step. Is delayed from Characterized by a clock signal output.

The invention according to claim 18 is the invention according to any one of claims 14 to 17, wherein the first address and the first clock signal are output from the first processor to the synchronous memory. And a first control signal, and one of a second address, a second clock signal, and a second control signal output from the second processor to the synchronous memory. And outputting an output signal to the synchronous memory.

The invention of claim 19 is characterized in that, in the invention of claim 18, the output signal selecting step is a step of selecting an output signal from the processor using a selector.

According to a twentieth aspect, in the invention according to the nineteenth aspect, the selector outputs the first address and the second processor which are output from the first processor to the synchronous memory. A first selector, to which the second address is input, which is output from the first processor to the synchronous memory; a first clock signal, which is output from the first processor to the synchronous memory; A second selector, to which the second clock signal is input, which is output from the second processor to the synchronous memory, and which is output to the synchronous memory from the first processor;
The first control signal and a third selector, which is output from the second processor to the synchronous memory and receives the second control signal, is configured by the output signal selecting step. When outputting a first address, a first clock signal, and a first control signal from the first processor to the synchronous memory to the synchronous memory, the first selector, the first selector, Controlling a second selector and the third selector to select a signal output from the first processor;
Output from the processor to the synchronous memory.
When outputting the address, the second clock signal, and the second control signal to the synchronous memory, the first selector, the second selector, and the third selector,
Is controlled to select a signal output from the second processor.

According to a twenty-first aspect of the present invention, in the eighteenth aspect, the output signal selecting step is a step of selecting an output signal from a processor using a three-state buffer.

According to a twenty-second aspect of the present invention, in the twenty-first aspect, the three-state buffer is provided with the first state buffer.
A first three-state buffer, to which the first address is input, which is output from the processor to the synchronous memory, and a first clock signal, which is output to the synchronous memory from the first processor. A second three-state buffer to be input, a third three-state buffer to be output from the first processor to the synchronous memory, to which the first control signal is input, and the synchronization from the second processor. A fourth three-state buffer, to which the second address is input, which is output to an expression memory; and a second, which is output to the synchronous memory from the second processor.
A fifth three-state buffer to which the clock signal is inputted, and a sixth three-state buffer to which the second control signal is outputted, which is outputted from the second processor to the synchronous memory, In the output signal selecting step, a first address, a first clock signal, and a second clock are output from the first processor to the synchronous memory.
And outputting the first control signal to the synchronous memory, the fourth three-state buffer, the fifth three-state buffer, the sixth three-state buffer,
To a high impedance state and output a second address, a second clock signal, and a second control signal output from the second processor to the synchronous memory to the synchronous memory, The first three-state buffer, the second three-state buffer, and the third
And a high-impedance state of the three-state buffer to select an output from the processor.

According to a twenty-third aspect of the present invention, there is provided a clock delay selecting step of delaying a clock signal output from at least one processor for reading and writing data to and from the synchronous memory to the synchronous memory. It is characterized by the following.

According to a twenty-fourth aspect of the present invention, in the twenty-third aspect of the present invention, the clock delay selecting step includes a step of giving a predetermined delay to at least one or more input clock signals connected in series. A delay step of delaying a clock signal by a delay element to output, and a clock signal selecting step of selecting whether to output the clock signal output from the delay step or to output the clock signal input to the clock delay selecting step And a clock signal selection control step of controlling the operation of the clock signal selection step by a control register.

According to a twenty-fifth aspect of the present invention, in the twenty-third aspect or the twenty-fourth aspect, a host CPU has a clock delay selection control step of controlling the operation of the clock delay selection step.

The invention according to claim 26 is the invention according to claim 25, wherein the number of the delay elements used in the clock delay selecting step is m, where m is an arbitrary positive integer of 1 or more. In this case, the host CPU sets k to an integer having a value of 0 or more and m or less based on a k-th delayed clock signal provided with k delays of the delay elements and transfers the data to the synchronous memory. Writing and reading are performed by the processor, and the k-th determining operation for determining whether the written value matches the read value is sequentially performed from the 0-th determining operation to the k-th determining operation. Perform the steps up to the m-th determination operation, calculate the average delay amount of the delay amounts that give the coincident values, and determine the delay amount closest to the average delay amount in the clock delay selecting step. Place In, and having a clock signal selection step of the clock signal output is delayed a clock signal output from the clock delay selection process from the clock delay selection step.

[0075]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a clock adjusting circuit for a synchronous memory and a clock adjusting method for a synchronous memory according to the present invention will be described with reference to the drawings.

First, a first embodiment of a clock adjusting circuit for a synchronous memory according to the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of a first embodiment of a clock adjusting circuit of a synchronous memory according to the present invention. However, the description of the first embodiment of the clock adjustment circuit of the synchronous memory according to the present invention described below also serves as the description of the first embodiment of the clock adjustment method of the synchronous memory according to the present invention. It is. Further, in the members shown in FIG. 1, the same members as those shown in FIG. 13 are denoted by the same reference numerals.

As shown in FIG. 1, the first embodiment of the clock adjusting circuit of the synchronous memory according to the present invention comprises a processor 1, a processor 2, a synchronous memory 4 shared by these, And a clock delay selection circuit 9 inside each processor for selecting a clock delay for the synchronous memory 4, and a selector 83 for selecting one of an address output from the processor 1 and an address output from the processor 2 A selector 84 for selecting either the clock output from the processor 1 or the clock output from the processor 2; and a control signal output from the processor 1 or a control signal output from the processor 2. And a selector 85 for selecting one.

One of the address output from the processor 1 and the address output from the processor 2 is selected by the selector 83 and then output to the synchronous memory 4 as the address 13. Similarly, after one of the clock output from the processor 1 and the clock output from the processor 2 is selected by the selector 84, the clock 1
4, one of the control signal output to the synchronous memory 4 and output from the processor 1 or the control signal output from the processor 2
Is selected and output to the synchronous memory 4 as the control signal 15.

Here, as shown in FIG. 1, the processor 1 and the processor 2 are connected via a data bus 5 and a host bus 6, respectively. The data bus 5 is also connected to the synchronous memory 4. Also,
A host CPU 3 for controlling the operation of each processor is connected to the processors 1 and 2 via a host bus 6.

The transfer speeds of the data bus 5 and the host bus 6 are not particularly limited in the present invention, and the data bus 5 and the host bus 6 having any transfer speed can be appropriately used.

Next, the clock delay selection circuit 9 provided in the processor 1 and the processor 2 shown in FIG.
Will be described with reference to FIG. FIG. 2 shows a block diagram of the configuration of the clock delay selection circuit 9 shown in FIG. However, in the example shown in FIG. 1, the clock delay selection circuit 9 provided in the processor 1 and the clock delay selection circuit 9 provided in the processor 2 are given the same numbers as the same, As explained below,
A clock delay selection circuit 9 provided in the processor 1;
The clock delay selection circuit 9 included in the processor 2 may have a configuration independent of, for example, the number of delay elements inside the clock delay selection circuit 9.

As shown in FIG. 2, the clock delay selection circuit 9 has, for example, four serially connected delay elements 102 which delay the internal clock 101 and output it as a clock 106.

A selector 103 is provided on the output side of each delay element 102. This selector 103 selects and outputs either the internal clock 101 or the output of the delay element 102.

The selection of each selector 103 is controlled by the control register 100. In the example shown in FIG. 2, since four delay elements 102 are connected in series, if all the delay elements 102 have the same delay time, the case where 0 to 4 delay elements are selected corresponds to 5 types of delay times can be selected by the control register 100. Further, the control register 100 stores the host bus 6
The operation is controlled by the host CPU 3 via the.

However, the configuration of the clock delay selection circuit 9 shown in FIG. 2 is an example, and the clock delay selection circuit 9 included in the first embodiment of the clock adjustment circuit of the synchronous memory according to the present invention is The number of delay elements is not limited to the case shown in FIG. 2, and may be any number other than four, for example.

Further, as shown in FIG. 2, a selector is used as a member for selecting a signal output from the delay element. The selector selects the internal clock 101 and the output from the delay element. It may be replaced with two three-state buffers.

Next, the operation of the clock adjusting circuit of the synchronous memory according to the first embodiment of the present invention shown in FIG. 1 will be described with reference to FIGS. 1, 2 and 3. FIG.
FIG. 3 shows a flowchart of the operation of the first embodiment of the clock adjustment circuit of the synchronous memory according to the present invention shown in FIG.

As shown in FIG. 3, the host CPU 3
First determines whether to operate the processor 1 or the processor 2 (step S1). In this determination, when the processor 1 is operated, (Y
ES), the process proceeds to step S3. If the processor 2 is to be operated (NO), the process proceeds to step S11.

If it is determined in step S1 that the processor 1 is to be operated, in step S3, in order to make the processor 1 processable,
The host CPU 3 controls the selector 83, the selector 84, and the selector 85 so that the address, the clock, and the control signal from the processor 1 are input to the synchronous memory 4.

On the other hand, in step S1, the processor 2
Is selected to be operated, step S11 is performed.
In order to put the processor 2 into a processable state,
The host CPU 3 controls the selector 83, the selector 84, and the selector 85 so that the address, the clock, and the control signal from the processor 2 are input to the synchronous memory 4.

Next, the host CPU 3 sets the control register 100 included in the clock delay selection circuit 9 of the selected processor to be operated so that the number of selected delay elements becomes zero. The clock based on the delay time causes the selected processor to write and read the synchronous memory 4, and determines whether the same value as the written value has been read.

Then, the number of delay elements selected in the clock delay selection circuit 9 is sequentially increased from 1 to 4, and in this case, similarly, it is determined whether the writing and reading to the synchronous memory 4 have been normally performed. Is performed (step S5).

Here, as shown in FIG. 7, in order to perform writing and reading to and from the synchronous memory 4 normally,
It is necessary that data on the data bus 5 synchronized with the phase of the clock 14 satisfy the setup time Ts and the hold time Th of the internal clock of the processor (hereinafter, also referred to as a condition). Time T
The phase range of the clock 14 that satisfies s and the hold time Th has a certain width.

Therefore, when the number of delay elements selected in the clock delay selection circuit 9 sequentially changes from 0 to 4, for example, when the delay value is 0, the condition is not satisfied, and when the delay value is 1 to 3, Satisfies the condition, and when the delay value is 4, the condition may not be satisfied. of course,
The delay value that satisfies the condition is not limited to such a combination, but may be another combination.
In this case, the optimum delay value can be an average value between the delay values satisfying these conditions.

For this reason, the host CPU 3 calculates the average value of the delay values for which the above-mentioned delay times have been confirmed to be normal operation with respect to the internal clock 101 (this average value may be a non-integer number) (step S7). The delay value is set in the delay control register 100 so as to be closest to the average value (step S9). As described above, the processor selected to operate is in a processable state in a state where data can be read and written from the synchronous memory 4 normally.

Since the processor 1 and the processor 2 do not operate at the same time, there is no simultaneous access to the synchronous memory 4.

Therefore, according to the first embodiment of the clock adjusting circuit of the synchronous memory according to the present invention and the first embodiment of the clock adjusting method of the synchronous memory according to the present invention shown in FIG. Even when the synchronous memory is shared by the two processors, the delay value of the clock 14 output to the synchronous memory 4 in each processor is set to the delay value at which each processor can normally read and write data. And the data transfer via the synchronous memory can be reliably performed, and one synchronous memory 4 is used as a processor 1 and a processor 2,
Since the processors are shared, the manufacturing cost of the semiconductor integrated circuit to which the present invention is applied can be significantly reduced.

Next, a second embodiment of the clock adjusting circuit for a synchronous memory according to the present invention will be described with reference to FIG. FIG. 4 is a block diagram showing a configuration of a second embodiment of the clock adjustment circuit of the synchronous memory according to the present invention. However, the description of the second embodiment of the clock adjustment circuit of the synchronous memory according to the present invention described below also serves as the description of the second embodiment of the clock adjustment method of the synchronous memory according to the present invention. It is. Also, in FIG.
In FIG. 4, members similar to those shown in FIG.
The same numbers as in FIG. 1 are assigned.

As shown in FIG. 4, the second embodiment of the clock adjusting circuit for a synchronous memory according to the present invention comprises a processor 1, a processor 2, a synchronous memory 4 shared by these processors, A CPU 3, a clock delay selection circuit 9 inside each processor for selecting a clock delay for the synchronous memory 4, a three-state buffer 20 for setting a control signal output of the processor 1 to a high impedance state, A three-state buffer 21 for setting a high impedance state to the clock signal output;
A three-state buffer 22 for setting an impedance state;
A three-state buffer 23 for setting a high impedance state to the control signal output of the processor 2, a three-state buffer 24 for setting a high impedance state to the clock signal output of the processor 2, and a three-state buffer 24 for the address output of the processor 2. Put into high impedance state 3
And a state buffer 25.

Here, as shown in FIG. 4, the processor 1 and the processor 2 are connected via a data bus 5 and a host bus 6, respectively. The data bus 5 is also connected to the synchronous memory 4. Also,
A host CPU 3 for controlling the operation of each processor is connected to the processors 1 and 2 via a host bus 6.

The synchronous memory 4 outputs an address 7 selected by the operation of the three-state buffer 22 and the three-state buffer 25, which is the address from the processor 1 or the address from the processor 2. I have.

The synchronous memory 4 outputs the clock 8 selected by the operation of the three-state buffer 21 and the three-state buffer 24, which is the clock from the processor 1 or the clock from the processor 2. I have.

The synchronous memory 4 stores a control signal 10 from the processor 1 or the control signal 10 from the processor 2 selected by the operation of the three-state buffer 20 and the three-state buffer 23. Has been output.

The structure of the clock delay selecting circuit 9 shown in FIG. 4 is the same as that of the first embodiment of the clock adjusting circuit of the synchronous memory according to the present invention.
, And the description is omitted.

However, in the second embodiment of the clock adjusting circuit of the synchronous memory according to the present invention shown in FIG. 4, the first embodiment of the clock adjusting circuit of the synchronous memory according to the present invention described above. Similarly to the above, the clock delay selection circuit 9 provided in the processor 1 and the clock delay selection circuit 9 provided in the processor 2 are given the same numbers as the same, but are provided in the processor 1. The clock delay selection circuit 9 and the clock delay selection circuit 9 provided in the processor 2 may have independent configurations, for example, in the number of delay elements inside the clock delay selection circuit 9 and the like.

Next, the operation of the clock adjusting circuit of the synchronous memory according to the second embodiment of the present invention shown in FIG. 4 will be described with reference to FIGS. 4 and 5. FIG. 5 shows a flowchart of an example of the operation of the second embodiment of the clock adjustment circuit of the synchronous memory according to the present invention shown in FIG.

As shown in FIG. 5, the host CPU 3
First, it is determined whether to operate the processor 1 or the processor 2 (step S31). In this determination, when the processor 1 is operated (YES), the process proceeds to step S33, and when the processor 2 is operated (NO), the process proceeds to step S41.

If it is determined in step S31 that the processor 1 is to be operated, step S3
3, the host CPU 3 stores the processor 1 in the synchronous memory 4 so that the processor 1 can be processed.
The three-state buffer is controlled to a high impedance state so that an address, a clock, and a control signal are input from the CPU.

More specifically, as shown in FIG. 4, when operating the processor 1, the three-state buffer 2
The three-state buffer 24 and the three-state buffer 25 are controlled to a high impedance state.

On the other hand, if it is determined in step S31 that the processor 2 is to be operated, in step S41, the host CPU 3 sends the synchronous memory 4 to the synchronous memory 4 in order to make the processor 2 ready for processing. The three-state buffer is controlled to a high impedance state so that the address, clock, and control signal of FIG.

More specifically, as shown in FIG. 4, when operating the processor 2, the three-state buffer 2
The 0, 3-state buffer 21 and 3-state buffer 22 are controlled to a high impedance state.

Next, the host CPU 3 sets the control register 100 provided in the clock delay selection circuit 9 of the selected processor to be operated so that the number of selected delay elements becomes zero. The clock based on the delay time causes the selected processor to write and read the synchronous memory 4, and determines whether the same value as the written value has been read.

Then, the number of delay elements to be selected is sequentially increased from 1 to 4, and in this case as well, it is determined whether writing to and reading from the synchronous memory 4 has been normally performed. (Step S35).

Then, the host CPU 3 sets the internal clock 1
The average value of the delay values for which the above-mentioned delay times have been confirmed to be normal operation with respect to 01 is calculated (step S37), and the delay control register 100 sets the delay value so as to be closest to this average value (step S39). . Thus, the selected processor is in a processable state.

Here, since the processor 1 and the processor 2 do not operate at the same time, the synchronous memory 4 is not accessed at the same time.

Therefore, according to the second embodiment of the clock adjusting circuit of the synchronous memory according to the present invention and the second embodiment of the clock adjusting method of the synchronous memory according to the present invention shown in FIG. As in the first embodiment, since the data transfer processing can be executed accurately, the sharing of the synchronous memory between the two processors becomes easy, and the apparatus cost can be greatly reduced.

Further, according to the second embodiment of the clock adjusting circuit of the synchronous memory according to the present invention and the second embodiment of the clock adjusting method of the synchronous memory according to the present invention shown in FIG. By replacing the selector with a three-state buffer as compared with the first embodiment, the three-state buffer can be configured in the same LSI as the processor, and the selector must be placed outside the processor. The number of parts can be reduced compared to the first embodiment.

Further, by arranging a three-state buffer inside the LSI, the delay time to the synchronous memory is reduced, and the period adjustable by the clock delay selection circuit can be advanced, so that the range of selection of the delay time can be expanded. Thus, a more optimal delay time can be selected.

Next, a third embodiment of the clock adjusting circuit for a synchronous memory according to the present invention will be described with reference to FIG. FIG. 6 is a block diagram showing a configuration of a third embodiment of the clock adjustment circuit of the synchronous memory according to the present invention. However, in FIG. 6, the same members as those shown in FIG. 1 are denoted by the same reference numerals. Further, the description of the third embodiment of the clock adjustment circuit of the synchronous memory according to the present invention described below also serves as the description of the third embodiment of the clock adjustment method of the synchronous memory according to the present invention. is there.

The configuration of the clock adjusting circuit of the synchronous memory according to the present invention shown in FIG. 6 is different from that of the first embodiment of the clock adjusting circuit of the synchronous memory according to the present invention shown in FIG. The point is that there is only one processor 1 in the third embodiment, as shown in FIG. Therefore, there is no need to select an output from the processor, and there is no need to provide a selector as shown in FIG. 1 or a three-state buffer as shown in FIG.

That is, the clock adjustment circuit of the synchronous memory shown in FIG. 6 is a clock adjustment circuit of a non-memory sharing type synchronous memory.

Here, the operation of each member shown in FIG. 6, particularly the operation of the clock delay selection circuit 9, will be described with reference to the first clock adjustment circuit of the synchronous memory according to the present invention shown in FIG. Since the operation is the same as that of the clock delay selection circuit 9 in the embodiment, the description is omitted.

Accordingly, in the third embodiment of the clock adjusting circuit for a synchronous memory according to the present invention shown in FIG. 6, even when the synchronous memory 4 is used by one processor 1, the clock delay selection circuit can be used. By using the circuit 9, for example, as shown in FIG. 7, the timing of the internal clock and the clock input to the synchronous memory 4 can be optimally adjusted in the processor 1 to read and write data. 4 can accurately read and write data.

Here, the embodiment of the clock adjusting circuit for the synchronous memory according to the present invention and the embodiment of the clock adjusting method for the synchronous memory according to the present invention are not limited to the above-described embodiments, but may be variously modified. Modifications are possible.

For example, in each of the above-described embodiments, the number of processors has been described as one or two. However, in the clock adjusting circuit for a synchronous memory and the clock adjusting method for a synchronous memory according to the present invention, The number of processors is not limited to such a number, but may be any number.

In the above description of the embodiment,
Although there was no particular limitation on the synchronous memory,
As the synchronous memory to which the semiconductor integrated circuit and the clock distribution method according to the present invention are applied, a dynamic R
AM (DRAM), S-DRAM, ROM, RambusD which is a DRAM having a high-speed interface
A memory such as a RAM that operates in synchronization with another clock signal can be included. Here, Rambus
Base Rambus DRAM, C
once Rambus DRAM and D
directRambus DRAM.

In the above-described first embodiment of the semiconductor integrated circuit and the clock distribution method according to the present invention, a selector is used to select an address, a clock, and a control signal output from each processor. In the second embodiment of the semiconductor integrated circuit and the clock distribution method according to the present invention, a three-state buffer is used to select an address, a clock, and a control signal output from each processor. The main gist of the present invention is to provide a processor with a clock delay selection circuit,
Since the phase of the clock output to the synchronous memory is to be optimized, the member for selecting the signal output from each processor is not limited to the selector or the three-state buffer. Any of those that can be used as the selection means can be used.

Furthermore, in the description of the above-described embodiment, the case where the synchronous memory operates in synchronization with the clock signal is not limited to whether the synchronous memory operates at the rising edge or the falling edge of the clock signal. But,
The edge used in the semiconductor integrated circuit and the semiconductor integrated circuit of the clock distribution method according to the present invention includes:
A rising edge of the clock signal, a falling edge, or both edges may be used.

[0129]

As is apparent from the above description, according to the present invention, the clock output from the processor can be output after giving an optimum delay to the synchronous memory, so A synchronous memory clock adjustment circuit that facilitates sharing of a synchronous memory by two or more processors, accurately reads data from and writes data to the synchronous memory, and enables a significant reduction in device cost. And a method for adjusting the clock of the synchronous memory.

[Brief description of the drawings]

FIG. 1 is a block diagram of a configuration of a first embodiment of a clock adjustment circuit of a synchronous memory according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a clock delay selection circuit included in a clock adjustment circuit of the synchronous memory illustrated in FIG. 1;

FIG. 3 is a flowchart illustrating an example of an operation of the clock adjustment circuit of the synchronous memory illustrated in FIG. 1;

FIG. 4 is a block diagram of a configuration of a clock adjusting circuit of a synchronous memory according to a second embodiment of the present invention;

FIG. 5 is a flowchart illustrating an example of an operation of the clock adjustment circuit of the synchronous memory illustrated in FIG. 4;

FIG. 6 is a block diagram of a configuration of a third embodiment of the clock adjustment circuit of the synchronous memory according to the present invention.

FIG. 7 is an example of a timing chart of the data output of the synchronous memory in the clock adjustment circuit of the synchronous memory according to the present invention and the conventional memory integrated type semiconductor integrated circuit.

FIG. 8 is a block diagram showing a configuration of a first example of a clock adjustment technique in a conventional semiconductor integrated circuit.

FIG. 9 is a block diagram illustrating a configuration of a second example of a clock adjustment technique in a conventional semiconductor integrated circuit.

FIG. 10 is a block diagram showing a configuration of a third example of a clock adjustment technique in a conventional semiconductor integrated circuit.

FIG. 11 is a block diagram showing a configuration of a fourth example of a clock adjustment technique in a conventional semiconductor integrated circuit.

FIG. 12 is a block diagram illustrating a configuration of a fifth example of a clock adjustment technique in a conventional semiconductor integrated circuit.

FIG. 13 is a block diagram illustrating an example of a configuration of a conventional memory-shared semiconductor integrated circuit.

FIG. 14 is an example of a timing chart of data output of a synchronous memory in a conventional memory sharing type semiconductor integrated circuit.

[Explanation of symbols]

1, 2 processor 3 host CPU 4 synchronous memory 5 data bus 6 host bus 7 address 8 clock 9 clock delay selection circuit 10 control signal 13 address 14 clock 15 control signal 20, 21, 22, 23, 24, 25 3-state buffer 83, 84, 85 selector 100 control register 101 internal clock 102 delay element 103 selector 106 clock

Claims (26)

[Claims] A first processor that reads and writes data from and to a synchronous memory; and a second processor that reads and writes data to and from the synchronous memory; A first processor having a first clock delay selection circuit for delaying and outputting a clock signal output to the synchronous memory; and a second processor delaying a clock signal output to the synchronous memory. A clock adjusting circuit for a synchronous memory, comprising: a second clock delay selecting circuit for outputting a clock signal. 2. The method according to claim 1, wherein the first clock delay selection circuit and the second clock delay selection circuit provide a predetermined delay to at least one or more input clock signals, each of which is connected in series, and output the clock signal. And selecting whether to output a clock signal output from the delay element or to output a clock signal input to the first clock delay selection circuit or the second clock delay selection circuit. 2. The clock adjusting circuit for a synchronous memory according to claim 1, further comprising: a selector provided on each output side of said delay element; and a control register for controlling an operation of said selector. 3. The clock of a synchronous memory according to claim 1, further comprising a host CPU for controlling an operation of said first clock delay selection circuit and said second clock delay selection circuit. Adjustment circuit. 4. When the number of delay elements provided in the first clock delay selection circuit is m1 where m1 is an arbitrary positive integer of 1 or more, k1 is set to 0 or more and m1 or less. The host CPU writes to the synchronous memory based on a k1th delayed clock signal that is delayed by k1 delay elements,
And the k-th determination operation for determining whether or not the written value matches the read value is sequentially performed from the 0-th determination operation. By performing up to the m1th determination operation, an average delay amount of the delay amounts giving the coincident values is calculated, and the delay amount closest to the average delay amount is calculated by the first clock delay selection circuit. When the delay amount is assumed to be a delay amount, the clock signal output from the first clock delay selection circuit is used as a clock signal output after being delayed from the first clock delay selection circuit; When the number of delay elements included in the circuit is m2, where m2 is an arbitrary positive integer of 1 or more.
If k2 is an integer having a value of 0 or more and m2 or less, the host CPU determines the synchronous type based on a k2th delayed clock signal that is delayed by k2 delay elements. Writing to memory,
And the k-th determination operation for determining whether or not the written value matches the read value is performed sequentially from the 0-th determination operation. The second clock delay selecting circuit calculates the average delay amount of the delay amounts giving the coincident values by performing the operation up to the m2th determination operation, and calculates the delay amount closest to the average delay amount in the second clock delay selection circuit. The clock signal output from the second clock delay selection circuit is a clock signal output after being delayed from the second clock delay selection circuit when the delay amount is assumed to be the delay amount. 3. The clock adjusting circuit of the synchronous memory according to 3. 5. A first address, a first clock signal, and a first control signal, which are output from the first processor to the synchronous memory, and from the second processor to the synchronous memory. And a selecting means for selecting any one of a second address, a second clock signal, and a second control signal to be output and outputting the selected signal to the synchronous memory. 5. The clock adjusting circuit for a synchronous memory according to any one of 1 to 4. 6. The clock adjusting circuit for a synchronous memory according to claim 5, wherein said selecting means comprises a selector. 7. The method according to claim 7, wherein the selector outputs the first address output from the first processor to the synchronous memory and the second address output from the second processor to the synchronous memory. A first selector to which an address is input; the first clock signal output from the first processor to the synchronous memory; and the first clock signal output from the second processor to the synchronous memory. A second selector to which a second clock signal is input; a first control signal output from the first processor to the synchronous memory; and an output from the second processor to the synchronous memory. And a third selector to which the second control signal is inputted, wherein a first address, a first address, and a first address are outputted from the first processor to the synchronous memory. When outputting a lock signal and a first control signal to the synchronous memory, the first selector, the second selector, and the third selector output signals from the first processor. And selecting a second address, a second clock signal, and a second control signal, which are output from the second processor to the synchronous memory, to the synchronous memory. Controlling the first selector, the second selector, and the third selector so as to select a signal output from the second processor; and outputting a signal output to the synchronous memory. 7. The clock adjusting circuit for a synchronous memory according to claim 6, wherein said clock adjusting circuit is selected. 8. The clock adjustment circuit for a synchronous memory according to claim 5, wherein said selection means comprises a three-state buffer. 9. The first three-state buffer, wherein the first address is input to the first three-state buffer, the first three-state buffer being output from the first processor to the synchronous memory; A second three-state buffer, to which the first clock signal is input, which is output to an expression memory; and a third, to which the first control signal is output, which is output from the first processor to the synchronous memory. A three-state buffer, a fourth three-state buffer to which the second address is input, which is output from the second processor to the synchronous memory, and which is output to the synchronous memory, from the second processor. A fifth three-state buffer to which the second clock signal is input; A first address, a first clock signal, and a first control signal output from the first processor to the synchronous memory. When outputting to the synchronous memory, the fourth three-state buffer, the fifth three-state buffer, and the sixth three-state buffer are set to a high-impedance state; When outputting the second address, the second clock signal, and the second control signal output to the synchronous memory to the synchronous memory, the first three-state buffer and the second A three-state buffer and the third three-state buffer are set to a high impedance state, and a signal output to the synchronous memory is selected. Clock adjustment circuit of a synchronous memory of claim 8, wherein. 10. A clock delay that includes at least one processor that reads and writes data from and to a synchronous memory, wherein the processor delays and outputs a clock signal output to the synchronous memory. A clock adjustment circuit for a synchronous memory, comprising a selection circuit. 11. A clock delay selecting circuit comprising: at least one or more delay elements connected in series, each of which applies a predetermined delay to an input clock signal and outputs the clock signal; and a clock output from the delay element. A selector provided on each output side of the delay element, for selecting whether to output a signal or output the input clock signal, and a control register for controlling an operation of the selector. The clock adjusting circuit for a synchronous memory according to claim 10. 12. The system according to claim 1, further comprising a host CPU for controlling an operation of said clock delay selection circuit.
12. The clock adjusting circuit for a synchronous memory according to 0 or 11. 13. When the number of the delay elements is m, where m is an arbitrary positive integer of 1 or more, and k is an integer having a value of 0 or more and m or less, the host CPU Based on a k-th delayed clock signal that is delayed by k delay elements, causes the processor to perform writing and reading to and from the synchronous memory, and writes the written value and the read value. Are sequentially performed from the 0-th determination operation to the m-th determination operation to determine whether or not are equal to each other. Calculating a delay amount, and assuming that the delay amount closest to the average delay amount is the delay amount in the clock delay selection circuit, the clock signal output from the clock delay selection circuit is converted to the clock delay selection circuit Delayed from Claim, characterized in that the clock signal output on 12
A clock adjustment circuit for a synchronous memory as described in the above. 14. A first clock delay selecting step for delaying a clock signal output from the first processor to the synchronous memory to read and write data from and to the synchronous memory; And a second clock delay selecting step of delaying a clock signal output from the second processor to the synchronous memory for reading and writing data to the synchronous memory. Method. 15. The first clock delay selecting step and the second clock delay selecting step, wherein at least one or more, respectively, serially connected input clock signals are given a predetermined delay and output. A delay element for delaying an input clock signal by a delay element to be output, and outputting the clock signal output from the delay step, selecting the first clock delay, or selecting the second clock delay. 15. A clock signal selecting step of selecting whether to output a clock signal input to the step, and a clock signal selecting control step of controlling an operation of the clock signal selecting step by a control register. Clock adjustment method for synchronous memory. 16. The method according to claim 14, further comprising a clock delay selection control step of controlling operations of the first clock delay selection step and the second clock delay selection step by a host CPU. The clock adjustment method of the synchronous memory described in the above. 17. When the number of delay elements used in the first clock delay selecting step is m1 where m1 is an arbitrary positive integer of 1 or more, k1 is set to 0 to m1 or less. As an integer taking a value, the host CPU writes to the synchronous memory based on a k1th delayed clock signal obtained by delaying k1 delay elements,
And the k-th determination operation for determining whether or not the written value matches the read value is sequentially performed from the 0-th determination operation. By performing the operations up to the m-th determination operation, an average delay amount of the delay amounts giving the coincident values is calculated, and the delay amount closest to the average delay amount is calculated in the first clock delay selecting step. When it is assumed that the delay amount is the delay amount, the clock signal output from the first clock delay selecting step is a clock signal delayed and output from the first clock delay selecting step; When the number of delay elements used in the process is m2, where m2 is an arbitrary positive integer of 1 or more, and k2 is an integer having a value of 0 to m2, the host CPU Based on the k2 delayed clock signal gave k2 pieces of delay of the delay element, writing to the synchronous memory,
And the k-th determination operation for determining whether or not the written value matches the read value is performed sequentially from the 0-th determination operation. By performing up to the m2th determination operation, an average delay amount of the delay amounts giving the coincident values is calculated, and the delay amount closest to the average delay amount is calculated in the second clock delay selecting step. The clock signal output from the second clock delay selecting step is a clock signal output after being delayed from the second clock delay selecting step when the delay amount is assumed to be the delay amount. A method for adjusting a clock of a synchronous memory according to claim 16. 18. A first address, a first clock signal, and a first control signal output from the first processor to the synchronous memory, and from the second processor to the synchronous memory. An output signal selecting step of selecting any one of a second address, a second clock signal, and a second control signal to be output and outputting the selected signal to the synchronous memory. A method for adjusting a clock of a synchronous memory according to any one of claims 14 to 17. 19. The method according to claim 18, wherein the output signal selecting step is a step of selecting an output signal from a processor using a selector. 20. The selector according to claim 20, wherein the selector outputs the first address output from the first processor to the synchronous memory, and the second address output from the second processor to the synchronous memory. A first selector to which an address is input; the first clock signal output from the first processor to the synchronous memory; and the first clock signal output from the second processor to the synchronous memory. A second selector to which a second clock signal is input; a first control signal output from the first processor to the synchronous memory; and an output from the second processor to the synchronous memory. And a third selector to which the second control signal is inputted. In the output signal selecting step, the signal is output from the first processor to the synchronous memory. When outputting the first address, the first clock signal, and the first control signal to the synchronous memory, the first selector, the second selector, and the third selector, Is controlled to select a signal output from the first processor, and a second address, a second clock signal, and a second control, which are output from the second processor to the synchronous memory. When outputting a signal to the synchronous memory, controlling the first selector, the second selector, and the third selector to select a signal output from the second processor. 20. The method for adjusting a clock of a synchronous memory according to claim 19, wherein: 21. The method according to claim 18, wherein said output signal selecting step is a step of selecting an output signal from a processor using a three-state buffer. 22. The three-state buffer, comprising: a first three-state buffer to which the first address is input, the first three-state buffer being output from the first processor to the synchronous memory; A second three-state buffer, to which the first clock signal is input, which is output to an expression memory; and a third, to which the first control signal is output, which is output from the first processor to the synchronous memory. A three-state buffer, a fourth three-state buffer to which the second address is input, which is output from the second processor to the synchronous memory, and which is output to the synchronous memory, from the second processor. A fifth three-state buffer to which the second clock signal is input; and a second output from the second processor to the synchronous memory. A first address, a first clock signal, a first clock signal output from the first processor to the synchronous memory in the output signal selecting step. And outputting the first control signal to the synchronous memory, setting the fourth three-state buffer, the fifth three-state buffer, and the sixth three-state buffer to a high impedance state. Outputting a second address, a second clock signal, and a second control signal from the second processor to the synchronous memory to the synchronous memory, the first three states; A buffer, the second three-state buffer, and the third three-state buffer in a high impedance state to select an output from the processor. Clock adjustment method of a synchronous memory of claim 21, characterized in that the. 23. Synchronization comprising a clock delay selecting step of delaying a clock signal output from at least one processor for reading and writing data to and from the synchronous memory to the synchronous memory. How to adjust the clock of an expression memory. 24. The clock delay selecting step, comprising: a delaying step of delaying the clock signal by at least one or more delay elements that are connected in series and output a predetermined delay to the input clock signal. A clock signal selecting step of selecting whether to output the clock signal output from the delay step or the clock signal input to the clock delay selecting step, and control the operation of the clock signal selecting step by a control register 24. The method of claim 23, further comprising the step of: 25. The synchronous memory clock adjusting method according to claim 23, further comprising a clock delay selecting control step of controlling an operation of the clock delay selecting step by a host CPU. 26. When the number of the delay elements used in the clock delay selecting step is m, where m is an arbitrary positive integer of 1 or more, k is set to a value from 0 to m. As an integer to be taken, the host CPU causes the processor to perform writing and reading to and from the synchronous memory based on a k-th delayed clock signal obtained by delaying k delay elements. The k-th determination operation for determining whether the value matches the read value is sequentially performed from the 0-th determination operation to the m-th determination operation. The average delay amount of the delay amount giving the value is calculated, and if the delay amount closest to the average delay amount is the delay amount in the clock delay selecting step, the delay amount is output from the clock delay selecting step. Clock Clock adjustment method of a synchronous memory of claim 25, characterized in that it comprises a clock signal selection step of the clock signal output signal is delayed from the clock delay selection step.