JP2000031953A - Digital phase locked loop and clock recovery circuit - Google Patents

Abstract

(57) Abstract: A digital phase locked loop circuit that outputs a reproduction clock synchronized with an input signal even while input burst data is paused. Further, a circuit for outputting a stable reproduction clock with little influence of jitter in the input signal is obtained. SOLUTION: A frequency and a phase in a digital input signal are extracted, a phase is compared with an output, and a feedback control is performed so as to add an increase / decrease shift amount to a circuit-specific original clock based on a phase difference of the comparison result. In a configuration for obtaining a clock output, a shift request generating means for generating a predetermined amount of shift after a predetermined period of time is provided in a feedback control loop, and when a digital input signal is interrupted and phase information of the input signal cannot be obtained. The feedback control is performed by adding a predetermined shift amount to the time determined by the shift request generating means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital phase-locked loop (DPLL) for generating a reproduction clock having a frequency synchronized with the frequency of burst-input data even during a pause.

[0002]

2. Description of the Related Art As a circuit for identifying data input in a burst manner by using a timing source asynchronous with the frequency of the data, for example, in the clock recovery system disclosed in Japanese Patent Application Laid-Open No. 02-56134, FIG. It has such a configuration. In this conventional example, in addition to a phase comparator, a loop filter (up-down counter), a fixed frequency oscillator, a pulse rejection adder, and a frequency divider, which are basic digital phase locked loop circuits, a frame synchronization signal is obtained from an input signal. And a control circuit for controlling the parameters of the up / down counter and the pulse elimination adder.

The operation of the DPLL by the above-mentioned prior art circuit will be described. In the figure, a binary quantization phase comparator 303 compares the phases of an input signal 301 and a reproduced clock 302, and outputs a leading (1) and a lagging (-1) signal. The up / down counter 304 counts 1 and −1, and when the count value matches the set value + N or −N,
The advance or delay is notified to the pulse rejection adder 305. The pulse removal adder 305 normally transmits the reference pulse number to the frequency divider 307, but when it receives advance or delay information, it advances, , An M bit pulse is added and removed. The frequency divider 307 frequency-divides a plurality of pulses received from the pulse rejection adder 305 into one cycle clock.

The above is the basic operation of the DPLL.
In such a DPLL, the pulse elimination adder operates more sensitively to the phase difference as N is smaller, and the amount of correction per phase difference is larger as M is larger, so that it is suitable for high-speed synchronization pull-in. Conversely, when N is large and M is small, the influence of the error of the phase comparator due to noise on the pulse rejection adder is small, and the synchronization accuracy is improved.
Moreover, it is suitable for high-accuracy clock reproduction. As can be seen from the above, in a normal DPLL, high-speed synchronization pull-in and high stability are incompatible with each other because of the contradictory characteristics. Therefore, in the above-mentioned conventional technology, the parameters of N and M are changed between during synchronization pull-in and after synchronization. We are implementing.

The format of a generally transmitted burst signal is as shown in FIG. 20, and the preamble portion at the head of the burst is 1,0,1,0... So that the bit phase of data can be easily identified.・ It is a police box pattern. Thereafter, there is a frame synchronization pattern for identifying a frame phase, and thereafter, management information for transmission and user information to be actually communicated are transmitted. The preamble portion is an unnecessary overhead for information actually communicated, and there is a demand to set the preamble portion as short as possible in order to increase transmission efficiency. Thus, at the time of synchronization pull-in, the above parameters are set for high-speed pull-in, and the clock phase is pulled in at high speed in the preamble portion. When the frame detector 308 detects a frame synchronization pattern, the parameters are set for high stability and high accuracy. By the above operation, high-speed burst synchronization can be obtained, and the reproduction clock used for data identification can be made highly stable and accurate, so that highly efficient and reliable burst data transmission can be realized.

[0006] However, in the above-mentioned conventional example, although the performance of discriminating burst data is taken into consideration, there is no function of extracting a frequency component of data to be received and constantly generating a stable reproduction clock. That is, the reproduced clock is not stable in the portion where there is no burst data. FIG.
9 is a diagram illustrating an example of an operation in the device having the configuration of FIG. Even if the phase difference between the data and the reproduced clock is large at the beginning of the burst, the phase is shifted in a short time, and the subsequent phase becomes stable. During this time, the phase of the reproduced clock is constant with a certain width with respect to the phase of the data, so that its frequency is on average synchronized with the frequency of the data. However, when the burst data ends, in the above conventional example, the function of controlling the clock phase does not work. Becomes This is because the base clock that generates the recovered clock is generated by a fixed frequency oscillator, and therefore cannot exactly match the frequency of the input data.
When the input signal disappears, an open loop state occurs, and the phase shifts more and more at a rate according to the magnitude of the frequency shift.

[0007]

As described above, in the conventional digital phase-locked loop, the reproduction clock is shifted when the burst data of the received signal is lost, and it is necessary to obtain the synchronization again from the out-of-sync state at the time of re-reception. There is a problem that it takes time until a correct reproduction clock is obtained. Of course, there is also a problem that a correct reproduction clock cannot be obtained during the burst pause. In addition, since the feedback control is performed immediately following the phase difference exceeding the threshold value even during the burst, the shift direction is likely to be reversed due to the influence of the fine jitter, and the reproduction clock is not stable.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital phase locked loop circuit which outputs a reproduction clock synchronized with an input signal even when input burst data is paused. Still another object of the present invention is to provide a circuit which outputs a stable reproduction clock with little influence of jitter in an input signal. It is still another object of the present invention to provide a circuit that converges on a stable reproduction clock with little influence of jitter in a short time.

[0009]

A digital phase locked loop circuit according to the present invention extracts a frequency and a phase from a digital input signal, compares the phase with the output of a reproduced clock, and performs a circuit based on the phase difference of the comparison result. In a configuration in which the output of the reproduction clock is obtained by performing feedback control so as to add an increase / decrease shift amount to the original original clock, shift request generation means for generating a predetermined amount of shift amount after a predetermined time is provided in the feedback control loop. If the digital input signal is interrupted and the phase information of the input signal cannot be obtained, a predetermined amount of shift is added to the time determined by the shift request generating means to perform feedback control.

Further, a phase difference integration means for detecting whether a phase difference between a digital input signal and an output reproduction clock exceeds a threshold value, an average time until the threshold value detected by the phase difference integration means exceeds the threshold value, and a direction of increase / decrease Shift interval averaging means for calculating and storing the shift amount, and the shift request generation means generates an increase / decrease direction in which the shift amount to be stored is stored when the time stored by the shift interval averaging means elapses, and performs feedback control. did.

Further, the shift interval averaging means requests the shift request means to generate the shift amount every time the average time elapses without correcting the average time when the phase difference obtained by integrating the specified time is small. I did it.

Further, when the phase difference is large, the shift interval averaging means obtains an approximate frequency from the time until the threshold is exceeded each time, and averages the obtained approximate frequencies to obtain an average frequency. The approximate average time was obtained from the obtained average frequency.

Further, when the phase difference is large, the shift interval averaging means obtains an approximate frequency from the time until the threshold value is exceeded each time, and averages the obtained approximate frequency using a weight coefficient. The average frequency was determined, and the approximate average time was determined from the determined average frequency.

Further, when the phase difference is large, the shift interval averaging means obtains an approximate frequency from the time until the threshold value is exceeded each time, and averages the obtained approximate frequency using a weight coefficient. An average frequency is obtained, an approximate average time is obtained from the obtained average frequency, and the weight coefficient is changed depending on the shift direction or the number of times of averaging.

Further, after detecting the phase difference between the digital input signal and the output recovered clock, a low-pass digital filter and a phase difference detection signal exceeding the set threshold of the low-pass digital filter are used as shift information. A shift interval counting means for obtaining a shift interval time and a shift interval averaging means for calculating and storing a shift interval time average and a direction detected by the shift interval counting means are provided, and a phase difference is large in a period during which a digital input signal is obtained. In such a case, the shift request generating means generates the shift amount in the increasing / decreasing direction in which the shift amount to be stored is stored after the lapse of the time stored by the shift interval averaging means, and performs feedback control.

Further, when the phase difference is large, the shift interval averaging means averages the time until the threshold value is exceeded each time using a weighting coefficient to obtain an average time.

Further, the shift interval averaging means stores the time when the phase difference is 0 and the feedback control is performed by the shift request generating means as the initial averaging time to be stored first.

Still further, when the average time of the shift interval is obtained, an assumed value minimum interval time is set, and the shift interval averaging means first stores the average time, and when the average time is stored, the expected value minimum interval time is shorter than the assumed value minimum interval time. The shift interval input is excluded and the average time is obtained and stored.

Further, when performing the feedback control to add the increase / decrease shift amount, during the period in which the digital input signal is obtained, the shift request generated by the shift request generating means is ignored and the setting of the low-pass digital filter is performed. Feedback control is performed in which a phase difference detection signal exceeding a threshold value is set as a shift request and an increase / decrease shift amount is added.

Furthermore, after detecting the phase difference between the digital input signal and the output recovered clock, a low-pass digital filter and a phase difference detection signal exceeding a set threshold value of the low-pass digital filter are shifted as shift information. A shift interval counting means for calculating an interval time; and a shift interval averaging means for calculating and storing a shift interval time average and a direction detected by the shift interval counting means. Is sampled a plurality of times, and the median of the maximum value and the minimum value is output as a value after filtering, and the shift request generating means determines the amount of shift to be stored when the time stored by the shift interval averaging means elapses. It occurs in the direction of increase / decrease to be stored, and feedback control is performed.

A clock recovery circuit according to the present invention extracts a frequency and a phase from a digital input signal, compares the frequency and phase with an output reproduction clock, and converts the frequency and phase into a circuit-specific original clock based on the phase difference of the comparison result. In a configuration in which feedback control is performed so as to add an increase / decrease shift amount, a predetermined amount of increase / decrease shift amount is requested in a feedback loop, and when a digital input signal is interrupted and phase information of the input signal cannot be obtained, Shift request generating means for requesting the addition of the average increase / decrease shift amount for each stored average time, and shift control means for adding the increase / decrease shift amount based on the request of the shift request generation means and providing a reproduced clock before frequency division. With.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 The basic concept of the present invention is a typical circuit configuration for generating a reproduction clock at the time of receiving a burst signal before the burst pause period and obtaining a reproduction clock which is not affected by jitter even during the reception of the burst signal. In this embodiment, in a typical DPLL, several phase correction signals obtained from the immediately preceding phase difference signal are averaged and stored, and when a predetermined threshold value is reached or the stored average time elapses, the storage shift is performed. A shift interval control means for instructing the value to be increased or decreased in the original clock is provided, and the configuration is changed to a loop filter.

Hereinafter, the configuration of the digital phase locked loop circuit according to the present embodiment will be described with reference to FIGS. FIG. 1 is a configuration diagram of the entire phase synchronization circuit. In the figure, 101 is input data, 102 is identification data, 103 is a reproduced clock as output, 104 is phase comparison means, 106 is shift control means, and 107 is an original data. Reference numeral 108 denotes a frequency dividing means, 109 denotes a data identifying means, and 110 denotes a shift interval controlling means which is an important new element in the present embodiment. Reference numeral 111 denotes frame phase information, and 112 denotes input data disconnection information. Reference numeral 100 denotes a clock recovery circuit composed of these elements. FIG. 2 shows a detailed configuration example of the shift interval control unit 110. In the figure, 2
02 is a shift interval averaging means, 203 is a shift request generating means, 204 is a clock number counting means, 205 is a phase difference integrating means, 103 is a reproduction clock, 207 is phase difference information, and 209 is a shift control means for instructing phase correction. Shift request.

Next, the operation of the circuit having this configuration will be described. The phase comparison unit 104 samples the phase difference between the input data 101 and the reproduction clock 103 using the high-speed clock from the original clock generation unit 107 and sends the result to the shift interval control unit 110 as phase difference information 207. This is the same operation as the conventional one. Although the operation of the shift interval control means 110 will be described later, this phase difference information is averaged and stored,
When a predetermined period or deviation occurs, a shift request signal is sent to the shift control means 106 as an output. Shift control means 1
In step 06, when there is no shift request signal, n is sent as the number of shifts s when there is a shift request signal, and n + s is sent to the frequency dividing means 108 as the frequency dividing number. Source clock generation means 10
7 generates a high-speed clock having a frequency n times the assumed frequency of the input data. The dividing means 108 divides the high-speed clock according to the dividing number from the shift control means 106,
A reproduction clock 103 is generated. In the above operation, when there is input data, the basic operation in which the shift interval control means 110 generates the shift request signal is the same as the operation of the basic digital phase locked loop.

The operation of the shift interval control means 110 will be described. The phase difference integration means 205 includes an up / down counter, and counts up or down based on the value of the phase difference information 207. A threshold value N is set in the up / down counter, and when the count value reaches + N or -N, +1 and -1 are notified to the shift interval averaging means 202, and at the same time, the count reset signal is sent to its own up / down counter and clock. Number counting means 20
Send to 4. This configuration and operation are equivalent to a conventional loop filter. The clock number counting means 204 performs an operation corresponding to a timer for measuring a predetermined time. That is, the number of reproduction clocks is counted up to a preset maximum value cmax, and the value is sent to the shift interval averaging means 202.
When the count value reaches cmax, the counting operation is stopped, the value is held, and count overflow information is sent to the shift interval averaging means 202. The count value is reset by a count reset signal from the phase difference integration means 205.

The shift interval control means in the first embodiment of the present invention averages and stores the frequency deviation by a simplified calculation method, and corrects the averaging calculation when the integrated value of the phase difference information exceeds a threshold value. The shift direction is sent to the shift control means only after the passage of the corrected cycle to obtain a predetermined shift amount. The shift interval averaging means 202 averages the threshold excess information generated so far by a method according to the flowchart shown in FIG. In the figure, cshift is a threshold excess occurrence interval count, and s1 is threshold excess information (+ 1 /-
1), cmax is the maximum value of the count exceeding the threshold occurrence interval, N
a is a shift interval averaging weighting coefficient, cst is the difference of the current shift, rdf is the difference by the average value up to the previous shift, r
shift is the shift interval average value, and r1 is the shift direction (+ 1 / -1) of the average value. First, in step S1, the initial value of the average value is set to 0. At S2, the phase difference integrating means 20
When the threshold N is exceeded from 5 in S3, it is determined in S3 whether or not the number of reproduction clocks required for the maximum has reached the maximum value cmax, based on the overflow information. If so, it is determined that the phase difference is small, the average value is left as it is (S4), and in S5, shift request compulsory generation information and threshold excess information s1 (+1 or -1) are sent to the shift request generating means 203. If the number of reproduction clocks required for the occurrence of the excess of the threshold value has not reached the maximum value cmax, that is, if it is determined that the phase difference is large, correction calculation of the average value is performed. In the calculation, a difference from the upper limit value cmax is obtained based on the count value of the threshold excess occurrence interval, and is set as an approximate frequency. That is, in the limited T region where the cycle is T, the frequency is obtained by approximating 1 / T ≒ KT.
Similarly, the average value is also calculated by taking the difference from cmax and averaging the differences as an approximate frequency. When calculating the difference, the threshold excess information s1 and the shift direction r of the average value
The shift value and the shift direction are determined in consideration of the sign of 1 (+1 or -1). However, when the average shift interval is 0, the difference is also set to 0 (S6). At the time of calculation, a coefficient Na for weighting the average value up to the previous time, for example, 3 is set (S7).

After calculating the average of the differences, the sign (+/-) information indicating the shift direction of increase / decrease is stored, and this is set as r1. Thereafter, the difference from cmax is again calculated based on the difference value from which the sign has been removed in S8, and the difference is returned to the approximate period (time).
And the result is the new shift interval value (time). Then, the average shift interval and the shift direction, which are the calculation results, are sent to the shift request generation means 203 in S9.

Another operation in which the circuit of the present embodiment is different from the basic DPLL is that the shift request generating means 203 issues a shift request immediately and the shift control means does not perform feedback for phase correction. It is to wait. That is, the shift request generating means 203 counts the number of reproduction clocks from the time when the previous shift request was generated, that is, monitors the time, and this count value (time) is used as the shift value from the shift interval averaging means 202. When the interval average value is reached, a signal of a shift request 209 of +1 or -1 is generated in S9 according to the shift direction information also obtained from the shift interval averaging means 202. Further, even if a predetermined time has elapsed since the previous phase correction and shift request compulsory occurrence information is input in S5, the threshold excess information s1 is immediately
Generates a +1 or -1 shift request signal. Then, the count value of the reproduction clock is reset at the same time when the shift request signal is generated.

FIG. 4 is a diagram showing the relationship between the frequency deviation (phase deviation) and the pulse interval indicated by the input phase difference information 207. If the correction of the phase difference is to be averaged in order to avoid the influence of fine jitter, it must be converted to a frequency equivalent and averaged instead of averaging at time intervals. This is because if the number of pulses corresponding to time is averaged with a sign as the shift interval as it is, the greater the number of pulses, that is, the greater the interval, the greater the effect. However, as can be seen from FIG. 4, the intervals are actually long (large).
In the shift control, the component of the frequency deviation between the input data and the original clock is small, and conversely, the shorter the interval, that is, the greater the phase difference information in which the deviation occurs in a short time, the larger the frequency deviation. Therefore, as described above, by taking the difference from the maximum value of the count from the interval value, it is approximately expressed in frequency, and the numerical value of the smaller interval is increased, so that the correction is correctly performed. ing. That is, in the limited range,
This means approximating 1 / T ≒ KT.

FIG. 5 shows an example of a phase change by the circuit according to the present embodiment. This figure shows the change in the phase difference between the input data and the recovered clock since the initial burst data input. As described in the conventional example, since the frequency between the input data and the original clock (1 / n) shifts, the phase difference gradually increases unless the shift operation is performed. In the initial state, the average shift interval in the shift interval control means is 0.
Since no shift request is generated, the phase difference increases (near a in the figure). When the phase difference becomes large, the phase comparison means 104 constantly outputs the phase difference information, and the up / down counter of the phase difference integration means 205 as a filter exceeds the threshold value + N or -N.
The shift is output to interval averaging means 202. Based on this, a shift interval is calculated by the interval averaging means.
When the number of reproduced clocks from the beginning reaches the shift interval value (at first, the interval is set to the interval B), the shift request generating means 203 generates a shift request, and the shift control means 106 controls the phase shift. (Near b in the figure). If the phase difference still remains, the value of the up / down counter exceeds the threshold value + N, the average value of the shift interval is corrected, and the interval stored in the shift interval averaging means 202 referred to by the shift request generating means is similarly calculated. Becomes shorter,
The phase shift by the shift control means 106 frequently occurs (near c in the figure). As a result, when the shift interval becomes shorter than the actually required shift interval, the phase difference changes to the negative side (near d in the figure), and the value of the up / down counter exceeds the opposite threshold value -N. The interval is corrected and the interval becomes slightly longer. Since the phase difference information is lost during the burst pause, the shift interval itself is not corrected, the average value up to the previous time is held, and the shift is continued based on the held interval (near e in the figure).

As described above, unlike the basic DPLL, the shift control is averaged based on the previous shift interval results. In addition, the average shift interval is calculated based on the frequency of the input data, and gradually converges to the shift interval based on the average frequency. The speed of the convergence differs depending on the threshold value N of the up / down counter and the setting of the weighting coefficient Na at the time of calculating the shift interval average. In the case where the input data has little noise and the accuracy of the phase of the original clock is high, it is possible to make N and Na small to converge at high speed, and conversely, there is much noise in the input data,
Further, when the accuracy of the phase of the original clock is low, N and Na need to be increased to suppress the influence of noise and the like, so that the convergence time becomes relatively long. Thus, the clock recovery circuit 100 extracts and follows the clock included in the input data, and can obtain a recovered clock based on the average clock cycle even during the burst pause period.

Embodiment 2 FIG. A phase synchronization circuit using other shift interval control means for performing shift correction even during a burst pause period, averaging and storing some phase corrected signals after filtering during input of a burst signal, and instructing increase or decrease based on the average. Will be described. In the circuit of the present embodiment, in the data input part, after extracting the low frequency component with a filter, the phase comparison result is converted to an approximate frequency and averaged, and the phase shift control is performed with a value obtained by returning the averaged result to the average interval. Then, the frequency deviation between the input data and the original clock is feedback-controlled. FIG. 6 shows the entire configuration of the digital phase locked loop circuit according to the present embodiment. In the figure, 10
5 is a digital filter. The other elements are the same as those in FIG. 1 and will not be described. The clock recovery circuit 10
0 can also be realized by connection with the elements in FIG. Also,
FIG. 7 shows a detailed configuration of the shift interval control means 110b.
In the figure, 201 is a shift interval counting means, 208
Is phase difference shift information. The other elements are the same as those in FIG.

Next, the operation of the circuit having this configuration will be described. The operation of the phase comparing means 104 is the same as that of the first embodiment, but sends the phase difference information to the filter 105. The filter 105 performs the same operation as that of the phase difference integration means 205 in the first embodiment.
One shift request signal is sent to the shift control means 106 and the shift interval control means 110b. Shift interval control means 11
Although the operation of 0b will be described later, a shift request signal is generated as an output signal as in the first embodiment. The shift control means 106 monitors these two kinds of shift request signals,
When there is no request for either, n is set as n + s or n−
s is sent to the frequency dividing means 108 as a frequency dividing number. The operations of the original clock generating means 107 and the frequency dividing means 108 are the same as in the first embodiment.

The operation of the shift interval control means 110b will be described. The shift interval counting means 201 has a count of the maximum count value cmax, and counts an interval at which the phase difference shift information 208 is input by a reproduction clock to obtain time information. This count value is used as the shift interval value cs
The phase difference shift information 208 is sent to the shift interval averaging means 202 as +1 and −1 as the shift direction s1. When the count value reaches cmax, the counting operation is stopped, the value is held, and count overflow information is sent to the shift interval averaging means 202.

The shift interval averaging means 202 averages the threshold excess information generated so far by a method according to the flowchart shown in FIG. First, the initial value of the average value is set to 0 in step S11. If a phase shift has occurred in S12, it is determined in S13 from the shift information 208 whether or not it is based on the result of the phase comparison. If it is based on the phase comparison result, it is determined in S14 whether the number of reproduced clocks from the previous phase shift has reached the maximum value cmax based on the overflow information from the shift interval counting means 201, and if it has reached the maximum value. , S15, the average value is left as it is. If the number of reproduction clocks required for the occurrence of exceeding the threshold value has not reached the maximum value cmax, correction calculation of the average value is performed in S16. The calculation is the same as the averaging method of the first embodiment. That is, the pulse interval of the shift request is changed to the approximate frequency (S16), and the average frequency is calculated (S17).
It returns to the original interval value (S18).

FIG. 9 shows an example of a phase change by the circuit in the present embodiment. This figure shows the change in the phase difference between the input data and the recovered clock since the initial burst data input. In the present embodiment, the phase difference by the phase comparing means 104 is reduced and filtered, and the phase difference shift information 208 is averaged or directly leads to a phase shift.
Compared to the first embodiment, a phase shift at the time of data input is more likely to occur, and feedback control for eliminating a phase difference with data earlier works. For this reason, the phase difference decreases early as shown in the figure. However, as in the basic DPLL, the jitter of the reproduced clock tends to increase due to a sudden phase shift of the input data because it follows the phase of the input data as needed. Therefore, this embodiment is suitable for applications in which data identification performance is high during burst data input and a stable clock is reproduced during burst pause.

Embodiment 3 In the present embodiment, the shift interval averaging means in the first or second embodiment weights data for calculating the average interval value. That is, when the control direction of the new shift is different from the control direction of the shift of the averaging result value up to the previous time, and is also different from the control direction of the previous phase shift, the averaging result value of the previous time is further increased. Thus, the effect of the immediately preceding shift information data is reduced.

The configuration of the digital phase-locked loop, the configuration of the shift interval control means 110c, and the flow of shift interval averaging in the present embodiment are, for example, applied to the second embodiment, respectively. 7 and FIG. The difference from the second embodiment is that in the shift interval averaging flow, the average direction shift direction r
1 is different from the shift direction s1 of the new shift occurrence, and
When it is different from the previous shift direction s1, the weighting coefficient Na for the average value, for example, the value of 3, is further increased. With this increase rate as Napn, the averaging calculation is represented by the following equation (1). Other operations are the same as in the second embodiment.

The reason for further changing the weight coefficient itself will be described with reference to the operation example diagram of FIG. In the case of a configuration in which the phase is immediately shifted by detecting the phase difference in the data input portion as in the present embodiment, an area where the phase difference is not recognized by the phase comparing means 104 for the purpose of reducing the jitter due to the phase control, that is, A method of providing a wide phase difference 0 region is effective. That is, when a phase is detected outside the zero phase difference region, a phase shift occurs, and the phase difference detected within the region is regarded as having no phase difference. However, even in this case, a phase shift may occur due to a phase error such as jitter added to the input data when the actual phase difference should not cause a shift.

FIG. 11 is an operation example diagram when another reverse shift occurs. As shown in FIG. 11, in the case of a frequency deviation in which the phase difference moves away to the + side when the phase is not shifted, if the shift interval averaging is substantially converged, the shift in the-direction is performed at a certain interval. It should be the shift interval value. However, when the convergence value is slightly shifted, as shown in the figure, the phase difference gradually increases during the burst pause period, and a negative phase may be detected during the next burst period. In both of FIGS. 10 and 11, a shift in the + direction (upward) may occur immediately after a shift in the-direction (downward). At this time, since the interval value up to the shift in the + direction (upward) is very small, if the above-described averaging calculation is performed with the interval value as it is, the influence of the shift in the reverse direction becomes very large, and the shift interval The average value of can be quite crazy. Therefore,
By setting an appropriate value for Napn and reducing the weight of the correction amount of the sudden reverse shift that occurred immediately before, that is, increasing the average value up to that point, the shift interval of the shift interval can be increased. The value can be stabilized.

Embodiment 4 FIG. In the first embodiment,
Interval input, that is, conversion from time to an approximate frequency to obtain an average value, and return the obtained average value to indicate the interval value. This is because the computer is not good at reciprocal calculation. However, in the present embodiment, the first embodiment
The shift interval averaging means in is not as an approximation,
In order to obtain the averaged value, the frequency which is the reciprocal of the interval of each phase shift is calculated, the calculated frequency is averaged to obtain the average frequency, and the reciprocal is calculated again for the averaged frequency to obtain the interval. By obtaining the values, correct phase shift intervals are averaged. The configuration of the digital phase locked loop circuit and the configuration of the shift interval control means 110d in the present embodiment are the same as those in FIGS. 1 and 2. Shift interval control means 11 in the present embodiment
FIG. 12 is a flowchart of the shift interval averaging operation performed by Od.
Shown in What is different from FIG. 3 is that the target of averaging is not approximation by the difference from the maximum count value, but that the frequency is obtained by the reciprocal of the interval value in S26 and that the interval value is again correctly calculated by S2 in S28. It is only that. Other configurations and operations are the same as those of the first embodiment. Of course, it may be applied to the circuit of the second embodiment.

As described above, the principle of the present averaging method is the same as that described with reference to FIG. 4 in the first embodiment.
Since the components of the frequency deviation at each shift interval are calculated more accurately, errors in the calculation result are reduced. On the other hand, the calculation of the reciprocal takes a long time to process in a normal digital circuit, and the processing circuit becomes large, so that it is suitable for a phase synchronization circuit for data having a relatively low transmission speed.

Embodiment 5 FIG. As a change of the third embodiment, in the present embodiment, the shift interval averaging means in the first embodiment performs averaging as a method of performing averaging. The weight of the result value is increased according to the number of times of averaging. The configuration of the digital phase-locked loop, the configuration of the shift interval control means 110e, and the flow of shift interval averaging in the present embodiment are, for example, applied to the first embodiment, as shown in FIGS. Same as 3. The difference from the first embodiment is that the weighting coefficient Na for the average value is increased according to the number of times of averaging in the shift interval averaging flow. This increase rate is
a, the number of times of averaging is Nas, and the weighting coefficient Na is expressed by the following equation (2). However, since the increase is infinite,
Set the upper limit Nam. Other operations are the same as those in the first embodiment. Na = Naa * Nas However, Na ≦ Nam (2) As described with reference to FIG. 5 in the operation example of the phase correction of the circuit in the first embodiment, the convergence of the shift interval value is slower as the weighting coefficient Na is larger. On the other hand, the stability after convergence is good. Therefore, when this method is applied, at the beginning of the phase correction start, the weighting coefficient Na is small and the convergence is quick, and on the other hand, after the convergence, the weighting coefficient Na is large and the stability is improved.

Embodiment 6 FIG. In the present embodiment, an appropriate interval value at the time of the initial correction is obtained, and the convergence time is shortened. That is, the shift interval averaging means according to the second embodiment starts calculating the phase shift interval only when the input data phase is detected in the phase difference 0 area after the initial data input and when the phase shift occurs thereafter. The calculation is started from. The configuration of the digital phase-locked loop, the configuration of the shift interval control means 110f, and the flow of shift interval averaging in this embodiment are the same as those in FIGS. 6, 7, and 8, for example. The difference from the second embodiment is that the phase comparison means detects a phase difference of 0 and the shift control by the phase comparison has occurred once as a condition in S16 for taking in the initial shift interval for calculating the interval value. It is later. Other operations are the same as in the second embodiment.

The state of correction performed by this method will be described with reference to an operation example diagram of FIG. If there is an error in the shift interval to be taken in at the beginning, it takes time for the subsequent correction, and the convergence time is delayed. By the way, in the initial operation, as shown in FIG. 13, the initial phase difference is large, shift control at short intervals for phase difference correction is likely to occur, and even if the phase difference disappears, the phase shift May occur. In the present embodiment, in order to avoid such an influence, after an initial operation such as power-on, a phase difference of 0 is first detected, and a shift interval after a once phase shift occurs is taken in at an initial stage. In this way, the interval indicated by c in the figure is taken in as the interval value, and the shift interval value far from the first two actual frequency deviations is excluded, so that the subsequent convergence time is shortened.

Embodiment 7 FIG. Another method for avoiding the input of the interval value having a large error in the initial transient state will be described. According to the present embodiment, in the shift interval averaging means in the second embodiment, the interval value to be sampled first to calculate the phase shift interval in order to take in an appropriate interval value is replaced by the assumed phase shift interval value. If the value is out of the range, the value is ignored and is taken in from the interval value of the next phase shift. The configuration of the digital phase-locked loop according to the present embodiment, the configuration of the shift interval control means 110g, and the flow of shift interval averaging are the same as those shown in FIGS. 6, 7, and 8, for example. The difference from the second embodiment lies in the range of the phase shift interval value in which the interval value (time) is obtained from the assumed frequency deviation as a condition at S16 for taking in the initial shift interval for the interval value calculation. After that, it is determined that a suitable one is taken. Other operations are the same as in the second embodiment.

The manner in which the present system performs correction will be described with reference to the operation example diagram of FIG. The state of the initial phase control operation is the same as that described with reference to FIG. 13, and it is assumed that the first phase shift interval is a, and the next is b and c. On the other hand, it is assumed that the value of the shift interval assumed from the frequency accuracy of the input data and the original clock is equal to or longer than DIS. Then,
a and b are far from the shift interval to be actually converged, and if they are substituted as shift interval values, the error will increase.
Therefore, in this method, a, b, and c are assumed to be the assumed minimum intervals DIS.
Since a <b <DIS <c, the interval values of a and b are removed, and the interval shown by c in FIG. In this manner, since the shift interval value far from the actual frequency deviation is excluded as the interval value, the convergence time is shortened.

Embodiment 8 FIG. In each of the above embodiments,
The case where the addition / subtraction shift control is performed in response to the shift request from the same shift interval control means both when there is a burst input and during the pause of the burst has been described. In the present embodiment, in the shift control means according to the second embodiment, the phase shift time based on the phase difference shift information 208 from the filter 105 during burst input and the shift request 209h from the shift interval control means 110h during burst pause. Thus, the time for the phase shift is completely separated. The configuration of the digital phase-locked loop according to the present embodiment, the configuration of the shift interval control unit 110h, and the flow of shift interval averaging are the same as those in FIGS. 6, 7, and 8, for example. The difference from the second embodiment is that the shift control unit 106
h determines whether the current time is a data input part (during burst) or a data input non-part (burst pause) based on the frame phase information 111, and a data input part (during burst).
In this embodiment, the phase shift control is performed in accordance with the phase difference shift information 208 from the filter 105, and the phase shift is performed in response to a shift request from the shift interval control unit 110b when the data is not input (burst pause).

In this embodiment, in the data input portion,
Since the shift request from the shift interval control unit 110b is ignored, even if an unnecessary phase shift request 209b is instructed from the shift interval control unit 110b due to a state in which the shift interval value is not converged, Since the phase shift is not performed, and the phase shift is performed according to the phase difference shift information from the filter, the data shift has no influence on the data identification performance, and stable data identification can be performed. This embodiment has relatively many data change points,
This is effective when applied to a case where the same code continuous length is short.

Embodiment 9 FIG. In the present embodiment, a phase shift control is performed based on a phase comparison result in a data input portion, and a shift interval corresponding to a frequency deviation between input data and an original clock is obtained by averaging the shift intervals. is there. Here, a device will be described in which the shift interval is further averaged and obtained. The configuration of the digital phase locked loop circuit according to the present embodiment is the same as that of FIG. However,
The internal configuration of the shift interval control means 110i is different, and its detailed configuration is shown in FIG. In the figure, reference numeral 215 denotes a shift interval calculating means. Other shift interval averaging means 202, shift request generating means 203, reproduction clock 10
3, shift request pulse 207, phase difference shift information 20
8, or the secondary shift request pulse 209b is the signal shown in FIG.
Represents the same thing as that of.

Next, the operation will be described. As described in the second embodiment, the phase comparison unit 104
The phase difference between the original clock and the reproduced clock 103 is sampled by the high-speed clock from the original clock generator 107 and sent to the filter 105. The filter 105 includes an up-down counter, and when the phase difference is +, the up-counter
If the phase difference is-, count down and the count value is ±
When it reaches either of N, the shift request pulse of +1 or -1 is sent to the shift control means 106 and the shift interval control means 110i, and at the same time, the count value is reset.
Although the operation of the shift interval control means 110i will be described later, a secondary shift request pulse 209b as its output is sent to the shift control means 106, and the shift control means 10i based on this is transmitted.
6, the output operation is n when there is no shift request pulse, and the number of shifts s when there is a +1 shift request pulse.
Outputting n + s when there is a shift request pulse of −1 is the same as that of the second embodiment. The original clock generating means 107 and the frequency dividing means 1
Operation 08 is the same as in the second embodiment.

The operation of the shift interval control means 110i will be described with reference to the flowchart of FIG. The shift interval calculating means 215 includes an up / down counter. First, in step S31, the initial value is set to 0, and the phase difference shift information 208 is set.
Are integrated taking the direction into account. That is, S32
The up-count is performed when the shift is +, and the down-count is performed when the shift is negative. Further, a counter for counting the reproduction clock 103 is provided, and it is monitored whether or not the number of clocks corresponding to a predetermined monitoring period is reached. Also, the number of clocks cs at the time of the last input shift information pulse
It has a register for storing shift. And S34
When the predetermined monitoring period has been reached, it is checked in S35 whether the integrated value cs0 of the shift information pulse in the up / down counter is equal to or greater than the threshold value Css.
If this is the case, the average shift interval value during the main monitoring period is obtained by dividing the number of clocks cshift by the integrated value cs0 of the shift information pulse, and this is trshif in S36.
Let it be t. Thus, the monitoring period ends at S37, and each counter value is reset.

When the count value of the reproduction clock reaches the above monitoring period, the integrated value cs0 of the shift information pulse is obtained.
Is less than the threshold value Css, the monitoring period is extended in S45, and when the number of clocks reaches, for example, twice, the integrated value cs0 is checked again. Here, if it is not less than Css, the average shift interval is calculated, and if it is less than Css, the monitoring period is further extended. However, a limit is set on the number of extensions, and in S44, the count value of the reproduction clock is the maximum value cm.
ax. When the monitoring period is extended to the maximum, if the integrated value cs0 is not 0, similarly to the above,
The average shift interval is calculated, and if it is 0 in S37, 0 is set to t.
Provided as rshift. The calculated value of the average shift interval during the monitoring period calculated by the above procedure is sent to the shift interval averaging means 202.

The shift interval averaging means 202 further averages the average shift interval over the monitoring period. The calculation is
With the new shift interval value, the shift interval control maximum value cma
S3 is to take the difference from x, and also to take the difference from cmax in the same way, and to average the differences.
9 is performed. When calculating this difference, the sign (+) of the shift direction s1 of the new shift interval and the shift direction r1 of the average value
Also consider 1 or -1). However, if the average shift interval is 0, the difference is also 0. At the time of calculation, a coefficient Na that weights the average value up to the previous time is set as S40.

After calculating the average of the differences, the sign (+/−) information is stored, and this is set as r1. afterwards,
In S41, the difference from the cmax is again calculated based on the difference value from which the code has been removed, and the result is set as a new shift interval value.
Then, in S42, the average shift interval and the shift direction, which are the calculation results, are sent to the shift request generation means 203.

The shift request generation means 203 counts the number of reproduction clocks from the time when the previous shift information pulse was generated, and this count value is used as the shift interval averaging means 202.
When the average of the shift intervals from the shift direction is reached, a secondary shift request pulse of +1 or -1 is generated according to the shift direction information. Then, at the same time when the secondary shift request pulse is generated, the count value of the reproduction clock is reset.

The relationship between the shift interval value and the frequency deviation is the same as in the first embodiment, that is, as shown in FIG. It should be averaged over frequency, but for that, the reciprocal must be found and averaged. However, the reciprocal calculation takes a long time and is approximated as kT. In other words, by taking the difference from the maximum count value of the interval value, the numerical value of the smaller interval value is increased so that the correction is correctly performed.

A phase change diagram for explaining the operation of the present embodiment is shown, for example, in the same manner as FIG. In the present embodiment, since the result of smoothing the phase difference by the phase comparing means by the filter directly leads to the phase shift, a phase shift at the time of initial data input is likely to occur, and the control to eliminate the phase difference with the data quickly is performed. Works. For this reason, the phase difference quickly decreases as shown in the figure. Further, during the steady operation, the secondary shift request pulse by the shift interval control means is periodically generated even during the burst, so that the phase shift hardly occurs even in the period where the data change point is scarce. Further, since the shift interval control is performed based on the history of all the shift information, it is hardly affected by the phase noise in the input data.

Embodiment 10 FIG. In the present embodiment, the information to be integrated as the shift information in the shift interval calculating means in the ninth embodiment is only the shift request pulse from the filter. The configuration of the digital phase-locked loop of this embodiment and the configuration of shift interval control means 110j are the same as those in FIGS. FIG. 17 shows a flowchart of the shift interval averaging. 16 is different from FIG. 16 in that the target to be integrated as the shift information is not all the shift information, but only the phase difference shift information 208 from the filter 105. The only difference is that the frequency division ratio is determined based on only the phase difference shift information 208 and the secondary shift request pulse 209b from the shift interval control means 110c during the burst pause. Other configurations and operations are the same as those of the ninth embodiment.

The principle of approximating the frequency average with the shift interval value in the present embodiment is the same as that described in the first embodiment with reference to FIG. However, in the present embodiment, only the phase difference shift information by the filter based on the phase difference between the input signal and the reproduced clock is used as a reference when performing the shift interval control. On the other hand, in the first embodiment, , And the shift request pulse by the filter is used as a reference when performing the shift interval control in the next period. For this reason, the present embodiment is more susceptible to the phase fluctuation of the input data and, on the other hand, more easily follows the frequency fluctuation. Therefore, when the frequency at the source of the input signal is stable and the phase fluctuation due to noise or the like is large at the input of the digital phase locked loop, the ninth embodiment is suitable. This embodiment is suitable when the input is not stable and the phase fluctuation due to noise or the like is small at the input of the digital phase locked loop.

Embodiment 11 FIG. In the present embodiment, instead of the filters in the ninth and tenth embodiments, the phase difference between the input signal and the reproduced clock is sampled a plurality of times, and the median of the maximum and the minimum of the phase difference is output as a phase difference detection signal. It is a filter. The configuration of the digital phase-locked loop of this embodiment and the configuration of shift interval control means 110k are the same as those shown in FIGS. FIG. 18 is a flowchart of the phase difference information smoothing by the filter according to the present embodiment.
Shown in

The operation of the filter according to the present embodiment will be described with reference to FIG.
It will be described based on. However, the operations of S71 and S72 are as follows.
This is due to the phase comparison means 104. Input data 10
The fineness of the classification when classifying the phase difference between 1 and the reproduced clock 103 into multi-values is determined by the ratio between the frequency of the input signal and the frequency of the original clock. For example, it is assumed that quantization is performed from −Pd to + Pd using a natural number Pd. Filter 1
In step S7, the quantized phase difference is input, and the change point counter is incremented by one for each phase comparison (S7).
4) Until counting up to the set value PSC, S7
At 5, the maximum and minimum values of the phase difference input so far are stored. However, if the phase difference is larger than the set value Pdl in S73, the phase difference information is immediately set as + N in S82.
s or -Ns is output depending on whether the phase difference is positive or negative.
Resets the change point counter.

If the phase difference is smaller than Pdl in S73, the phase difference information is not output until the change point counter reaches the PSC (S81). When the change point counter reaches the PSC in S76, the maximum / minimum median value of the phase difference stored so far is calculated as an integer in S77. here,
When the difference between the maximum and the minimum is an odd number, there are two candidates for the median. In this case, a candidate closer to the phase difference inputted last is selected. Next, in S78, phase difference information is output from the calculated median. Here, in the early stage of the pull-in, the median value is used as the phase difference information as it is, and in the following normal times, if the median value is positive, +1 is used, and if it is negative, -1 is used as the phase difference information. Then, in S80, the change point counter is reset.

The set value PSC is determined according to the characteristics of the phase fluctuation of the input signal. For example, when a signal having a large code distortion is input, the phase of the change point of the input signal has a rising delay and a falling falling. Or, conversely, the rise is advanced and the fall is delayed. In this case, even if the phase difference between the input signal and the reproduced clock is 0 on average, the result of the phase comparison advances every time and repeats the delay. Therefore, if an even value is set as the PSC, the true phase difference can be recognized without being affected by code distortion. In practice, this adds phase noise from another source,
Although it is necessary to determine the value in consideration of these factors as well, when the influence of code distortion is large, the effect of smoothing the phase difference information by the smoothing means of the present embodiment is large. Also, in order to enhance the effect on the high-speed pull-in and the steady-state stability, it is possible to adopt a configuration in which the value of the PSC is switched at the normal time as the pull-in initial stage. For the set values Pdl and Ns, if the followability is also increased due to the characteristics of the phase fluctuation of the input signal, Pd
To decrease l and increase Ns to increase suppression, Pd
Set l to be large and Ns to be small. Further, the switching between the initial pull-in and the normal pull-in is set earlier when the initial frequency deviation is expected to be large, and earlier when the operation starts from a place where the frequency deviation is small.

[0065]

According to the present invention, as described above, the shift generation requesting means requests to perform the predetermined shift control at the predetermined intervals, so that even if the data input is not completed (burst pause), the input data is not transmitted. There is an effect that a reproduced clock synchronized with the frequency and the phase can be generated.

Furthermore, since the shift interval is determined by averaging the phase difference information, a reproduced clock can be generated based on the average interval value up to that point in the data input portion (during burst).

Further, since weighting is performed at the time of averaging, there is an effect that the influence of the immediately preceding phase difference information can be reduced and a reproduced clock can be generated.

Further, since the weight is changed depending on the shift direction or the number of times of averaging, the effect of increasing the convergence speed is added.

Further, since data that adversely affects the shift interval is removed, an effect that a desired interval value can be quickly converged is added.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a digital phase locked loop circuit according to a first embodiment of the present invention.

FIG. 2 is a detailed configuration diagram of a shift control unit of FIG.

FIG. 3 is an operation flowchart of the shift interval averaging means of FIG. 2;

FIG. 4 is a diagram showing a relationship between a frequency deviation and a shift interval value by an input phase difference information pulse.

FIG. 5 is a diagram showing an example of a phase change by the digital phase locked loop according to the first embodiment.

FIG. 6 is a configuration diagram of a digital phase locked loop according to a second embodiment of the present invention.

FIG. 7 is a detailed configuration diagram of a shift control unit of FIG. 6;

8 is an operation flowchart of the shift interval averaging means of FIG. 7;

FIG. 9 is a diagram illustrating an example of a phase change by the digital phase locked loop according to the second embodiment.

FIG. 10 is an operation example diagram in Embodiment 3 of the present invention.

FIG. 11 is another operation example diagram in the third embodiment.

FIG. 12 is an operation flowchart of shift interval averaging in Embodiment 4 of the present invention.

FIG. 13 is an operation example diagram in Embodiment 6 of the present invention.

FIG. 14 is an operation example diagram according to the seventh embodiment of the present invention.

FIG. 15 is a detailed configuration diagram of shift interval control means according to Embodiment 9 of the present invention.

FIG. 16 is an operation flowchart of a shift interval averaging unit according to the ninth embodiment.

FIG. 17 is an operation flowchart of a shift interval averaging unit according to the tenth embodiment.

FIG. 18 is an operation flowchart of the filter in the eleventh embodiment.

FIG. 19 is a configuration diagram of a conventional digital phase locked loop circuit.

FIG. 20 is an explanatory diagram showing a general format of burst data.

FIG. 21 is a diagram illustrating the operation of a conventional digital phase locked loop circuit.

[Explanation of symbols]

100 clock recovery circuit, 101 input data, 10
2 identification data, 103 reproduction clock, 104 phase comparison means, 105 filter, 106 shift control means, 107 original clock generation means, 108 frequency division means, 109 data identification means, 110, 110b, 11
0d, 110e, 110f, 110g, 110h, 11
0i, 110j, 110k shift interval control means, 11
1 frame phase information, 112 input data disconnection information, 2
01 shift interval counting means, 202 shift interval averaging means, 203 shift request generating means, 204 clock number counting means, 205 phase difference integrating means, 206
Reproduction clock, 207 Phase difference information, 208 Phase difference shift information, 209 shift request, 209b Secondary shift request, 215 Shift interval calculation means.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Hiroshi Ichigase, 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. (72) Shinya Makino 2-2-2 Marunouchi, Chiyoda-ku, Tokyo No. 3 Mitsubishi Electric Corporation F-term (reference) 5J106 AA05 CC03 CC21 CC53 DD23 GG09 HH02 KK05 5K047 AA12 GG14 KK02 KK05 MM33 MM48 MM55 MM56 MM60 MM63

Claims (13)

[Claims] 1. A method for extracting a frequency and a phase in a digital input signal, comparing the phase with the output of a reproduced clock, and performing feedback so as to add an increase / decrease shift amount to an original clock unique to the circuit based on a phase difference of the comparison result. In the above-mentioned configuration, a shift request generating means for generating a predetermined amount of shift after a predetermined time is provided in the feedback control loop, wherein the digital input signal is cut off, When the phase information is no longer obtained, the predetermined amount of shift is added to the time determined by the shift request generating means, and feedback control is performed. 2. A phase difference integrating means for detecting whether a phase difference between a digital input signal and an output reproduced clock exceeds a threshold value, an average time until the threshold value exceeds the threshold value detected by the phase difference integrating means, and a direction of increase / decrease. Shift interval averaging means for calculating and storing the shift amount. The shift request generating means generates the shift amount in the increasing / decreasing direction for storing the shift amount to be stored when the time stored by the shift interval averaging means has elapsed, and performs feedback control. 2. The digital phase-locked loop according to claim 1, wherein: 3. The shift interval averaging unit requests the shift request unit to generate a shift amount every time the average time elapses without correcting the average time when the phase difference obtained by integrating the specified time is small. 3. The digital phase locked loop circuit according to claim 2, wherein: 4. When the phase difference is large, the shift interval averaging means obtains an approximate frequency from the time until the threshold value is exceeded each time, averages the obtained approximate frequencies to obtain an average frequency, 3. The digital phase-locked loop according to claim 2, wherein an approximate average time is obtained from the obtained average frequency. 5. The shift interval averaging means, when the phase difference is large, obtains an approximate frequency from the time until the threshold value is exceeded each time, and averages the obtained approximate frequency using a weighting coefficient. 3. The digital phase-locked loop according to claim 2, wherein a frequency is obtained, and an approximate average time is obtained from the obtained average frequency. 6. When the phase difference is large, the shift interval averaging means obtains an approximate frequency from the time until the threshold value is exceeded each time, and averages the obtained approximate frequency by using a weighting coefficient. 3. The digital phase-locked loop according to claim 2, wherein a frequency is obtained, an approximate average time is obtained from the obtained average frequency, and a weight coefficient is changed according to a shift direction or an averaging count. 7. After detecting a phase difference between a digital input signal and an output recovered clock, a low-pass digital filter and a phase difference detection signal exceeding a set threshold value of the low-pass digital filter are shifted as shift information. A shift interval counting means for calculating an interval time; and a shift interval averaging means for calculating and storing a shift interval time average and a direction detected by the shift interval counting means, so that a phase difference is large in a period in which a digital input signal is obtained. 2. The method according to claim 1, wherein the shift request generating means generates a shift amount in a direction of increasing or decreasing the stored shift amount after a lapse of time stored by the shift interval averaging means, and performs feedback control. A digital phase-locked loop according to any of the preceding claims. 8. The shift interval averaging means, when the phase difference is large, averages the time until the threshold value is exceeded each time using a weighting coefficient to obtain an average time. The digital phase-locked loop according to claim 7. 9. The shift interval averaging means is characterized in that a phase difference is 0 and a time during which feedback control is performed by the shift request generating means is stored as an initial averaging time to be stored first. A digital phase-locked loop according to claim 7. 10. An assumed value minimum interval time is set when calculating the average time of the shift interval, and the shift interval averaging means sets a short shift which is equal to or less than the assumed value minimum interval time when the average time is first stored. 8. The digital phase-locked loop according to claim 7, wherein the average input time is obtained and stored without the interval input. 11. When performing a feedback control to add an increase / decrease shift amount, during a period in which a digital input signal is obtained, a shift request generated by a shift request generator is ignored and a low-pass digital filter is set. 8. A digital phase-locked loop according to claim 7, wherein a feedback control for adding said increase / decrease shift amount is performed by using a phase difference detection signal exceeding a threshold value as a shift request. 12. After detecting a phase difference between a digital input signal and an output recovered clock, a low-pass digital filter and a phase difference detection signal exceeding a set threshold value of the low-pass digital filter are shifted as shift information. A shift interval counting means for calculating an interval time; and a shift interval averaging means for calculating and storing a shift interval time average and a direction detected by the shift interval counting means, wherein the low-pass digital filter includes: The phase difference from the reproduction clock is sampled a plurality of times, and the median of the maximum value and the minimum value is output as a filtered value. A shift amount to be stored is generated in an increasing / decreasing direction and feedback control is performed. Digital phase synchronizing circuit according to claim 1. 13. A method of extracting a frequency and a phase in a digital input signal, comparing the phase with a reproduced clock of an output, and adding an increase / decrease shift amount to an original clock unique to the circuit based on a phase difference of the comparison result. In the feedback control configuration, a predetermined amount of increase / decrease shift is requested in the feedback loop after a predetermined time, and when the digital input signal is cut off and phase information of the input signal cannot be obtained, it is stored. Shift request generating means for requesting the addition of the average increase / decrease shift amount for each average time; and shift control means for adding the increase / decrease shift amount based on the request of the shift request generation means and providing a reproduction clock before frequency division. A clock recovery circuit.