JP2000031818A - Delay circuit and PLL circuit having the same - Google Patents

Abstract

(57) [Problem] To provide a delay circuit capable of accurately delaying an externally input signal. An input clock and an input signal are compared in phase by a phase frequency comparator, and a voltage corresponding to the phase difference is output to a charge pump and a low-pass filter. The voltage input to the charge pump and the low-pass filter 6 is charged and discharged, and only the low-pass is passed to the voltage-controlled oscillator 8. The voltage control oscillator 8 controls the oscillation frequency of the input signal according to the output signal of the charge pump and the low-pass filter 6 and feeds it back to the phase frequency comparator 4. A delay unit 10 including substantially the same circuit element as the voltage controlled oscillator 8 receives the output signal of the charge pump and the low-pass filter 6 as a reference clock, and delays a data signal input to the delay unit 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit for delaying an input signal and a phase locked loop (PLL) having the same.
Circuit).

[0002]

2. Description of the Related Art Conventionally, in a delay circuit, an FLL (Frequency Lock Loop) has been used in order to suppress variations in delay time.
) It is common to use a circuit. The case where this FLL circuit is used for a PLL (Phase Locked Loop) circuit will be described below.

FIG. 7 is an example showing a configuration of a conventional delay circuit and a PLL circuit connected to the delay circuit. As shown in FIG. 7, a reference clock is input to the FLL circuit 100, and the FLL circuit 100 generates a control clock based on the reference clock, and
Output to The delay circuit 102 receives a data signal from the outside and the control clock, and outputs the generated delay clock to a phase frequency comparator (PF) in the PLL circuit 104.
D: Phase Frequency Detector) 106.

As shown in FIG. 7, the PLL circuit 104 includes a phase frequency comparator 106, a charge pump (CH)
P), a low-pass filter (LPF) 108, and a voltage controlled oscillator (VCO: Voltage Controlled Oscillator) 1
10.

[0005] The PLL circuit 104 operates as follows. The delayed clock output from the delay circuit 102 is compared with an output clock oscillated by the voltage controlled oscillator 110 in the PLL circuit 104 by a phase frequency comparator 106, and a voltage corresponding to the phase difference is supplied to a charge pump (CH).
P) 108, and the voltage is smoothed by a low-pass filter (LPF) 108 that passes only the low frequency band. Then, the output clock is synchronized with the delay clock by controlling the oscillation frequency of the output clock by the voltage controlled oscillator 110 according to the smoothed voltage. In such a delay circuit used for the PLL circuit 104, it is necessary to accurately delay the time by a half of the period of the reference clock.

[0006]

However, the delay circuits FLL circuit 100 and PLL circuit 104
Is relatively shallow, it is difficult to obtain a waveform accurately delayed by half the period of the reference clock.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has been made by using, as a part of a delay circuit, a circuit having substantially the same configuration as a voltage-controlled oscillator that controls an oscillation frequency according to an input voltage. It is another object of the present invention to provide a delay circuit capable of accurately delaying an input signal input from the outside.

[0008]

In order to achieve the above object, a delay circuit according to the present invention comprises:
Phase comparing means for comparing the phase of the second input signal and outputting a voltage corresponding to the phase difference, filter means for passing only a low band of the output voltage of the phase comparing means, and output signal of the filter means And a voltage-controlled oscillating means for controlling the oscillation frequency of the second input signal in accordance with the control signal and feeding back to the phase comparing means, and a circuit element substantially identical to the voltage-controlled oscillating means. Delay means for receiving a signal and delaying an input third input signal with reference to the output signal.

A PLL circuit according to the present invention compares a phase of input first and second input signals and outputs a voltage corresponding to the phase difference, and an output voltage of the phase comparator. Filter means for passing only the low frequency band of the signal, voltage-controlled oscillation means for controlling the oscillation frequency of the second input signal in accordance with the output signal of the filter means, and feedback to the phase comparison means, Delay means for receiving an output signal of the filter means, delaying a third input signal to be inputted with reference to the output signal, and a signal delayed by the delay means. And a phase synchronizing means for receiving the clock as a reference clock and performing phase synchronization.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. A delay circuit, which is a semiconductor memory device according to an embodiment of the present invention, is connected to a PLL (Phase
The case where the present invention is used in the input side circuit of a Locked Loop circuit will be described below.

FIG. 1 is a diagram showing a configuration of a delay circuit and a PLL circuit according to an embodiment of the present invention. As shown in FIG. 1, the delay circuit 2 includes a phase frequency comparator (PFD:
Phase Frequency Detector 4, charge pump (CH
P: Charge Pump) and low-pass filter (LPF: Lo)
w Pass Filter) 6, Reference voltage controlled oscillator (VC
O: Voltage Controlled Oscillator) 8 and a delay unit 10.

Further, the PLL circuit 12 receiving the output of the delay unit 10 includes a phase frequency comparator (PFD) 14,
Charge pump (CHP) and low-pass filter (LP
F) 16 and a voltage controlled oscillator (VCO) 18.

The phase frequency comparators (PFD) 4, 14
Compares the phases of two input clocks, converts the phase difference into a voltage, and outputs the voltage. The charge pump (CHP) and the low-pass filter (LPF) 6, 16
Supplies a charge according to the input voltage to a charge pump (C
HP), and smoothes the voltage with a low-pass filter (LPF) that passes only the low frequency band. Also,
The voltage controlled oscillators (VCOs) 8, 18 are oscillators that change the oscillation frequency according to the input voltage.

Next, the operation of the delay circuit and the PLL circuit according to the embodiment of the present invention will be described. First, an external reference clock and a control clock from a reference voltage control oscillator 8 are input to the phase frequency comparator 4. The phase of the reference clock and the control clock are compared by a phase frequency comparator 4, and a voltage corresponding to the phase difference is supplied to a charge pump (CHP) and a low-pass filter (LPF) 6.
Is output to

The voltage input to the charge pump (CHP) and the low-pass filter (LPF) 6 is charged and discharged by the charge pump, and is further smoothed by the low-pass filter that passes only the low band. The smoothed voltage is input to the reference voltage-controlled oscillator 8, and the voltage-controlled oscillator 8 controls and outputs the output control clock oscillation frequency according to the voltage. FIG. 2 shows a circuit configuration of the voltage controlled oscillator 8. As shown in FIG.
The voltage controlled oscillator 8 includes transistors Q1 to Q16, capacitors C1 and C2, resistors R1 to R7, and constant current sources I1 to I
7 and a voltage power supply Vcc.

As described above, the phase frequency comparator 4 compares the phases of the reference clock and the control clock every cycle, generates a voltage proportional to the phase difference, and reduces the phase difference between the two. The oscillation frequency of the voltage controlled oscillator 8 is controlled. This operation is continued until the frequency and phase of the reference clock and control clock completely match. Then, both the frequency and the phase of the control clock are synchronized with the frequency and the phase of the reference clock.

Here, the low-pass filter (LPF)
6 is input to the delay unit 10. This output signal is changed to a signal delayed by a half cycle by the delay unit 10 and output as a delayed clock. FIG. 3 shows a circuit configuration of the delay unit 10. As shown in FIG. 3, the delay unit 10 includes transistors Q21 to Q37, capacitors C21 and C22, resistors R21 to R28, constant current sources I21 to I29, and a voltage power supply Vcc. The S line shown in FIG. 2 and the S line shown in FIG. 3 are connected. As shown in FIGS. 2 and 3, the voltage controlled oscillator 8 and the delay unit 10 have substantially the same circuit configuration.

Further, the delayed clock and the output clock from the voltage controlled oscillator 18 are input to the phase frequency comparator 14 in the PLL circuit 12. The phase of the delayed clock and the output clock are compared by the phase frequency comparator 14, and a voltage corresponding to the phase difference is supplied to the charge pump (C).
HP) and a low-pass filter (LPF) 16.

The voltage input to the charge pump (CHP) and the low-pass filter (LPF) 16 is charged and discharged by the charge pump, and further smoothed by a low-pass filter that passes only a low frequency band. The smoothed voltage is input to a voltage controlled oscillator 18, which controls the oscillation frequency of the output clock, which is the output thereof, according to the voltage and outputs it.

As described above, the phase frequency comparator 14 compares the phases of the delay clock and the output clock on a cycle-by-cycle basis, and generates a voltage proportional to the phase difference. The oscillation frequency of the control oscillator 18 is controlled. This operation is continued until the frequency and phase of the delay clock and the output clock completely match.
Then, both the frequency and the phase of the output clock output from the voltage controlled oscillator 18 are synchronized with the frequency and the phase of the delay clock output from the delay unit 10.

FIGS. 4 to 6 are timing charts showing the input and output of the delay unit 10 when the input current to the voltage controlled oscillator 8 is changed. FIG. 4 shows a voltage controlled oscillator 8
5 shows a case where the input current to the voltage controlled oscillator 8 is 750 μA, and FIG. 6 shows a case where the input current to the voltage controlled oscillator 8 is 1 mA (1000 μA). A to G in FIGS. 4 to 6 indicate waveforms at locations indicated by A to G in FIGS. 2 and 3. A and B are input waveforms to the delay unit 10, C and D are output waveforms from the delay unit 10, E is an output waveform from the voltage controlled oscillator 8, F is a discharge voltage waveform of the delay unit 10, and G is a voltage controlled oscillator. 8 shows respective discharge voltage waveforms. As can be seen from these figures, the delay times T1, T2, and T3 by the delay unit 10 are half the cycle of the signal waveform output from the respective voltage controlled oscillators 8.

As described above, according to the embodiment of the present invention, by using, as a part of the delay circuit, a circuit configured almost identically to the voltage-controlled oscillator that controls the oscillation frequency according to the input voltage, It is possible to accurately delay an input signal input from the outside.

Further, when the delay circuit of this embodiment is used as an input circuit of a PLL circuit,
Since the relative relationship with the LL circuit becomes stronger, a clock that is more accurately delayed can be supplied to the PLL circuit.

[0024]

As described above, according to the present invention, a circuit having substantially the same configuration as a voltage controlled oscillator for controlling an oscillation frequency in accordance with an input voltage is used for a part of a delay circuit, so that it can be externally provided. A delay circuit capable of accurately delaying an input signal to be input can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a delay circuit and a PLL according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating a configuration of a circuit.

FIG. 2 is a circuit diagram showing a configuration of a voltage controlled oscillator in the delay circuit.

FIG. 3 is a circuit diagram showing a configuration of a delay unit in the delay circuit.

FIG. 4 is a timing chart showing an input waveform and an output waveform of the delay unit when an input current to the voltage controlled oscillator is changed.

FIG. 5 is a timing chart showing an input waveform and an output waveform of the delay unit when an input current to the voltage controlled oscillator is changed.

FIG. 6 is a timing chart showing an input waveform and an output waveform of the delay unit when an input current to the voltage controlled oscillator is changed.

FIG. 7 is an example showing a configuration of a conventional delay circuit and a PLL circuit connected to the delay circuit.

[Explanation of symbols]

2. Delay circuit 4. Phase frequency detector 6. Charge pump and low pass filter 8. Voltage controlled oscillator (Voltage Controlled Oscillato)
r) 10: delay unit 12: PLL circuit 14: phase frequency detector (Phase Frequency Detector) 16: charge pump (Charge Pump) and low-pass filter (Low Pass Filter) 18: voltage controlled oscillator (Voltage Controlled Oscillat)
or) Q1 to Q16, Q21 to Q37 ... transistors C1, C2, C21, C22 ... capacitors R1 to R7, R21 to R28 ... resistors I1 to I7, I21 to I29 ... constant current source Vcc ... voltage power supply

Claims (2)

[Claims] 1. A phase comparison means for comparing phases of input first and second input signals and outputting a voltage corresponding to the phase difference, and passing only a low range of an output voltage of the phase comparison means. Filter means for controlling, an oscillation frequency of the second input signal in accordance with an output signal of the filter means, a voltage controlled oscillation means for feeding back to the phase comparison means, and a circuit substantially the same as the voltage controlled oscillation means And delay means for receiving an output signal of the filter means and delaying an input third input signal with reference to the output signal. 2. A phase comparing means for comparing the phases of input first and second input signals and outputting a voltage corresponding to the phase difference, and passing only a low range of an output voltage of the phase comparing means. Filter means for controlling, an oscillation frequency of the second input signal in accordance with an output signal of the filter means, a voltage controlled oscillation means for feeding back to the phase comparison means, and a circuit substantially the same as the voltage controlled oscillation means A delay unit configured to receive an output signal of the filter unit, delay the input third input signal based on the output signal, and receive the signal delayed by the delay unit as a reference clock, and PLL (Phase Locked Loo) comprising:
p) circuit.