JP2000031452A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with which reliability is increased by avoiding damages to silicon wafers and miniaturization can be realized, and to provide a method for manufacturing the same. SOLUTION: Since an interlayer film 3 is formed in such a way that it covers the proximity of a scribe line 10, the surface of a silicon wafer 2 is not damaged by anisotropic etching for forming aluminum wiring 4 and passivation films 5a and 5b during manufacturing operations. Accordingly, a semiconductor device exhibiting high reliability can be obtained. Also, since a space which is required when the interlayer film 3 near the scribe line 10 is eliminated according to the conventional technology is no longer necessary, the semiconductor device can be miniaturized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device for improving the reliability of the device and realizing the miniaturization of the device and a method for manufacturing the same.

[0002]

2. Description of the Related Art A semiconductor device is sometimes used as an image sensor such as a facsimile or a scanner. In this case, a large number of phototransistors are arranged in a line to constitute an image sensor.

FIG. 6 shows an arrangement of such a phototransistor. For example, 10
A semiconductor chip (11, 12, 13, 14,...) On which about 0 phototransistors (12a, 13a) are arranged is cut out from a silicon wafer, and 20 to 30 semiconductor chips are connected and connected. Configure the sensor.

In order to enhance the reading accuracy, the intervals L1 between the phototransistors 12a and 13a must be arranged at the same interval, and the phototransistors 12 at the connection between the semiconductor chip 12 and the semiconductor chip 13 are required.
The interval L2 between a and 13a needs to be the same as the interval L1. Further, in order to increase the resolution of the read image, it is desirable that the intervals L1 and L2 between the elements are as small as possible.

FIG. 7 is an enlarged sectional view of a connection portion between the semiconductor chip 12 and the semiconductor chip 13. Semiconductor chip 1
Are formed once in a single silicon wafer 2 and then cut along scribe lines 10 to be divided into individual semiconductor chips. A method of manufacturing the conventional semiconductor device shown in FIG. 7 will be described with reference to FIGS. 8 to 10 are enlarged views of the vicinity of the scribe line 10 shown in FIG.

First, the silicon wafer 2 is partially covered with a silicon nitride film, and the surface of the silicon wafer 2 is selectively thermally oxidized to form LOCOS 21, 22, 2 shown in FIG.
3, 24, and 25 are formed, and the silicon nitride film is removed (FIG. 8A). Next, CVD (Chemical Vapor Depositio
An interlayer film 9 (silicon oxide film) is formed on the surface by the method n) (FIG. 8B).

Subsequently, when a predetermined portion of the interlayer film 9 is etched to form a contact hole, the interlayer film 9 near the scribe line 10 is also removed by etching at the same time. In this case, anisotropic etching is used to ensure the accuracy of the size of the contact hole.

That is, the photoresist 2 is formed on the interlayer film 9.
9 is selectively formed, and accelerated gas ions are brought into vertical contact. The material of the interlayer film 9 is knocked out by the impact of the incident ions, and the interlayer film 9 is partially removed.
a and 9b are formed (FIG. 8C). Thereafter, the interlayer film 9a,
The photoresist 29 on 9b is removed.

When forming the interlayer films 9a and 9b, LOC
The regions S4 ′ and S5 ′ covering the sides of the OSs 23 and 24 are formed so as to remain. On the other hand, if anisotropic etching is performed along the edges of the LOCOSs 23 and 24 to form the interlayer films 9a and 9b without leaving the regions S4 'and S5', L
There is a possibility that the OCOSs 23 and 24 are partially etched.

In order to miniaturize semiconductor devices, LOCOS
Since the LOCOS 23 and 24 are formed so as to be extremely fine to the limit, if the LOCOS 23 and 24 are partially etched, it becomes impossible to secure insulation between the elements.
For this reason, the interlayer films 9a and 9b are formed leaving regions S4 'and S5' covering the sides of the LOCOSs 23 and 24 shown in FIG. 8C.

Thereafter, an aluminum layer 4H is formed on the entire surface (FIG. 9A), and a photoresist 27 is formed on the aluminum layer 4H according to a wiring pattern. Then, the aluminum layer 4H is partially removed by etching to obtain a predetermined aluminum wiring 4 (FIG. 9B). In this case, anisotropic etching is used in order to secure the accuracy of the wiring, and the aluminum layer 4H is removed by impact of incident ions.

After forming the aluminum wiring 4, a passivation film 5 (silicon nitride film) is formed on the surface for surface protection (FIG. 10A). And the passivation film 5
Are etched to form holes for bonding pads. When forming the hole of the bonding pad, the passivation film 5 near the scribe line 10 is also removed by etching at the same time.

At this time, anisotropic etching is also used, and the passivation film 5 is partially removed by the impact of ion incidence. Thus, the passivation films 5a and 5b are formed (FIG. 10B), and the photoresist 28 on the passivation films 5a and 5b is removed.

When the passivation films 5a and 5b are formed, a region S2 'covering the sides of the interlayer films 9a and 9b,
It is formed so that the S3 'portion remains. This is the corner 6
(FIGS. 9B and 10A) to cover the aluminum remaining. That is, when the aluminum layer 4H is removed by etching in the steps shown in FIGS.
In some cases, aluminum is not completely removed but remains.

When aluminum is left in the corner portions 6, when cutting the silicon wafer 2 along the scribe line 10, the cutting blade contacts the aluminum and aluminum powder is scattered, and for example, adheres to the bonding pad. Product failure. Therefore, the region S covering the corner portion 6
Passivation films 5a and 5b except for 2 'and S3' portions
To form

After the above-described manufacturing steps, the silicon wafer 2 is cut along the scribe line 10 using a cutting blade, and the individual semiconductor chips 11, 12, 1
Get 3,14 ...

[0017]

The above-described conventional semiconductor device and its manufacturing method have the following problems. FIG.
C, 9B, and 10B, the anisotropic etching using the impact of the incident ions is performed, and the silicon wafer 2 is damaged at this time.

That is, in the steps shown in FIGS. 8C and 9B, the regions S1 ', S2' and S3 '(FIG. 10B) are impacted by ion incidence, and a lattice defect that disturbs the lattice of the silicon wafer 2 occurs. . Further, in the step shown in FIG. 10B, the region S1 ′ is subjected to the impact of ion incidence, causing a lattice defect.

Particularly, in the step of etching the aluminum layer 4H shown in FIG. 9B, the etching selectivity between the aluminum layer 4H and the silicon wafer 2 is small (the difference in etching speed is small). For this reason, it is difficult to control the etching depth, and there is a possibility that over-etching may occur, leading to lattice defects at a deeper portion of the silicon wafer 2.

As described above, problems such as lattice defects occur due to the anisotropic etching. Even in the case of the scribe line 10, if a lattice defect occurs, the operation of the device is affected and the reliability of the device is reduced.

FIG. 1 shows the vicinity of the scribe line 10.
0B, the regions S1 ′, S2 ′, S3 ′, S4 ′,
Since S5 'is located, the element interval L2' shown in FIG. 7 cannot be set small. Since the element interval L1 'and the element interval L2' are set to the same interval as described above, the miniaturization of the entire device is eventually hindered.

Accordingly, an object of the present invention is to provide a semiconductor device capable of improving the reliability of a device by avoiding damage to a silicon wafer and realizing miniaturization of the device, and a method of manufacturing the same.

[0023]

Means for Solving the Problems and Effects of the Invention
In the method of manufacturing a semiconductor device according to the above, when forming the interlayer insulating film on the semiconductor wafer, the interlayer insulating film is formed so as to cover the vicinity of the cutting line on at least one side of the chip region. Then, when forming the protective film over the interlayer insulating film, the protective film is formed so as not to cover the vicinity of the cutting line on at least one side of the chip region. Thereafter, the interlayer insulating film and the semiconductor wafer are cut along the cutting line.

As described above, the interlayer insulating film is formed so as to cover the vicinity of the cutting line on at least one side of the chip region, and the surface of the semiconductor wafer near the cutting line is not exposed. Therefore, it is possible to avoid damage to the semiconductor wafer surface due to impact or the like, and to provide a highly reliable semiconductor device.

Further, since the interlayer insulating film is formed so as to cover the vicinity of the cutting line on at least one side of the chip region, no space is necessary for exposing the vicinity of the cutting line. Therefore, miniaturization of a semiconductor device can be realized.

Further, the protective film is formed so as not to cover the vicinity of the cutting line on at least one side of the chip region. Therefore, when cutting is performed along the cutting line, the protective film does not hinder the cutting, and the efficiency of the manufacturing operation can be increased.

In the method of manufacturing a semiconductor device according to the second aspect, when forming the interlayer insulating film on the semiconductor wafer, the interlayer insulating film is formed so as to cover the vicinity of the cutting line on at least one side of the chip region. Then, a metal forming layer is formed on the interlayer insulating film, and a non-wiring portion of the metal forming layer is removed by anisotropic etching to form a metal wiring.

Further, when forming the protective film on the interlayer insulating film, the protective film is formed so as not to cover the vicinity of the cutting line on at least one side of the chip region, and thereafter the interlayer insulating film is formed along the cutting line. And cutting the semiconductor wafer.

As described above, when forming a metal wiring, a non-wiring portion is removed by anisotropic etching. That is, unlike isotropic etching in which etching progresses isotropically in the vertical direction and the horizontal direction, etching can proceed only in the vertical direction, and an accurate metal wiring can be formed.

Further, the interlayer insulating film is formed so as to cover the vicinity of the cutting line on at least one side of the chip region, and the surface of the semiconductor wafer near the cutting line is not exposed. Therefore, even when anisotropic etching is used when forming the metal wiring, damage to the semiconductor wafer surface due to impact or the like can be avoided, and a highly reliable semiconductor device can be provided.

Further, since the interlayer insulating film is formed so as to cover the vicinity of the cutting line on at least one side of the chip region, no space is required for exposing the vicinity of the cutting line. Therefore, miniaturization of a semiconductor device can be realized.

Further, the protective film is formed so as not to cover the vicinity of the cutting line on at least one side of the chip region. Therefore, when cutting is performed along the cutting line, the protective film does not hinder the cutting, and the efficiency of the manufacturing operation can be increased.

In the semiconductor device according to the third aspect, the surface near at least one edge of the semiconductor chip substrate is:
Since the semiconductor chip substrate is covered with the interlayer insulating film, the surface near the edge of the semiconductor chip substrate is not exposed. The surface of the interlayer insulating film near the edge is not covered with the protective film, so that the surface of the interlayer insulating film is exposed.

As described above, since the surface near at least one edge of the semiconductor chip substrate is covered with the interlayer insulating film, the surface of the semiconductor chip substrate near this edge is not exposed. Therefore, it is possible to prevent the semiconductor chip substrate surface from being damaged by impact or the like, and to provide a highly reliable semiconductor device.

Further, since the surface near at least one edge of the semiconductor chip substrate is covered with the interlayer insulating film, no space is required for exposing the vicinity of the edge. Therefore, miniaturization of a semiconductor device can be realized.

Further, the protective film is formed so as not to cover the surface of the interlayer insulating film near the edge. Therefore,
In the case where a semiconductor device is obtained by cutting along the edge, a semiconductor device with high accuracy can be obtained without the protective film hindering the cutting.

[0037]

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment A first embodiment of a semiconductor device and a method for manufacturing the same according to the present invention will be described with reference to the drawings. FIG. 1 is a side sectional view showing a semiconductor chip according to the present embodiment, and FIG.
FIGS. 3B, 3C, 3A, 3B, 3C, 4A, and 4B are diagrams for explaining the manufacturing process of the semiconductor chip shown in FIG.

An image sensor such as a facsimile or a scanner is configured by arranging a large number of phototransistors in a line. FIG. 6 shows an arrangement of such a phototransistor. In view of the manufacturing efficiency, for example, a semiconductor chip (11, 12, 13, 14,...) On which about 100 phototransistors (12a, 13a) are arranged is once cut out of a silicon wafer, and An image sensor is formed by connecting 30 pieces adjacently.

In order to improve the reading accuracy, the intervals L1 between the phototransistors 12a and 13a need to be arranged at the same interval.
The interval L2 between a and 13a needs to be the same as the interval L1. Further, in order to increase the resolution of the read image, it is desirable that the intervals L1 and L2 between the elements are as small as possible.

FIG. 1 shows a connection portion between the semiconductor chip 12 and the semiconductor chip 13 in this embodiment. The semiconductor chips 11, 12, 13, 14,... Are once formed in a single silicon wafer 2, and then cut along the scribe lines 10 to be divided into individual semiconductor chips.

The silicon wafer 2 is the semiconductor wafer in the present embodiment, and the scribe line 10 is the cutting line in the present embodiment. In the silicon wafer 2, the semiconductor chips 11, 12, 13, 1
4 are formed as chip regions in the present embodiment. Further, the phototransistors 12a and 13a formed in each semiconductor chip are element regions in the present embodiment.

Hereinafter, a method of manufacturing the semiconductor chips 12 and 13 shown in FIG. 1 will be described with reference to FIGS. First, impurities are implanted through a mask formed on the surface of the silicon wafer 2 and 12a, 1a shown in FIG.
A well region 16 is formed near the scribe line 10 shown in FIG. 2 together with the portion 3a (FIG. 2A).

Then, the silicon wafer 2 is partially covered with a silicon nitride film, and the surface of the silicon wafer 2 is selectively thermally oxidized to form the LOCOSs 21 and 22 shown in FIG.
23, 24 and 25 are formed, and the silicon nitride film is removed (FIG. 2B). LOCOS 21, 22, 23, 24, 2
Reference numeral 5 denotes an element isolation region in the present embodiment. The region including the phototransistor 12a and the LOCOS 22 shown in FIG.
The region including 25 is the target region in the present embodiment.

The scribe line 10 is a portion which is finally cut and then joined and arranged, and as described above, the distance L2 between the phototransistors 12a and 13a is changed.
Must be the same as the interval L1 between the other phototransistors. Therefore, the LOCOS 23 and 24 arranged on both sides of the scribe line 10 are different from the other LOCOS 2
It is formed in a size smaller than half of the sizes of 1, 22, and 25.

LOCOS 21, 22, 23, 24, 25
Then, impurities are implanted into the well region 16 shown in FIG. 2 together with the portions 12a and 13a shown in FIG. 1 to form the source / drain regions 17. Since the scribe line 10 is a part to be finally cut, the well region 16 shown in FIG.
The drain region 17 is essentially unnecessary. Therefore, this portion may be masked so that the well region 16 and the source / drain region 17 are not formed.

Subsequently, an interlayer film 3 (silicon oxide film) as an interlayer insulating film is formed on the surface by the CVD method (FIG. 3A). As shown in FIG. 3A, the interlayer film 3 is formed so as to cover the vicinity of the scribe line 10, and a state in which the vicinity of the scribe line 10 is left without being removed as in the conventional semiconductor device (FIG. 8C). The subsequent manufacturing process proceeds.

After the interlayer film 3 is formed, an aluminum layer 4H as a metal forming layer is formed on the entire surface (FIG. 3B), and a photoresist 27 is formed on 4H according to a wiring pattern. Then, the aluminum layer 4H corresponding to the non-wiring portion is removed by etching to obtain a predetermined aluminum wiring 4 (FIG. 4C). The aluminum wiring 4 is the metal wiring in the present embodiment.

In this case, anisotropic etching is used to secure the accuracy of the wiring, and the aluminum layer 4H is removed by impact of incident ions. That is, unlike isotropic etching in which etching progresses isotropically in the vertical and horizontal directions, anisotropic etching allows etching to proceed only in the vertical direction, and forms an accurate aluminum wiring 4. can do. The anisotropic etching in this embodiment includes RIE (Reactive I
on Etching) is used, but other anisotropic etching may be employed.

After the aluminum wiring 4 is formed, a passivation film 5 (silicon nitride film) is formed on the surface for surface protection (FIG. 4A). Then, a predetermined portion of the passivation film 5 is etched to form a hole for a bonding pad. When forming the hole of the bonding pad,
Passivation film 5 near scribe line 10
Is also removed by etching at the same time.

In this embodiment, anisotropic etching is also used for the etching at this time, and the passivation film 5 is partially removed by the impact of ion incidence.
Since fine precision is not required for forming the hole of the bonding pad, isotropic etching can be employed in the step of FIG. 4B. Thus, passivation films 5a and 5b, which are protective films, are formed (FIG. 4B), and the photoresist 28 on the passivation films 5a and 5b is removed.

After the above-described manufacturing steps, the silicon wafer 2 and the interlayer film 3 are cut along the scribe line 10 using a cutting blade, and the individual semiconductor chips 11 and
12, 13, 14 ... are obtained. Since the passivation film 5 in the vicinity of the scribe line 10 is removed, the passivation film 5 does not hinder cutting, and the efficiency of the manufacturing operation can be increased.

The cut semiconductor chips 11 and 1
The substrate portions 2, 13, 14,... (The silicon wafer 2 portions) are the semiconductor chip substrates in the present embodiment, and the portions corresponding to the scribe lines 10 at the cut portions are the edge portions of the semiconductor chip substrates.

The passivation film 5 shown in FIG.
a and 5b are formed, the regions S2 and L are spaced from the end of the LOCOS 23 to the end of the passivation film 5a.
It is formed so as to secure an interval region S3 from the end of the OCOS 24 to the end of the passivation film 5b. Region S2,
By securing S3, scribe line 1
When cutting along zero, it is possible to reduce the risk that the LOCOSs 23 and 24 will be partially cut due to misalignment of the cutting location.

For miniaturization of semiconductor devices, LOCOS
Since the LOCOS 23 and 24 are finely set to the limit, if the LOCOS 23 and 24 are partially cut,
Insulation between elements cannot be ensured. Therefore, by securing the regions S2 and S3, a more reliable semiconductor device can be obtained.

As described above, the interlayer film 3 is formed so as to cover the vicinity of the scribe line 10, and the surface of the silicon wafer 2 near the scribe line 10 is not exposed. Therefore, when the aluminum wiring 4 and the passivation films 5a and 5b are formed, damage to the surface of the silicon wafer 2 due to impact or the like can be avoided even though anisotropic etching is used. An apparatus can be provided.

The interlayer film 3 is formed by the scribe line 10
Since it is formed so as to cover the vicinity, the space necessary to expose the vicinity of the scribe line 10, for example, the regions S4 'and S5' (FIG. 7) in the related art is unnecessary. For this reason, the element interval L2 shown in FIG. 1 can be set small.

Then, the phototransistors 12a and 13
Since the interval L2 of a is configured to be the same as the interval L1 of the other phototransistors, it is possible to set the element interval L1 small by reducing the element interval L2, thereby realizing miniaturization of the semiconductor device. Can be. With such miniaturization of a semiconductor device, the degree of integration of elements can be increased, and the resolution of an image read by an image sensor can be increased.

2. Second Embodiment Next, a second embodiment of a semiconductor device and a method for manufacturing the same according to the present invention will be described with reference to FIG. FIG. 5 is a diagram corresponding to FIG. 4B described in detail in the first embodiment.

As shown in FIG. 5, the surface of the silicon wafer 2 has a region S shown in the first embodiment.
2, S3 is not formed. That is, LOCOS2
The three ends and the end of the passivation film 5a are located substantially on the same line, and the end of the LOCOS 24 and the end of the passivation film 5b are located substantially on the same line. This can be obtained by forming the end of the photoresist 28 shown in FIG. 4B in the first embodiment on the same line as the ends of the LOCOS 23 and 24, and performing etching.

Thus, the element interval L2 shown in FIG. 1 can be set smaller. By reducing the element spacing L2, the element spacing L1 can be set small, and miniaturization of the semiconductor device can be realized. With such miniaturization of a semiconductor device, the degree of integration of elements can be increased, and the resolution of an image read by an image sensor can be further increased.

The other parts are the same as those in the first embodiment, and the same reference numerals are given to the respective parts as in the first embodiment, and the detailed description is omitted. The manufacturing process is the same as in the first embodiment.

3. Other Embodiments The semiconductor device and the method of manufacturing the same according to the present invention are not limited to those described in the above embodiments. For example, in each of the above embodiments, a semiconductor device including a phototransistor for forming an image sensor has been described, but the present invention is not limited to this.

In each of the above embodiments, the region including the phototransistor 12a and the LOCOS 22 shown in FIG.
The region including the LOCOS 22 and the LOCOS 22 was not formed, but the phototransistor 1 was not formed.
The target region may be only the 2a or the phototransistor 13a.

[Brief description of the drawings]

FIG. 1 is a side sectional view showing a semiconductor chip which is a first embodiment of a semiconductor device according to the present invention.

FIGS. 2A, 2B, and 2C are diagrams for explaining a manufacturing process of the semiconductor chip shown in FIG.
It is an enlarged view of the vicinity.

FIGS. 3A, 3B, and 3C are diagrams for explaining a manufacturing process of the semiconductor chip shown in FIG.
It is an enlarged view of the vicinity.

FIGS. 4A and 4B are views for explaining a manufacturing process of the semiconductor chip shown in FIG. 1, and are enlarged views in the vicinity of a scribe line 10. FIGS.

FIG. 5 is a side sectional view showing a semiconductor chip which is a second embodiment of the semiconductor device according to the present invention, and is an enlarged view near a scribe line 10;

FIG. 6 is a plan view of the image sensor.

FIG. 7 is a side sectional view showing a conventional semiconductor chip.

FIGS. 8A, 8B, and 8C are diagrams for explaining a manufacturing process of the semiconductor chip shown in FIG. 7;
It is an enlarged view of the vicinity.

9A and 9B are views for explaining a manufacturing process of the semiconductor chip shown in FIG. 7, and are enlarged views in the vicinity of the scribe line 10. FIG.

FIGS. 10A and 10B are views for explaining a manufacturing process of the semiconductor chip shown in FIG. 7, and are enlarged views in the vicinity of the scribe line 10. FIGS.

[Explanation of symbols]

 2 ... Silicon wafer 4 ... Aluminum wiring 4H ... Aluminum layer 5,5a, 5b ... Passivation film 10 ... Scribe line 12a, 13a ... ..Phototransistors 21, 22, 23, 24, 25... LOCOS

Claims (3)

[Claims] A step of forming a target region having at least an element region for each chip region on a surface of the semiconductor wafer divided into a plurality of chip regions by a cutting line; and forming an interlayer insulating film on an upper portion of the semiconductor wafer. Forming a film, covering the vicinity of a cutting line on at least one side of the chip region, forming an interlayer insulating film, forming a protective film on the interlayer insulating film, A method of manufacturing a semiconductor device, comprising: forming a protective film so as not to cover the vicinity of the cutting line on at least one side; and cutting the interlayer insulating film and the semiconductor wafer along the cutting line. 2. A step of forming a plurality of element isolation regions for each chip region on a surface of a semiconductor wafer divided so as to form a plurality of chip regions by a cutting line; Forming an element region so as to be located between the element isolation regions in the semiconductor device; and forming an interlayer insulating film on the semiconductor wafer, wherein the interlayer is formed so as to cover the vicinity of the cutting line on at least one side of the chip region. Forming an insulating film; forming a metal forming layer on the interlayer insulating film; removing non-wiring portions of the metal forming layer by anisotropic etching to form a metal wiring; protecting on the interlayer insulating film Forming a film, wherein a protective film is formed so as not to cover the vicinity of the cutting line on at least one side of a chip region. Forming a semiconductor device, and cutting the interlayer insulating film and the semiconductor wafer along a cutting line. 3. An object region formed on a surface of a semiconductor chip substrate, the object region having at least an element region, an interlayer insulating film formed on an upper portion of the semiconductor chip substrate, and an interlayer insulating film formed on the interlayer insulating film. In the semiconductor device having the protective film, the surface near at least one edge of the semiconductor chip substrate is covered with the interlayer insulating film, so that the surface near the edge of the semiconductor chip substrate is exposed. The surface of the interlayer insulating film near the edge is not covered with the protective film, so that the surface of the interlayer insulating film is exposed.