JP2000029859A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To generate an interrupt when the output signal level of a microprocessor is different from the output level due to destruction of an output terminal, etc. Provided is a semiconductor integrated circuit capable of appropriately taking action based on the above. SOLUTION: The semiconductor integrated circuit includes a microprocessor 38, and outputs an output of an output data buffer 31 to an output terminal 33 via an output buffer 32. The semiconductor integrated circuit includes a signal level of an output terminal 33 and an output data buffer. A comparison circuit for comparing the output signal level of the output signal from the control circuit, an interrupt control circuit operating on the basis of the comparison result of the comparison circuit, and a circuit control means (39) controlled by the operation of the interrupt control circuit; When the signal level of the terminal 33 and the output signal level of the output data buffer 31 do not match, the interrupt control circuit 36 is operated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit including a microprocessor used for controlling electric equipment.

[0002]

2. Description of the Related Art In recent years, there has been a great deal of interest in the safety of electrical equipment, and safety design has become an important factor for electrical equipment manufacturers. The safety of semiconductor integrated circuits including microprocessors, which have been actively used in devices, home appliances, and the like, has also been pursued. In these portable home appliances, the device is controlled by the microprocessor, so if an excessive current or the like flows through the microprocessor for some reason and causes an abnormality such as destruction, the worst case is when the temperature of the main unit becomes too high. There is a risk of fire.

A conventional semiconductor integrated circuit including a microprocessor of this type will be described below with reference to the drawings.

FIG. 5 is a block diagram showing a configuration of a conventional device control circuit using a microprocessor. In the figure, reference numeral 1 denotes a control device, 2 denotes a device control switch, 3 denotes a device protection switch, and 4 denotes a microprocessor. First, when the operation of the device is necessary, the device control switch 2 is turned on by the device control signal Sc output from the microprocessor 4 based on the input sensor signal Si instructing the operation, and the operation of the device is started. If it becomes unnecessary, the device control switch 2 is turned off by the device control signal Sc based on the input sensor signal Si indicating that fact. At this time, if the terminal of the device control switch 2 is broken due to an overcurrent at the time of switching or the like, the device control switch may remain in an ON state, and the temperature of the device continues to rise. In such a case, the sensor detects the abnormal temperature rise, and an input sensor signal Si is input to the microprocessor 4 as a signal to that effect, and a device protection signal Ss is output from the microprocessor 4 to switch the device protection switch. 3 is configured to be turned off.

[0005]

However, in such a configuration, the temperature at which the microprocessor can recognize the abnormality of the device control by the sensor usually has a sufficient margin with respect to the temperature at which the device is heated by the current flowing through the semiconductor. Temperature, and when it is recognized as abnormal, other elements inside the device have already been damaged, and in the worst case, there is a high possibility that burns and ignition have occurred. Had a point. In addition, when immediate abnormality detection is required, it is extremely difficult to make an instantaneous determination because portable devices and the like are particularly susceptible to external noise and the like.

The present invention solves the above-mentioned conventional problems. An interrupt is generated when the output signal level of a microprocessor is different from the level to be output due to destruction of an output terminal or the like. It is an object of the present invention to provide a semiconductor integrated circuit that can detect the occurrence of an error and can take appropriate measures based on the detection.

[0007]

SUMMARY OF THE INVENTION A semiconductor integrated circuit according to the present invention includes a microprocessor, and outputs an output of an output data buffer to an output terminal via an output buffer. A comparison circuit that compares a signal level of a terminal with an output signal level of an output data buffer; an interrupt control circuit that operates based on a comparison result of the comparison circuit; and a circuit control unit that is controlled by an operation of the interrupt control circuit. When the signal level of the output terminal does not match the output signal level of the output data buffer, the interrupt control circuit is operated.

According to the present invention, when the output terminal is destroyed or the like, an interrupt is immediately generated, and an appropriate countermeasure against an abnormality such as turning off the device protection switch by software processing, or notifying by vibration, buzzer, or panel display. Safety control that takes appropriate measures is possible.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an example of a circuit configuration in an embodiment of a semiconductor integrated circuit of the present invention, and FIG. 2 is another example of a circuit configuration in an embodiment of the semiconductor integrated circuit of the present invention. FIG. 3 is a block diagram showing still another example of the circuit configuration in one embodiment of the semiconductor integrated circuit of the present invention. FIG. 4 is a timing chart of a microprocessor in one embodiment of the semiconductor integrated circuit of the present invention. FIG. 1 is a circuit diagram of a semiconductor integrated circuit to be processed.

[0011] In FIG. 1, the output data buffer 11, 12 output buffer, the output terminal 13, the comparator circuit 14, the interrupt control circuit 16, 17 CPU, 18 is a microprocessor, S ₁ is an interrupt request signal is there.

In FIG. 2, reference numeral 21 denotes an output data buffer, 22 denotes an output buffer, 23 denotes an output terminal, 24 denotes a comparison circuit, 26 denotes an interrupt control circuit, 27 denotes a CPU, 28 denotes a microprocessor, and 29 denotes a control switch for an output terminal. ,
S ₂ is an interrupt request signal.

In FIG. 3, 31 is an output data buffer, 32 is an output buffer, 33 is an output terminal, 34 is a comparison circuit, 35 is a logical product gate, 36 is an interrupt control circuit,
37 CPU, 38 is a microprocessor, 39 a control switch of the output terminal, S ₃ is an interrupt request signal.

In FIG. 4A, A indicates the output waveform of the output data buffer, B indicates the output waveform of the output terminal, and C indicates the waveform of the interrupt request signal. FIG.
The circuit shown in (b) is a circuit in which three comparison circuits are provided in the circuit shown in FIG. 3, and is a circuit which is an object of the timing chart of FIG. This circuit is an example in which the microprocessor has one cycle of three cycles. In other cases, a comparison circuit of the number of cycles is required. For example, in the case of the circuit of FIG. 2, each of samplings 1 to 3, 4 to 6, and 7 to 9 (see FIG. 4A) is one cycle.

The operation of the semiconductor integrated circuit thus configured according to the present embodiment will be described below.

(1) When the output terminal is normal The output signal level of the output data buffer 11 of the circuit of FIG. 1 and the signal level of the output terminal 13 via the output buffer 12 are the same, and the comparison circuit 14 outputs an abnormal signal. interrupt request signals S ₁ not detect does not occur.

[0017] Similarly interrupt request signal S ₂ also in the circuit of Figure 2 does not occur.

In the circuit of FIG. 3, the output signal level of the output data buffer 31 and the signal level of the output terminal 33 via the output buffer 32 are the same as sampling 1 and sampling 3 in the timing chart of FIG.
The output of the comparator circuit 34 becomes the low level, the interrupt request signal S ₃ through the AND gate 35 does not occur. Further, when the output terminal is normal and the output waveform A of the output data buffer changes due to the load of the output terminal due to the load of the output terminal as shown in sampling 2 in FIG. Although it is determined that the comparison results do not match, no interruption occurs because the comparison results match in sampling 1 and sampling 3, which are the same period of the microprocessor. In addition, when the output terminal is normal, noise occurs at the output terminal due to external factors as shown in sampling 4 in FIG. 4, and the signal level of the output terminal changes with respect to the change of the output signal level of the output data buffer. In this case, it is determined that the comparison results do not match, but no interruption is generated because the comparison results match in samplings 3 and 5 in the same cycle.

(2) When the output terminal is destroyed The output signal level of the output data buffer 11 of the circuit of FIG. 1 is different from the signal level of the output terminal 13 via the output buffer 12, and the output of the comparison circuit 14 indicates an abnormal signal. Upon detection, an interrupt request signal S ₁ is generated, the interrupt is accepted by the interrupt control circuit 16, and the CPU 17 executes an interrupt processing program. This allows the CPU 17
Stops, and no further malfunction occurs.

In the circuit of FIG. 2, similarly, an interrupt request signal S ₂ is generated, the interrupt is accepted by the interrupt control circuit 26, and the CPU 27 executes an interrupt processing program. At the same time, the control switch 29 of the output terminal is turned off by the interrupt signal, and the output of the output terminal enters a high impedance state, so that no more erroneous signal is output. This prevents a malfunction of the external device.

In the circuit of FIG. 3, in the case of sampling 7 to sampling 9 in FIG. 4, the output signal level of the output data buffer 31 and the output buffer 32 of FIG.
, The signal level of the output terminal 33 is different, and a plurality of comparison circuits 3 sampled at different timings.
4 are all high level, and the AND gate 35
When the output of also becomes high level, the interrupt request signal S ₃ occurs, an interrupt is received by the interrupt control circuit 36, the interrupt processing program is executed in the CPU 37. Further, the control switch 39 of the output terminal is turned off by the interrupt signal, and the signal level of the output terminal 33 becomes a high impedance state as shown in FIG.
No further erroneous signal is output.

As described above, according to the present embodiment, the function of comparing the signal level of the output terminal with the output signal level of the output data buffer and generating an interrupt when they do not match, and the output based on the function. By having the function of controlling the signal of the terminal, it is possible to detect abnormalities immediately and take appropriate measures, and a plurality of circuits for comparing the signal level of the output terminal with the output signal level of the output data buffer. By arranging and logically ANDing the comparison results of the data sampled at different timings, the software processing and the hardware processing can be performed without generating an erroneous interrupt due to noise or the like. Immediate safety control is possible with a few additional circuits.

[0023]

As described above, according to the present invention, an abnormality is immediately detected by generating an interrupt when the output signal level of the microprocessor is different from the level to be originally output due to the destruction of the output terminal or the like. And an appropriate effect based on this can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a circuit configuration according to an embodiment of a semiconductor integrated circuit of the present invention.

FIG. 2 is a block diagram showing another example of the circuit configuration in one embodiment of the semiconductor integrated circuit of the present invention;

FIG. 3 is a block diagram showing still another example of the circuit configuration in one embodiment of the semiconductor integrated circuit of the present invention;

FIG. 4 is a timing chart of a microprocessor and a circuit diagram of a target semiconductor integrated circuit according to an embodiment of the semiconductor integrated circuit of the present invention;

FIG. 5 is a block diagram showing a configuration of a device control circuit using a conventional microprocessor.

[Explanation of symbols]

 11, 21, 31 Output data buffer 12, 22, 32 Output buffer 13, 23, 33 Output terminal 14, 24, 34 Comparison circuit 16, 26, 36 Interrupt control circuit 17, 27, 37 CPU 18, 28, 38 Microprocessor 29, 39 Output terminal control switch 35 AND gate A Output data buffer output waveform B Output terminal output waveform C Interrupt request signal waveform

Claims (3)

[Claims] 1. A semiconductor integrated circuit including a microprocessor, wherein an output of an output data buffer is output to an output terminal via an output buffer, wherein a signal level of the output terminal and an output signal level of the output data buffer are provided. A comparison circuit, an interrupt control circuit that operates based on the comparison result of the comparison circuit, and circuit control means controlled by the operation of the interrupt control circuit. A semiconductor integrated circuit for operating an interrupt control circuit when output signal levels do not match. 2. The semiconductor integrated circuit according to claim 1, wherein the circuit control means performs control for cutting off the output of the output terminal. 3. The circuit according to claim 1, wherein a plurality of comparison circuits are arranged, and a malfunction of the circuit control means is prevented by ANDing comparison results of data sampled at different timings. 3. The semiconductor integrated circuit according to item 2.