JP2000029420A - Image display device - Google Patents

Abstract

(57) [Problem] To provide an image display device having a simple circuit configuration, which can prevent degradation of video quality due to a timing difference between a video signal and a sampling signal. A phase detection unit (13) uses a detection signal (MON1) as a reference and a part of a circuit of a data signal line drive circuit (3) itself or a part of a circuit formed by the same process as the data signal line drive circuit (3). The phase difference between the detection signal MON1 and the detection signal MON2 obtained by delaying the detection signal MON1 is detected. The phase adjusting unit 14 estimates the internal delay of the data signal line driving circuit 3 based on the phase difference, and generates the clock signal CKS and the clock signal CKS so that the data signal line driving circuit 3 can sample the video signal DAT at an appropriate timing. The phase difference between the start signal SPS and the video signal DAT is adjusted. Further, on the input side of the phase detection unit 13, a conversion unit 11 for shortening the rise time of the input signal is provided, and the phase difference can be detected with high accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device having a sampling section for sampling a video signal and a sampling signal generating section for instructing the sampling section to give a sampling timing. The present invention relates to an image display device capable of displaying a high-quality image without causing deterioration in video quality due to a timing deviation even if characteristics are different for each sampling signal generation unit.

[0002]

2. Description of the Related Art Image display devices having pixels arranged in a matrix, such as an active matrix type liquid crystal display device, have been widely used. As shown in FIG. 13, the pixel array 102 of the image display device 101 includes:
sequentially selecting n data signal lines SL ₁ to SL _n of this, them and the scanning signal lines GL ₁ ～GL _m of the m crossing is provided together, the scanning signal line drive circuit 104 is a scanning signal line GL Meanwhile, the data signal line driving circuit 103 outputs the respective video data D to each data signal line SL. Thus, the video data D is written to the pixel PIX corresponding to the combination of the scanning signal line GL and the data signal line SL, and the display state of each pixel PIX is set. When it is necessary to specify a position, such as the _first scanning signal line GL1, reference is made by adding a subscript indicating the position. G
As in L, reference is made without the suffix.

Here, the image display device 101 is provided with video data D to each pixel PIX in a time-division manner as a video signal DAT.
Is, for example, a start signal SPS or a clock signal CKS.
The video signal DAT is sampled in synchronization with a timing signal such as the above, amplified if necessary, and output to each data signal line SL.

More specifically, for example, FIG.
As shown in FIG. 5, when the start signal SPS is input to the sampling signal generation unit 132 of the data signal line driving circuit 103, the shift register unit 133 outputs the clock signal CKS.
, The start signal SPS is shifted. further,
The buffer unit 134 is configured to output the data signal lines SL _{1 to} SL based on the outputs N _{1 to} N _{n of the} stages of the shift register unit 133.
generating a sampling signal S ₁ to S _n indicating the sampling timing corresponding to _n.

In the sampling section 131 of the data signal line driving circuit 103, a sampling circuit AS provided for each data signal line SL converts a video signal DAT to a data signal based on a corresponding sampling signal S (/ S). It is determined whether to output to the line SL. Thereby, the video data D corresponding to each data signal line SL is
Is output.

Here, the data signal line driving circuit 103
, A finite signal delay occurs, and as shown in FIG. 16, each sampling signal S is a clock signal CKS.
, And changes with a delay time td. The delay time t
d is determined by characteristics (mobility, threshold voltage, and the like), size, and the like of the transistors included in the data signal line driving circuit 103. Therefore, clock signal CKS
Is applied at a timing when the phase difference from the video signal DAT becomes ta in anticipation of the delay time td, and the sampling time t101 (falling time of the sampling signal S) is set to a value immediately before the switching time t102 of the video data D. (Td ≦ ta).

In the following, for convenience of explanation, the phase difference ta between the video signal DAT and the clock signal CKS will be referred to as the switching time t102 of the video data D and the video data D
Is defined as the difference from the falling point of the clock signal CKS used to generate the sampling signal S corresponding to Further, the sampling signal S of the data signal line SL ₁ is
₁ and will be described as an example the relationship between the video data D ₁ corresponding thereto.

In this case, the sampling circuit AS ₁ can sample the video signal DAT at a correct timing,
Video data D ₁ having a correct value is output to the data signal line SL ₁ . Further, when writing the video data D ₁ to the pixel PIX, it is necessary to hold the video data D ₁ for a predetermined time, but since the time from the stabilization of the video data D ₁ to the sampling time t101 is sufficiently long, , Pixel PIX
Can secure a sufficient hold time. As a result, the image display device 101 can display a high-quality image without ghosts or bleeding.

[0009]

However, in the above configuration, if the delay time td varies, the data signal line driving circuit 103 cannot sample the correct video data D, and image quality such as ghost or blur of the video is deteriorated. Is generated.

Specifically, the delay time td varies, and the actual delay time td is larger than the assumed delay time td.
If dx is increased, as shown in FIG. 17, the sampling time t101x the sampling signals S ₁ instructs
May be later than the switching time t102 of the video data D (tdx> tax). In this case, an incorrect signal is output to the data signal line SL ₁ while the video data D ₁ is being switched from D ₁ to D ₂ , or the next video data D ₂ is mixed, thereby causing blurring of the video. And ghosts occur.

Meanwhile, as shown in FIG. 18, than the assumed delay time td, if the actual delay time tdy is short, from the time t100 to the video data D ₁ is stabilized, the sampling time t101y the sampling signals S ₁ instructs , The hold time may not be able to be secured (tdy << day). In this case, the pixel P
It can not be written to the video data D ₁ of the correct value to IX, bleeding of the image is generated.

In the above description, the case where each sampled video data D is directly written to the pixel PIX as in the dot sequential driving method has been described as an example, but the same applies to the line sequential driving method. Problems occur. That is, in the case of the line-sequential driving method, each video data D is once held by the sampling and holding circuit and then applied to each pixel PIX, but the sampling and holding circuit also requires a hold time. Therefore, in any case, the sampling signal S and the video signal DA
If a deviation from T occurs, blurring or ghosting of an image occurs.

In recent years, in particular, in recent years, there has been a demand for downsizing, higher resolution, and lower mounting costs of image display devices. To meet these demands, driving circuits such as data signal line driving circuits have been demanded. A technique for integrally forming a pixel array and a pixel array on the same substrate has attracted attention. In such an image display device integrated with a driving circuit, a polycrystalline silicon thin film transistor formed on a quartz substrate, a glass substrate, or the like is often used as an active element in order to increase a display area. In particular, in the case of a transmissive liquid crystal display device that is widely used at present, the substrate must be made of the above-described material because the substrate needs to transmit light.

However, in a polycrystalline silicon thin film transistor, the size of a crystal grain and the state of an interface vary depending on the manufacturing conditions, and as a result, transistor characteristics (carrier mobility, threshold voltage, leak current, etc.) may vary greatly. . For example, it is not uncommon for the threshold voltage to be within a range of several tens of mV within the same substrate, but to have a variation of several V between different substrates. Therefore, the variation of the delay time td is larger than when single crystal silicon is used as the substrate.

On the other hand, since the resolution of the image display device has been improved, the application period of the video signal DAT tends to be further shortened. Therefore, the timing deviation allowed for both signals DAT · S is also decreasing, and it is difficult to appropriately set the phase difference ta between the video signal DAT and the clock signal CKS in advance. As a result, bleeding or ghosting of the image is likely to occur, and there is a strong demand for an image display device that can fundamentally suppress these occurrences.

Here, for example, in Japanese Patent Application Laid-Open No. 5-46118, in order to prevent a display position shift, it is detected whether or not a sampling signal corresponding to video data exists, and based on the detection result, An image display device for adjusting a timing difference between the two is disclosed. However, in this configuration, a circuit for specifying a sampling signal corresponding to video data is required, and a relatively complicated circuit is required.
Further, the image display device cannot detect an abnormality until the sampling signal corresponding to the video data disappears, so that blurring of the video cannot be prevented.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide an image display device having a simple circuit configuration, which can prevent a decrease in image quality due to the above-mentioned timing shift. It is in.

[0018]

According to a first aspect of the present invention, there is provided an image display apparatus, comprising: a sampling circuit for sampling a video signal based on a sampling signal; and a supply timing of the video signal. An image display device having a sampling signal generation unit for generating the sampling signal based on a timing signal is characterized by the following means.

That is, a delay circuit composed of elements generated by the same process as the elements constituting the sampling signal generation section, detection means for measuring the delay time of the delay circuit, and detection results of the detection means A phase difference adjusting means for adjusting a phase difference between the video signal and the sampling signal based on the phase difference.

The delay circuit may be a part of the sampling signal generation unit itself or may be a part of the sampling signal generation unit as long as it is generated by the same process as the elements constituting the sampling signal generation unit. Circuit. The phase difference adjusting means can adjust the phase difference between the video signal and the sampling signal by controlling at least one of the phase of the video signal and the phase of the sampling signal. Further, when the phase difference adjusting means controls the phase of each signal, the video signal itself, or may control the sampling signal itself, instead of controlling the phase of each signal,
For example, the phase of a signal used when generating a video signal or a sampling signal, such as a timing signal, may be controlled.

In the above configuration, the sampling signal generator and the delay circuit are composed of elements generated by the same process. As a result, for example, when the characteristics (such as mobility and threshold voltage) of the element change due to variations in the manufacturing process, the delay time of the sampling signal generation unit and the delay time of the delay circuit have substantially the same tendency. Change.

Here, the phase difference adjusting means adjusts the phase difference between the video signal and the sampling signal based on the delay time of the delay time, so that both signals have a position corresponding to the delay time of the sampling signal generator. Set to phase difference. Thus, even if there is a difference in element characteristics between the sampling signal generation units, the sampling circuit can always sample the video signal at an appropriate timing.

Therefore, it is possible to reliably prevent the occurrence of a ghost, a band-like display unevenness, and a blur at an edge portion of an image due to a timing shift between the video signal and the sampling signal. As a result, the image display device can display a high-quality image.

Further, in the above configuration, since the phase difference is adjusted based on the delay time of the delay circuit, the sampling signal or timing signal corresponding to the video signal is not specified, and the video signal and the sampling signal are not specified. The phase difference can be adjusted. As a result, although the phase difference can be adjusted by the image display device alone, a circuit for specifying the above correspondence is not required, and the configuration of the image display device can be simplified.

By the way, the detecting means is, of course,
It may be constituted by an analog circuit or a digital circuit. However, in the case of an analog circuit, it is difficult to set the accuracy when the phase difference adjusting means adjusts the phase difference and the accuracy when the detecting means detects the delay time to the same degree, and the detecting means is difficult. There is a possibility that the circuit configuration may be required to be highly accurate and complicated, or the detection means may not be able to satisfy the detection accuracy required by the phase difference adjusting means.

On the other hand, in the image display apparatus according to the second aspect of the present invention, in the configuration according to the first aspect, the detecting means detects the timing (for example, rising or falling) indicated by a reference signal serving as a reference. Drop, etc.)
Until a timing indicated by a delay signal generated by delaying the reference signal, the delay circuit counts the number of pulse signals applied in a predetermined cycle and detects a delay time of the delay circuit. And

According to the above configuration, a highly accurate detection means can be realized by a simple circuit as compared with the case where it is configured by an analog circuit.

In the image display apparatus according to a third aspect of the present invention, in the configuration of the second aspect, the frequency of the pulse signal is set to an integral multiple of the frequency of the timing signal. And

According to the above configuration, interference between the pulse signal and the timing signal can be prevented, so that the display quality of the image display device can be further improved. In addition, if a pulse signal is divided to generate a timing signal, or a common clock signal is divided by different division ratios to generate a pulse signal and a timing signal, a new clock signal is prepared. Without generating a timing signal. As a result, the configuration of the image display device can be simplified as compared with the case where a new clock signal is prepared.

Incidentally, the delay signal delayed by the delay circuit changes relatively slowly even if the signal before the delay changes sharply. In particular, when the sampling signal generation unit and the delay circuit are formed on the same substrate as the substrate on which the pixels are formed, the driving capability of the circuit element tends to be low, and the signal dullness tends to increase.
Therefore, if the detection unit detects the delay time based on the point in time when the change of the delay signal ends, the detection accuracy may be reduced. On the other hand, if the delay signal is changed steeply to improve the detection accuracy, the power consumption increases and the circuit becomes complicated.

On the other hand, an image display device according to a fourth aspect of the present invention is the image display device according to the first, second or third aspect of the invention, wherein the sampling signal generator and the delay circuit are
The time during which the delay signal changes is formed on the same substrate as the substrate on which the pixels are formed, and before the delay signal output from the delay circuit to the outside of the substrate is input to the detection means. A conversion means is provided for converting the delay signal into a conversion signal whose change is completed in a shorter time. The conversion unit may have any circuit configuration as long as it can convert the signal into a signal having a short changing time (transition time). For example, the conversion unit may be configured by a differentiating circuit, a clipping circuit, or the like.

According to the above configuration, even if the delay signal output from the substrate is somewhat dull, the detection means can detect the delay time based on the converted signal having a sharp change, so that the detection accuracy of the detection means can be further improved. Can be improved. As a result, an image display device with higher display quality can be realized.

Further, since the detecting means can detect the delay time with high accuracy even if the output characteristic (driving ability) of the circuit for outputting the delay signal from the substrate is low, the load on the output circuit formed on the substrate is reduced. It is possible to suppress power consumption. Further, since the output circuit can be configured with a circuit having a low driving capability and a simple configuration, a more reliable image display device can be realized. In addition, it is possible to improve the tolerance of the load condition in the path from the output circuit to the detection means.

According to a fifth aspect of the present invention, in the image display device according to the fourth aspect, the conversion means includes a differentiating circuit. In this configuration, in the steady state, no current flows between the input and output of the differentiating circuit, so that an increase in power consumption of the conversion means can be prevented and the level can be suppressed to an extremely low level. Further, since the load on the output circuit can be further suppressed, an image display device with lower power consumption and higher reliability can be realized. In addition, it is possible to improve the tolerance of the load condition in the path from the output circuit to the detection means.

According to a sixth aspect of the present invention, in the image display device according to the fourth or fifth aspect, the conversion means clips the input signal to a level substantially equal to a power supply potential of the detection means. It is characterized by including a clipping circuit. Thus, even if the peak value of the delay signal exceeds the rated input condition of the detecting means, the converting means can generate a converted signal satisfying the rated input condition with a relatively simple circuit. Further, since the converted signal satisfies the rated input condition, it is possible to prevent the destruction of the detecting means and the deterioration of characteristics.

In addition, for example, when the threshold value of the active element formed inside the substrate is high and the peak value of the delay signal output from the substrate tends to be high, as in a TFT type image display device, for example. Even so, the rated input conditions can be satisfied. Therefore, as compared with the case where a level shifter is provided in the output circuit of the delay signal in order to satisfy the above rated input condition,
The shift amount of the level shifter can be reduced to reduce the load on the level shifter, or the level shifter itself can be omitted.
As a result, an image display device having high reliability and a simple circuit configuration can be realized.

On the other hand, an image display device according to the invention of claim 7 is the image display device according to claim 1, 2 or 3,
The sampling signal generation unit and the delay circuit are formed on the same substrate as the substrate on which the pixels are formed, and the detection unit determines that the delay signal output from the delay circuit to the outside of the substrate is a predetermined signal. Based on when the threshold is exceeded,
A delay time of the delay circuit is detected, and a threshold value of the detection means is set within 50% of a peak value of the delay signal. The detecting means detects a time point when the delay signal exceeds the threshold value and becomes larger when detecting the rising edge of the delay signal, and a threshold value when detecting the falling edge of the delay signal. Detect when the value exceeds the value and becomes smaller.

According to the above configuration, the detecting means can detect a change in the delay signal by using a steep portion immediately after the start of the change in the delay signal. As a result, even if the delay signal output to the outside of the substrate is somewhat blunt,
The delay time of the delay circuit can be detected with higher accuracy as well as earlier.

In addition, the detecting means can detect the delay time with high accuracy even if the output characteristic (driving ability) of the circuit for outputting the delay signal from the substrate is low. The load on the output circuit to be created can be reduced,
In the path from the output circuit to the detection means, the tolerance of the load condition can be improved, and the image display device with low power consumption and high reliability can be realized.

Further, unlike the configuration of the invention described in claim 4, the detection accuracy of the detection means is improved without providing the conversion means. As a result, an image display device having a simple circuit configuration and a small number of components can be realized as compared with the configuration.

According to an eighth aspect of the present invention, in the image display device according to the first, second, third, fourth, fifth, sixth, or seventh aspect, the phase difference adjusting means includes: Before the display is started, the phase difference between the video signal and the sampling signal is adjusted.

According to this configuration, the image display device does not display an image when the phase difference adjusting means adjusts the phase difference. Therefore, even before and after the adjustment, the timing at which each sampling circuit samples the video signal changes, and even if the output of the sampling circuit changes significantly, the displayed image is not disturbed. As a result, the phase difference can be adjusted without giving the user a feeling of strangeness. Further, since the period during which the phase difference is adjusted is limited to the period during which no image is displayed, the power consumption of the image display device can be reduced as compared with the case where the phase difference is adjusted even during image display.

According to a ninth aspect of the present invention, in the image display device according to the eighth aspect, the phase difference adjusting means is configured to control the image signal before the light source of the light emitted from the pixel is turned on. And a phase difference between the sampling signal and the sampling signal.

In this configuration, since the light source is turned off while the phase difference adjusting means is adjusting the phase difference, no image is displayed on the image display device. Further, since the turning on or off of the light source can be determined or controlled with a very simple circuit, an image display device capable of adjusting the phase difference without giving a user a sense of incongruity can be realized with a simple circuit.

On the other hand, an image display device according to a tenth aspect of the present invention is the image display device according to the eighth aspect, further comprising a reflective pixel array capable of controlling the display state of each pixel in accordance with the output of the sampling circuit. At least a phase difference adjusting display means for displaying a fixed level image on the pixel array while the phase difference adjusting means adjusts the phase difference is provided. The display means for adjusting the phase difference may keep the output of the sampling circuit constant, for example, by keeping the video signal at a constant level, or may provide a constant output to each pixel of the pixel array separately from the sampling circuit. A circuit for supplying a signal of a level may be provided to display a video of a certain level.

According to the above configuration, in the reflection-type image display device, the phase difference can be adjusted without giving a sense of incongruity to the user, and the power consumption can be reduced as compared with the case where the phase difference is constantly adjusted.

The image display apparatus according to the eleventh aspect of the present invention is the image display device according to the first, second, third, fourth, fifth, sixth or seventh aspect, wherein the phase difference adjusting means is a last sampling circuit. Is characterized in that the phase difference is adjusted during a period from the end of the sampling of the video signal to the start of the sampling of the video signal by the first sampling circuit.

According to the above configuration, since the phase difference is adjusted at the time of image switching, even if the phase difference is adjusted during image display, the output of the sampling circuit does not change due to the adjustment, and the displayed image is not changed. No disturbance occurs. As a result, the image display device can adjust the phase difference during display without giving the user a feeling of strangeness.

Further, since the user does not feel uncomfortable even if the phase difference is frequently adjusted during display, the delay time of the sampling signal generation unit may fluctuate during the operation of the image display device due to the aging of the circuit or the temperature. Even so, the phase difference between the video signal and the sampling signal can be kept at an appropriate value by following the fluctuation.

When the phase difference adjusting means adjusts the phase difference based on one detection result of the delay time, for example, if the detection result contains an error due to noise or the like, the image signal and the video signal are output. There is a possibility that the phase difference from the sampling signal may be set to an undesired value.

On the other hand, the image display apparatus according to the twelfth aspect of the present invention is characterized in that
In the configuration of the invention described in 8, 9, 10 or 11, the phase difference adjusting means adjusts the phase difference based on a result of the detection means detecting the delay time a plurality of times.

According to the above configuration, the phase difference adjusting means adjusts the phase difference based on the detection results of a plurality of times.
Even if a large error is included in the detection results, the phase difference adjusting means can adjust the phase difference between the video signal and the sampling signal to an appropriate value. As a result, the occurrence of a determination error can be suppressed, and the display quality of the image display device can be further improved.

In the case where the phase difference is adjusted even during display as in the configuration of the present invention, there is a possibility that erroneous determination by the detecting means may cause display disturbance. Therefore, it is particularly effective if the configuration of the twelfth aspect is applied to the configuration of the invention of the eleventh aspect to prevent erroneous determination of the detection means.

[0054]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention.
This will be described below with reference to FIG.
As will be described later, the present invention can be widely applied to an image display device that samples a video signal and writes video data to each pixel. Hereinafter, an active matrix type liquid crystal display device will be described as an example. .

That is, as shown in FIG. 1, an image display device 1 according to the present embodiment includes a pixel array 2 having pixels arranged in a matrix, a data signal line driving circuit 3 for driving each pixel, and a scanning circuit. When the video signal processing circuit 5 generates a video signal DAT from an RGB signal or the like, an image can be displayed based on the video signal DAT.

The pixel array 2 includes, as shown in FIG.
n data signal lines SL _{1 to} SL _n and m scanning signal lines G intersecting each of the data signal lines SL _{1 to} SL _n
And a L ₁ ~GL _m. Any positive integer less than or equal to n i, any positive integer less than or equal to m When j, for each combination of the data signal line SL _i and the scanning signal line GL _j, pixel P
IX _{(i, j)} is provided, and each pixel PIX _{(i, j)} is
It is arranged in a portion surrounded by two adjacent data signal lines SL _i and SL _{i + 1} and two adjacent scanning signal lines GL _j and GL _{j + 1} . In the present embodiment, for convenience of explanation, for example, as in the i-th data signal line SL _i, only when it is necessary to specify the position, reference are given the subscript indicating the position, identify the location In cases where it is not necessary or necessary to refer to a generic name, reference is made by omitting the subscript.

[0057] The pixel PIX _{(i, j),} for example, as shown in FIG. 3, the gate to the scanning signal line GL _j, a field effect transistor SW whose drain is connected to the data signal line SL _i, the electric field the source of the effect transistor SW, one electrode and a pixel capacitor C _P connected. The other end of the pixel capacitor C _P is connected to the common of the common electrode line to all the pixels PIX. The pixel capacitance C _P includes a liquid crystal capacitance C _L and an auxiliary capacitance C _S added as needed.

[0058] The pixel PIX _{(i, j)} in the scanning signal line GL _j is selected, conductive field effect transistor SW is, voltage applied to the data signal line SL _i is applied to the pixel capacitor C _P You. On the other hand, the scanning signal line GL _j selection period is finished, while the field effect transistor SW is blocked, the pixel capacitor C _P, continues to hold the voltage during blocking. Here, transmittance or reflectance of the liquid crystal varies depending on a voltage applied to the liquid crystal capacitor C _L. Therefore, selecting the scanning signal line GL _j, by applying a voltage corresponding to the video data D to the data signal line SL _i, the pixel PI
The display state of X _{(i, j)} can be changed together with the video data D.

In the image display device 1 shown in FIG. 1, the scanning signal line driving circuit 4 selects the scanning signal line GL, and sends the selected pixel to the pixel PIX corresponding to the combination of the scanning signal line GL and the data signal line SL. The video data D is output by the data signal line drive circuit 3 to each data signal line SL. Thereby, the respective video data D are written to the pixels PIX... Connected to the scanning signal line GL.
Further, the scanning signal line driving circuit 4 sequentially selects the scanning signal lines GL, and the data signal line driving circuit 3
The video data D is output to As a result, the video data D is written to all the pixels PIX of the pixel array 2.

Here, as shown in FIG. 6, between the video signal processing circuit 5 and the data signal line driving circuit 3, the video data D to each pixel PIX is transmitted as a video signal DAT in a time division manner. And the data signal line driving circuit 3
Is a clock signal C having a predetermined cycle serving as a timing signal.
At the timing based on KS and start signal SPS,
Each video data D is extracted from the video signal DAT.

Specifically, the data signal line driving circuit 3
Includes, for example, a sampling unit 31 including sampling circuits AS _{1 to} AS _n provided between a signal line for transmitting a video signal DAT and each of the data signal lines SL _{1 to} SL _n , as shown in FIG. Each sampling circuit AS _{1 to} AS
to _n, and a sampling signal generator 32 for outputting a respective sampling signal S ₁ to S _n. Furthermore, to the sampling signal generator 32 includes a cascaded latch circuits LAT ₁ to LAT _n, in synchronization with the clock signal CKS, the shift register 33 for sequentially shifting the start signal SPS, the latch circuits LAT ₁
Based on the output N ₁ to N _n in to LAT _n, a buffer unit 34 is provided for generating each sampling signal S ₁ to S _n.

FIG. 4 shows one latch circuit L as an example.
A configuration in which one data signal line SL corresponds to AT is shown, and the buffer unit 34 buffers one output N and generates one sampling signal S.

More specifically, the portion corresponding to one data signal line SL in the data signal line drive circuit 3 is
Then, in each block SD, the sampling circuit AS drives the corresponding data signal line SL bidirectionally, so that the two analog switches AS of different polarities are driven.
a · ASb are connected in parallel. The two analog switches ASa and ASb output the sampling signal S
And their inverted signals / S are opened and closed almost simultaneously. In this embodiment, both analog switches ASa and AS
The polarity of b is set so as to be cut off at the time when the sampling signal S falls (at the time when the inverted signal / S rises). On the other hand, in the buffer section 34, the output N of the latch circuit LAT is inverted by the inverter G1, and then supplied to the analog switch ASa as the sampling signal S via the inverter G2. The output of the inverter G1 is supplied to the analog switch ASb as an inverted signal / S of the sampling signal S via the inverters G3 and G4.

[0064] In the above configuration, start signal SPS input to the shift register unit 33, each pulse application of the clock signal CKS (in this case, each edge) is shifted by one stage, each sampling circuit AS _i, than the previous sampling circuit AS _i-1, a sampling signal S _i of a timing delayed by the pulse application period of the clock signal CKS is supplied. Here, the phase difference ta between the clock signal CKS and the video signal DAT is, the converter 11 and the timing control circuit 12 will be described later, the sampling circuit AS _i is adjusted to allow obtaining the image data D _i at the correct timing .

As a result, the data signal line driving circuit 3
Video data D corresponding to each data signal line SL can be extracted from the video signal DAT and output to each data signal line SL. As a result, each pixel PIX is supplied with video data D having an accurate value, and the pixel array 2 can display an image without blurring or ghost of the video.

FIG. 4 shows an example in which one sampling signal S is generated from the output N of one latch circuit LAT. However, as shown in FIG. May be used to generate one sampling signal. In this configuration example, each block SD _i
So instead of the inverter G1, NAND circuit G5 is provided, and outputs the negation of logical product of the output N _{i + 1} of the latch circuit outputs N _i and the next-stage latch circuit LAT _i LAT _i + ₁ ing.

Hereinafter, the clock signal CKS and the video signal DAT for instructing the timing to the data signal line driving circuit 3 will be described.
The adjustment of the phase difference between the two will be described in detail. That is, as shown in FIG. 1, the data signal line driving circuit 3 according to the present embodiment includes a detection signal MO for detecting an internal delay.
N1.MON2 is formed so that it can be output.
The timing control circuit 12 has a phase difference t between the two detection signals MON1 and MON2 given through a conversion unit 11 described later.
a phase detection unit (detection means) 13 for detecting p, and a phase adjustment unit (which calculates the internal delay of the data signal line driving circuit 3 from the phase difference tp, and adjusts the phase difference ta between the video signal DAT and the clock signal CKS ( (Phase difference adjusting means) 14.

In this embodiment, the detection signals MON1.MO
As an example of a generation method of N2, as shown in FIG. 4 (FIG. 5), the last stage to the subsequent block SD _n of the block SD _y of the same configuration is provided redundantly, the input and output of the inverter G2 is detected The signals are output as signals MON1 and MON2. As a result, a signal obtained by delaying the detection signal (reference signal) MON1 by the inverter G2 is output as a detection signal (delay signal) MON2. In this case, the inverter G2 corresponds to the delay circuit described in the claims.

Here, the phase difference tp between the detection signals MON1 and MON2 (the delay amount of the inverter G2) is different from the phase difference td between the clock signal CKS and the sampling signal S (the delay amount of the sampling signal generation unit 32). In Although,
Since both the inverter G2 and the sampling signal generator 32 are formed in the data signal line drive circuit 3 and are manufactured by the same process, the phase difference t
There is a strong correlation between p and td.

More specifically, when both MON1 and MON2 are generated as the input and output of the inverter G2, the detected delay amount tp is larger than the delay amount td of the sampling signal generator 32 by the latch circuit LAT and Inverter G
The value is shorter by the delay time (signal transmission time) at 1 (G5). Here, the delay time of the latch circuit LAT and the inverter G1 (G5) also fluctuates due to variations in the characteristics of transistors constituting the circuit and changes with time.
In the same data signal line driving circuit 3, since there is no large difference in transistor characteristic variation and change with time, it can be estimated from the detected delay time tp. For example, when the delay time of the inverter G2 increases by 30%,
The delay time in the other inverters {G1 (G5), G3...} And the latch circuit LAT also increases by about 30%.

On the other hand, the delay time due to the circuits other than the data signal line drive circuit 3
Specifically, the delay time when the phase adjustment unit 14 generates the clock signal CKS based on the instruction of the phase detection unit 13 and the delay time when the phase adjustment unit 14 generates the video signal DAT
Delay time for adjusting the time difference between the two. However, the timing control circuit 12 is usually included in an external IC, and is configured by a transistor different from the data signal line driving circuit 3. Therefore, the variation of the delay time of the timing control circuit 12 is extremely small compared to the variation of the delay time of the data signal line driving circuit 3, and can be regarded as a substantially constant value.

In the above description, the case where the detection signals MON1 and MON2 are detected as input and output of the inverter G2 has been described as an example, but the phase difference t between the detection signals MON1 and MON2 has been described.
The relationship between the detection signal MON2 and the delay amount td of the sampling signal generation unit 32 is as follows.
2 and the detection signal MON1
Is established if is generated with a delay.

Therefore, the sampling signal generator 32
The delay amount td of the two detection signals MON1 and MON2 is expressed by the following equation (1) regardless of the output positions of the two detection signals MON1 and MON2: tdｄA.tp + B = tc (1) It can be approximated as a linear function of the phase difference tp. In the above equation (1), tc is an approximate value of the delay amount td, and the coefficients A and B are the circuit configuration of the sampling signal generation unit 32 and the detection signals MON1 · MO
In accordance with the detection position of N2 and the like, for example, the timing is set in advance by actual measurement or simulation. Since the coefficients A and B are determined by the shape of the element, the circuit configuration, and the like, they are maintained at substantially the same value even when the characteristics of the element are different between different substrates due to variations in the manufacturing process. .

On the other hand, the phase adjusting section 14 calculates the phase difference t detected by the phase detecting section 13 based on the above equation (1).
p, an approximate value tc of the delay amount td is calculated, and the video signal D
By controlling at least one of the AT and the clock signal CKS, the phase difference ta between the two signals DAT and CKS is adjusted.
Thus, the sampling time point t1 indicated by the sampling signals S _1, the corresponding video data D ₁ of the switching time point t
Set immediately before 2.

For example, FIG. 6 shows a case where the phase adjuster 14 controls the clock signal CKS to adjust the phase difference ta. For convenience of description, if a clock signal for sampling at a desired sampling time t1 is displayed as a clock signal CKSr when there is no delay, the phase adjustment unit 14 is earlier than the clock signal CKSr by the approximate value tc. The clock signal CKS is generated at a timing (timing that is later by the period-approximate value tc).

Generally, a circuit constituting the image display device 1 such as the timing control circuit 12 has a certain original clock signal C.
LK (the highest frequency timing signal in the system) or a clock signal CKS obtained by dividing the clock signal CLK. Therefore, if the timing at which frequency division is started is changed when the timing control circuit 12 generates the clock signal CKS, the phase adjustment unit 14
Can control the phase of the clock signal CKS on a pulse application cycle basis of the original clock signal CLK.

Since the clock signal CKS is a periodic signal, when the phase adjustment unit 14 controls the phase of the clock signal CKS, the control width of the phase is limited to the pulse application cycle of the clock signal CKS. Therefore, when controlling the phase of the clock signal CKS over a range longer than the pulse application cycle, the phase of the start signal SPS may be controlled together.

FIG. 6 shows the case where the clock signal CKS is controlled. However, if the sampling time t1 can be set immediately before the switching time t2, the supply timing of the video signal DAT may be controlled. Signal DAT
By controlling both clock signals CKS, both signals DAT
The phase difference ta of CKS may be adjusted.

The video signal processing circuit 5 includes a time axis adjusting section 51 capable of adjusting the timing of supplying the video data D,
An inversion processing unit 52 that inverts the output of the time axis adjustment unit 51;
A buffer unit 53 for buffering the output of the inversion processing unit 52; and the video signal processing circuit 5 also operates in synchronization with the original clock signal CLK. Therefore, the phase adjustment unit 14 instructs the time axis adjustment unit 51,
If the time when the frequency division is started is changed, the original clock signal CL
The phase of the video signal DAT can be controlled in units of the K pulse application cycle.

If the unit of phase adjustment is not sufficient even in the unit of the pulse application cycle of the original clock signal CLK, a clock signal having a higher frequency than the original clock signal CLK is separately provided and the clock signal CKS or the video signal The phase of DAT may be controlled. However, the pulse application cycle of the original clock signal CLK is usually equal to the clock signal C
Since it is set to be several times or more the pulse application cycle of KS, even when the original clock signal CLK is used, the phase adjustment unit 14 controls the clock signal CKS and the video signal DAT.
Can be controlled with sufficient accuracy.

In the above configuration, the phase difference ta between the clock signal CKS and the video signal DAT is equal to the detection signal MON1.MO
Based on N2, adjustment is made for each data signal line drive circuit 3, and each sampling circuit AS is set so as to be able to sample the video signal DAT at the correct timing (immediately before the switching time of the corresponding video data D). Therefore, the characteristics of the active elements of the data signal line drive circuit 3 vary due to the variation in the manufacturing process of the data signal line drive circuit 3, and the delay amount td of the sampling signal generation unit 32 varies for each data signal line drive circuit 3. Even if different, the sampling unit 31 can always sample the video signal DAT at the correct timing. As a result,
A high-quality image display device 1 that does not cause bleeding of images or ghosts can be realized.

Further, the delay amount td of the sampling signal generator 32 is estimated from the two detection signals MON1 and MON2. Therefore, the adjustment amount of the phase adjustment unit 14 can be determined without specifying the video data D corresponding to the sampling signal S. Thereby, the circuit configuration of the image display device 1 can be simplified as compared with the case where a circuit for specifying is provided.

For example, at the time of shipping, the timing difference between the sampling signal S and the video data D is measured, and the phase difference t between the clock signal CKS and the video signal DAT is measured.
If "a" is set for each image display device 1, the circuit for specifying can be omitted. However, in this case, it takes time to measure the timing deviation and set the delay amount for each image display device 1. Further, since the opportunity to adjust the phase difference ta is limited, for example, when the characteristics of the transistor change due to a change over time or a change in the surrounding environment, and the amount of delay changes, the phase difference between the two signals CKS and DAT is changed. ta cannot be maintained at a correct value, and blurring or ghosting of the image may occur. In particular, when the liquid crystal display device is used as an optical shutter for a projector, the ambient temperature is 60 ° C.
Since the above may occur, the temperature can be a large fluctuation factor.

On the other hand, in the image display device 1 according to the present embodiment, the phase difference ta between the two signals CKS and DAT can be adjusted by a simple circuit. Therefore, it is possible to greatly reduce the time and effort required for manufacturing, and even if the characteristics of the transistor change due to aging or changes in the surrounding environment,
The phase difference ta between the two signals CKS and DAT can always be kept at a correct value.

Here, since the phase detector 13 only needs to be able to detect the phase difference ta between the detection signals MON1 and MON2, various configurations can be adopted regardless of analog / digital. The circuit configuration can be simplified. In this case, as shown in FIG. 7, the phase detector 13 determines how many times the original clock signal (pulse signal) CLK has risen between the rise of the detection signal MON1 and the rise of the detection signal MON2. Count and detect the phase difference tp between the two detection signals MON1 and MON2.
Is detected.

Here, an independently generated pulse signal may be used as the clocking pulse. For example, the pulse signal is input to the data signal line driving circuit 3 (more narrowly, the sampling signal generating unit 32). It is better to use the original clock signal CLK itself used to generate the timing signal to be generated or the pulse generated by dividing the frequency of the original clock signal CLK. As a result, the clock pulse can be generated without adding a special circuit for generating the pulse signal. In this case, the detection accuracy of the phase difference tp between the detection signals MON1 and MON2 is limited to the pulse application cycle of the original clock signal CLK, but as described above, the video signal D
Since the phase difference ta between the AT and the clock signal CKS is adjusted in units of the pulse application cycle of the original clock signal CLK,
Necessary and sufficient detection accuracy is obtained. As a result, the circuit configuration of the phase detector 13 can be simplified. In addition, unlike the case where another clock signal that is not synchronized with the original clock signal CLK is used as a clock pulse, the interference between the two clock signals does not occur and the image display device 1 is less likely to malfunction.
Can be realized.

In the above description, the case of counting the rising edge has been described as an example of the pulse counting method. However, the present invention is not limited to this.
The same effect can be obtained even when another counting method such as a falling edge or an edge of a pulse is used. In the present embodiment, for convenience of explanation, the detection signals MON1, MON2
The case where the rising point is detected will be described as an example, but the phase difference tp between the two detection signals MON1 and MON2 may be detected based on the falling point.

Incidentally, the detection signals MON1 and MON
2 is output from the data signal line driving circuit 3 formed on the same substrate as the pixel array 2 using a polycrystalline silicon thin film transistor, the two detection signals MON1 and MON
Since the transition characteristic of No. 2 is poor, the detection accuracy of the phase difference tp may be reduced.

On the other hand, in the image display device 1 according to the present embodiment, in order to improve the detection accuracy of the phase difference tp,
Between the data signal line drive circuit 3 and the phase detection unit 13, a conversion unit (conversion means) 11 for shortening the rise time of both detection signals MON1 and MON2 is provided. Hereinafter, the conversion unit 11 will be described with reference to FIGS.

That is, the conversion unit 11 according to the present embodiment
Is the rise time t of both detection signals MON1 and MON2.
is a circuit that converts s to a shorter time. For example, using a differentiating circuit, the waveform of the input signal is sharply converted.
This can be realized by using a clip circuit composed of a diode, a Zener diode, or the like to extract only a portion where the change of the input signal is sharp.

As a result, for example, as shown in FIG.
The detection signals (converted signals) MON1a and MON2a that rise in a time tsa shorter than the time ts are converted by the converter 11
Output from As a result, even if the detection signals MON1 and MON2 are dull to some extent, the phase detection unit 13 can make a determination using the detection signals MON1a and MON2a that have sharp changes, and can improve the detection accuracy of the phase difference tp.

Further, even if the driving capability of the circuit that outputs the detection signals MON1 and MON2 is low, the phase difference tp can be detected with high accuracy, so that the load on the output circuit can be suppressed. Further, since there is no need to improve the driving capability, an increase in power consumption accompanying the improvement in the driving capability can be reduced.
In addition, the tolerance of the load condition from the output of the detection signals MON1 and MON2 to the phase detection unit 13 can be improved.

Further, for example, the data signal line driving circuit 3
Is a monolithic driver using a polycrystalline silicon thin film transistor, its operating voltage is, for example, 10 V to
The voltage is about 16 V, which is higher than that of a device formed on a general single crystal silicon substrate. On the other hand, when the phase detection unit 13 is configured by the single crystal silicon-based device, the drive voltage operates at a relatively low voltage such as 5 V or 3 V.

Therefore, the conversion unit 11 detects the detection signal M using a diode or a Zener diode, for example.
ON1 and MON2 are clipped near the operating potential range,
If the amount of change in the detection signals MON1a and MON2a is suppressed,
The rated input condition of the phase detector 13 can be reliably satisfied. Thereby, the destruction of the phase detection unit 13 and the deterioration of characteristics can be prevented. In this case, it is not necessary to reduce the peak values of the detection signals MON1 and MON2 output from the data signal line driving circuit 3 in order to satisfy the rated input condition of the phase detection unit 13. Therefore, both detection signals MO
There is no need to provide a level shifter in the output circuit of N1.MON2, and even if it is provided, the shift amount can be reduced. As a result, the load on the output circuit can be reduced.

In addition, if the conversion unit 11 is constituted by a differentiating circuit and the data signal line driving circuit 3 and the conversion unit 11 are capacitively coupled, no current flows constantly. Therefore, the power consumption of the data signal line driving circuit 3 serving as an output circuit of the detection signals MON1 and MON2 can be reduced. Further, since the data signal line drive circuit 3 does not need to constantly output a current, the load on the data signal line drive circuit 3 is reduced, and the highly reliable data signal line drive circuit 3 can be realized.

For example, in the configuration example shown in FIG. 9, a capacitor C1 is provided between the input terminal IN and the output terminal OUT of the converter 11, and the output side of the capacitor C1 is connected via a resistor R1. And grounded, and connected to the power supply voltage VDD via the diode D1. Also,
The output side of the capacitor C1 is connected to the output terminal OUT via a diode D2, and the connection point between the diode D2 and the output terminal OUT is grounded via a resistor R2.

According to this configuration, the detection signal MON1 (MON2) input from the input terminal IN is output from the capacitor C
1 and a differential circuit composed of resistors R1 and R2, and output from an output terminal OUT as a detection signal MON1a (MON2a). Therefore, t1 shown in FIG.
As in the period from 1 to t12, the detection signal MON1a
(MON2a) rises with the rise of the detection signal MON1 (MON2). Further, at time t12, when the detection signal MON1 (MON2) rises and exceeds the power supply voltage VDD, the diode D1 serving as a clip circuit becomes conductive. Thus, the detection signal MON1 (MON
2) is clipped and the detection signal MON1a (MON2
a) is maintained at the predetermined power supply voltage VDD (t
12 or later).

While the diode D1 is conducting,
The voltage V1 on the anode side of the diode D1 is higher than the power supply voltage VDD by the forward voltage of the diode D1. However, between the anode side of the diode D1 and the output terminal OUT, to compensate for the voltage rise,
A diode D2 is provided, and the voltage V1 is output after being reduced by the forward voltage of the diode D2. Thus, while the diode D1 is conducting, the detection signal MON1a (MON2a) is maintained at the power supply voltage VDD.

As a result, the detection signal MON1a (MON2
The rise time tsa of a) corresponds to the detection signal MON1 (M
ON2) is shorter than the rise time ts. As an example of an actual operation waveform, as shown in FIG.
1, the detection signal MON1 (MON2) is about 2
While rising at about 40 ns, the detection signal MON output from the conversion unit 11 as shown in FIG.
1a (MON2a) rises in about 70 ns.

FIG. 9 shows an example of the configuration, and the conversion unit 1
A similar effect can be obtained if the input waveforms (detection signals MON1 and MON2) where 1 is dull can be converted to steep output waveforms (detection signals MON1a and MON2a). For example, the converter 11 may use a so-called transistor or a transistor with a built-in resistor.

The conversion unit 11 outputs the detection signals MON1 and M
Instead of changing ON2 to the detection signals MON1a and MON2a, the same effect can be obtained by lowering the threshold when the phase detector 13 detects the rise of the detection signals MON1 and MON2. In this case, as shown in FIG. 12, the conversion unit 11 is omitted, and the two detection signals MON1 and MON2 are directly applied to the phase detection unit 13. Further, the threshold value is set to be smaller than 電源 of the power supply voltage of the phase detector 13.

According to this configuration, the phase detection unit 13 detects the two detection points in a portion that changes relatively sharply immediately after the rise of the detection signals MON1 and MON2, as in the period from t11 to t12 shown in FIG. The application timing of the signals MON1 and MON2 can be detected, and the detection accuracy of the phase difference tp can be improved.

If the detection error of the phase detector 13 due to the dulling of the waveforms of the two detection signals MON1 and MON2 is small enough not to cause a decrease in display quality, the threshold value need not be set as described above. Is also good.

By the way, various timings can be considered as timings at which the timing control circuit 12 shown in FIG. 1 or FIG. 12 adjusts the phase difference ta between the clock signal CKS and the video signal DAT. Hereinafter, these timings will be described. That is, the timing control circuit 12 can adjust the phase difference ta as needed. However, in this case, before and after the adjustment of the phase difference ta,
Since the timing at which the sampling unit 31 samples the video signal DAT changes, the value of the video data D supplied to each pixel PIX may change, and the image displayed on the pixel array 2 may be disturbed.

Therefore, the timing control circuit 12
It is desired to adjust the phase difference ta at a timing when no image disturbance occurs. As an example of the timing, for example, before the image display device 1 starts displaying an image, the video signal D
A period during which an image based on the AT is not displayed on the pixel array 2 is exemplified. For example, when the image display device 1 is a transmission type, the timing control circuit 12 adjusts the phase difference ta before turning on the backlight. When the image display device 1 is of a reflection type, the timing control circuit 12 controls the video signal processing circuit (display means during phase difference adjustment) so as to keep the video signal DAT at a constant level for a predetermined period after power-on. 5, the display level of each pixel PIX is kept constant. In addition, a circuit capable of applying a constant level signal to each data signal line SL is provided in the data signal line driving circuit (display means at the time of phase difference adjustment) 3, and each pixel PI
The display level of X may be kept constant. At these timings, no image is disturbed because no image is displayed. Therefore, if the timing control circuit 12 adjusts the phase difference ta at these timings, the clock signal C is adjusted without giving the user a sense of incompatibility.
The phase difference ta between KS and the video signal DAT can be adjusted.

Another suitable timing is a point in time when the pixel array 2 switches the image. That is, generally, during the period (horizontal synchronization period) from the application of the pulse of the start signal SPS to the application of the next pulse, the pixel PIX connected to a certain scanning signal line GL
Video data D ₁ of the the to D _n are sequentially supplied in synchronization with the clock signal CKS. However, the last video data D _n
After There is output, by the first video data D ₁ is given by the following scanning signal lines GL, is provided with a certain period of time. Similarly, from the end of the selection of the last scanning signal line GL _m, even until given the next vertical synchronizing signal,
A certain period is provided. During these periods,
Since the sampling circuits AS _{1 to} AS _n do not sample the video signal DAT, the timing control circuit 12
By adjusting the phase difference ta during this period, the phase difference ta can be adjusted without causing image disturbance even while the image display device 1 is displaying an image. These periods can be easily identified from the start signal SPS, the vertical synchronization signal, and the like.

As described above, if the phase difference ta is adjusted when the pixel array 2 switches the image, the timing control circuit 12 can adjust the phase difference ta even during the display of the image without giving the user a sense of incongruity. . Therefore, even if the delay time td of the data signal line drive circuit 3 fluctuates due to a temperature change during operation or changes over time, the delay time td does not change.
, The phase difference ta can be adjusted.

By the way, when the timing control circuit 12 adjusts the phase difference ta, the phase detecting section 13 makes the two detection signals MO
If the number of times of detecting the phase difference tp of N1.MON2 is set to one and the phase detector erroneously detects the phase difference tp due to noise or the like, the phase difference ta between the clock signal CKS and the video signal DAT is correctly adjusted. become unable.

Therefore, when the timing control circuit 12 adjusts the phase difference ta, the phase difference t
The number of times p is detected is set to a plurality of times, and the phase adjustment unit 14 sets the clock signal CKS based on the phase difference tp detected a plurality of times.
By adjusting the phase difference ta between the signal and the video signal DAT, it is possible to prevent the occurrence of an error due to noise or the like. As a result, the phase difference ta between the clock signal CKS and the video signal DAT can be more reliably adjusted. Here, as a method of evaluating the detection results of a plurality of times, any evaluation method can be adopted as long as the influence of the erroneously detected phase difference tp can be eliminated.

In this embodiment, the clock signal CK is used.
The case of controlling the phase of S and the video signal DAT has been described as an example, but the present invention is not limited to this. For example, a circuit for individually controlling the phase of each sampling signal S may be provided in the data signal line driving circuit 3 for adjustment. Video signal DA
If the phase difference between T and each sampling signal S can be adjusted,
The same effect is obtained. However, controlling the phases of the clock signal CKS and the video signal DAT can simplify the circuit configuration as compared with the case where the phases of the sampling signals are individually controlled.

In FIGS. 4 and 5, block SD
Provided ₁ to SD _n similar dummy circuit (block SD _y), it has been described as an example the case of producing a detectable signal MON1 · MON2, not limited to this. The same effect can be obtained if the reference detection signal MON1 is output as the detection signal MON2 after passing through the delay circuit manufactured by the same process as the sampling signal generation unit 32. In this case, the delay circuit and the sampling signal generator 32
After they are manufactured in the same process, they may be separated on different substrates. However, when the sampling signal generator 32 and the delay circuit are arranged closer to each other, the temperatures of the two are closer, so that the delay amount td of the sampling signal generator 32 can be more accurately estimated. Further, when the circuit configuration of the delay circuit is the same as a part of the circuit of the sampling signal generation unit 32 like a dummy circuit, the two detection signals MON
The error in estimating the delay amount td from the phase difference tp of 1 · MON2 is reduced.

In the above embodiment, the image display device 1
As an example, an active matrix type liquid crystal display device driven in a dot sequence has been described, but the present invention is not limited to this. The present invention can be widely applied to any image display device provided with a data signal line driving circuit for sampling the video signal and extracting video data to each pixel.

[0113]

According to the first aspect of the present invention, there is provided an image display apparatus comprising:
As described above, a delay circuit composed of elements generated by the same process as the elements constituting the sampling signal generation unit, and a detection unit for measuring a delay time of the delay circuit,
A phase difference adjusting unit that adjusts a phase difference between the video signal and the sampling signal based on a detection result of the detecting unit.

According to the above configuration, since the delay time of the sampling signal generator and the delay time of the delay circuit change with substantially the same tendency, it is assumed that there is a difference in element characteristics between the respective sampling signal generators. Also, the phase difference between the video signal and the sampling signal can be adjusted without specifying the sampling signal or the timing signal corresponding to the video signal. As a result, there is an effect that an image display device capable of displaying an image with high quality can be realized with a simple circuit.

According to the image display device of the second aspect of the present invention, as described above, in the configuration of the first aspect of the present invention, the detecting means detects the timing of the delay circuit from the timing indicated by the reference signal serving as a reference. Until the timing indicated by the delay signal generated by delaying the reference signal, counting the number of pulse signals applied in a predetermined cycle,
This is a configuration for detecting the delay time of the delay circuit.

Therefore, as compared with the case of using an analog circuit, there is an effect that a highly accurate detecting means can be realized by a simple circuit.

According to a third aspect of the present invention, as described above, in the configuration of the second aspect, the frequency of the pulse signal is set to an integral multiple of the frequency of the timing signal. Configuration.

According to the above configuration, the interference between the pulse signal and the timing signal can be prevented, so that the display quality of the image display device can be further improved. In addition, since the timing signal can be generated without preparing a new clock signal, the configuration of the image display device can be simplified.

According to a fourth aspect of the present invention, as described above, in the configuration of the first, second or third aspect of the present invention, the change ends in a time shorter than the time when the delay signal changes. The conversion means for converting the delay signal into a conversion signal is provided in a stage preceding the detection means.

According to the above configuration, even if the delay signal output from the substrate is somewhat dull, the delay time can be detected with high accuracy based on the converted signal having a sharp change. As a result, there is an effect that the display quality can be further improved.
In addition, since the driving capability of the circuit that outputs the delay signal can be set lower, an effect of realizing an image display device with high reliability and low power consumption can be realized.

As described above, the image display device according to the fifth aspect of the present invention has the configuration according to the fourth aspect of the present invention, wherein the conversion means includes a differentiating circuit. In this configuration, no current flows between the input and output of the differentiating circuit in a steady state. Therefore, there is an effect that an image display device with lower power consumption and higher reliability can be realized.

According to a sixth aspect of the present invention, as described above, in the configuration of the fourth or fifth aspect of the present invention, the converting means inputs the level substantially equal to the power supply potential of the detecting means. This is a configuration including a clip circuit that clips a signal.

According to the above arrangement, even if the peak value of the delay signal exceeds the rated input condition of the detecting means, the converting means can use a relatively simple circuit to satisfy the rated input condition. A signal can be generated. As a result, there is an effect that the destruction of the detecting means and the characteristic deterioration can be prevented without increasing the power consumption.

According to a seventh aspect of the present invention, as described above, in the configuration of the first, second or third aspect of the present invention, the threshold value of the detecting means is set to be equal to the peak value of the delay signal. The configuration is set within 50%.

According to the above configuration, the detecting means can detect a change in the delay signal by using a steep portion immediately after the start of the change in the delay signal. Therefore, although the circuit configuration is simpler than that of the fourth aspect, similar to the fourth aspect, it is possible to improve the detection accuracy of the detection means without increasing power consumption.

As described above, in the image display apparatus according to the eighth aspect of the present invention, in the configuration of the first, second, third, fourth, fifth, sixth, or seventh aspect, the phase difference adjusting means is all provided. Before the pixels start displaying, the phase difference between the video signal and the sampling signal is adjusted.

Therefore, there is an effect that the phase difference can be adjusted without generating disturbance of the displayed image. Further, since the period during which the phase difference is adjusted is limited to the period during which no image is displayed, there is an effect that the power consumption of the image display device can be reduced as compared with the case where the phase difference is adjusted even during image display.

According to a ninth aspect of the present invention, as described above, in the configuration of the eighth aspect of the present invention, the phase difference adjusting means may be configured to output the video signal and the sampling signal before the light source is turned on. This is a configuration for adjusting the phase difference.

Therefore, an effect is obtained that an image display device capable of adjusting the phase difference without giving the user a sense of incongruity can be realized with a simple circuit.

An image display device according to a tenth aspect of the present invention is
As described above, in the configuration of the invention according to claim 8, at least the phase difference adjustment display means for displaying a fixed level image on the pixel array while the phase difference adjustment means adjusts the phase difference. It is a configuration provided with.

Therefore, in the reflection type image display device, it is possible to adjust the phase difference without giving the user a sense of incongruity, and to reduce the power consumption as compared with the case where the phase difference is constantly adjusted.

The image display device according to the eleventh aspect of the present invention
As described above, claims 1, 2, 3, 4, 5, 6, or 7
In the configuration of the invention described above, the phase difference adjusting means adjusts the phase difference during a period from when the last sampling circuit ends sampling the video signal to when the first sampling circuit starts sampling the video signal. It is a configuration to do.

According to the above configuration, since the phase difference is adjusted at the time of switching the image, no disturbance occurs in the displayed image. As a result, the image display device has an effect that the phase difference can be adjusted during display without giving the user a feeling of strangeness.

Further, since the phase difference is adjusted even during the display, even if the delay time fluctuates during the display, it follows the fluctuation,
The phase difference can be adjusted. As a result, the display quality of the image display device can be further improved.

The image display device according to the twelfth aspect of the present invention
As described above, claims 1, 2, 3, 4, 5, 6, 7,
In the configuration of the invention described in 8, 9, 10 or 11, the phase difference adjusting means adjusts the phase difference based on a result of the detection means detecting the delay time a plurality of times.

According to the above configuration, since the phase difference adjusting means adjusts the phase difference based on a plurality of detection results, the occurrence of a judgment error can be suppressed, and the display quality of the image display device can be further improved. It works.

[Brief description of the drawings]

FIG. 1 illustrates one embodiment of the present invention, and is a block diagram illustrating a main configuration of an image display device.

FIG. 2 is a block diagram showing the vicinity of a pixel array in the image display device.

FIG. 3 is a circuit diagram illustrating a configuration example of a pixel in the image display device.

FIG. 4 is a circuit diagram showing a configuration example of a data signal line driving circuit in the image display device.

FIG. 5 is a circuit diagram showing another configuration example of the data signal line driving circuit.

FIG. 6 is a timing chart showing the operation of the entire image display device.

FIG. 7 is a timing chart showing an operation of a phase detection unit in the image display device.

FIG. 8 is a waveform chart showing an operation of a conversion unit in the image display device.

FIG. 9 is a circuit diagram showing a configuration example of the conversion unit.

FIG. 10 is a waveform diagram showing an actual input waveform of the converter.

FIG. 11 is a waveform chart showing an actual output waveform of the converter.

FIG. 12 is a block diagram showing a modification of the image display device and showing a configuration of a main part of the image display device.

FIG. 13 shows a conventional example, and is a block diagram illustrating a main configuration of an image display device.

FIG. 14 is a circuit diagram showing a configuration example of a data signal line driving circuit in the image display device.

FIG. 15 is a circuit diagram showing another configuration example of the data signal line driving circuit in the image display device.

FIG. 16 shows the operation of the image display device.
9 is a timing chart in a case where a data signal line driving circuit instructs acquisition of video data at a correct timing.

FIG. 17 shows the operation of the image display device,
6 is a timing chart showing a case where a video data acquisition instruction is late.

FIG. 18 shows the operation of the image display device.
6 is a timing chart illustrating a case where an instruction to acquire video data is too early.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Image display apparatus 2 Pixel array 3 Data signal line drive circuit (display means at the time of phase adjustment) 5 Video signal processing circuit (display means at the time of phase difference adjustment) 11 Conversion part (conversion means) 13 Phase detection part (detection means) 14 Phase adjuster (phase difference adjusting means) 31 sampling section 32 samples the signal generating unit AS ₁ ~AS _n sampling circuits C1 capacitor (differentiating circuit) D1 diode (clipping circuit) G2 inverter (delay circuit) PIX pixel R1 · R2 resistor (differentiating circuit CKS clock signal (timing signal) CLK original clock signal (pulse signal) DAT video signal MON1 detection signal (reference signal) MON2 detection signal (delay signal) MON1a / MON2a detection signal (conversion signal)

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Yasushi Kubota 22-22, Nagaike-cho, Abeno-ku, Osaka-shi, F-term in Sharp Corporation (reference) 5C006 AA11 AA22 AC02 AC11 AF72 AF81 BB16 BC12 BF04 BF26 BF27 BF36 BF37 FA16 FA29 5C080 AA10 BB05 CC03 DD01 DD30 EE29 FF11 GG09 JJ02 JJ03 JJ04 JJ05

Claims (12)

[Claims] 1. An image display device comprising: a sampling circuit for sampling a video signal based on a sampling signal; and a sampling signal generating unit for generating the sampling signal based on a timing signal indicating a supply timing of the video signal. A delay circuit composed of elements generated by the same process as the elements constituting the sampling signal generation unit; detection means for measuring a delay time of the delay circuit; and a video signal based on a detection result of the detection means. An image display device comprising: a phase difference adjusting unit that adjusts a phase difference between the sampling signal and the sampling signal. 2. The method according to claim 1, wherein the detecting means is applied at a predetermined period from a timing indicated by a reference signal serving as a reference to a timing indicated by a delay signal generated by delaying the reference signal by the delay circuit. 2. The image display device according to claim 1, wherein the delay time of the delay circuit is detected by counting the number of pulse signals. 3. The image display device according to claim 2, wherein the frequency of the pulse signal is set to an integral multiple of the frequency of the timing signal. 4. The sampling signal generation section and the delay circuit are formed on the same substrate as the substrate on which the pixels are formed, and a delay signal output from the delay circuit to the outside of the substrate is sent to the detection means. 2. A conversion means for converting the delay signal into a conversion signal whose change ends in a shorter time than the time when the delay signal changes, before being input. 4. The image display device according to 2 or 3. 5. The image display device according to claim 4, wherein said conversion means includes a differentiating circuit. 6. The image display device according to claim 4, wherein said conversion means includes a clip circuit for clipping an input signal to a level substantially equal to a power supply potential of said detection means. 7. The sampling signal generation section and the delay circuit are formed on the same substrate as the substrate on which the pixels are formed, and the detection means includes a delay signal output from the delay circuit to outside the substrate. Detects a delay time of the delay circuit based on a time point when a predetermined threshold value is exceeded, and the threshold value of the detection means is 5 times the peak value of the delay signal.
2. The method according to claim 1, wherein the value is set within 0%.
4. The image display device according to 2 or 3. 8. The apparatus according to claim 1, wherein said phase difference adjusting means adjusts the phase difference between the video signal and the sampling signal before all the pixels start displaying.
The image display device according to 5, 6, or 7. 9. The image display according to claim 8, wherein said phase difference adjusting means adjusts the phase difference between the video signal and the sampling signal before the light source of the light emitted from the pixel is turned on. apparatus. 10. A reflection-type pixel array capable of controlling a display state of each pixel in accordance with an output of said sampling circuit, and at least while said phase difference adjusting means adjusts a phase difference, said pixel array includes: 9. The image display apparatus according to claim 8, further comprising a phase difference adjustment display unit for displaying a video of a fixed level. 11. The phase difference adjusting means adjusts the phase difference during a period from when the last sampling circuit finishes sampling the video signal to when the first sampling circuit starts sampling the video signal. The image display device according to claim 1, 2, 3, 4, 5, 6, or 7. 12. The apparatus according to claim 1, wherein said phase difference adjusting means adjusts the phase difference based on a result of detecting said delay time a plurality of times by said detecting means.
The image display device according to 5, 6, 7, 8, 9, 10 or 11.