JP2000023163A - Motion vector detection device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reduce the amount of calculation by thinning out pixels used for block matching calculation in motion vector search, and to greatly reduce the circuit scale of a data delay unit installed between calculation units. I do. SOLUTION: An encoded pixel value is stored in an encoding memory 1 and then inputted to PEs 6 and 7 in block units in a horizontal direction. The reference pixel value is stored in the reference memory 2, input to the reference registers 4 and 5, and input to the PEs 6 and 7. PE6
In, the absolute value of the difference between the outputs of the reference registers 4 and 5 and the coded pixel value is calculated. In PE7, a differential absolute value operation is performed, and P
The result of addition with the result of the difference absolute value calculation of E6 is output.
AE of coded block and prediction block candidate from PE7
Is output.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motion vector detecting device for detecting a motion vector used in motion compensation coding of a moving image by a block matching method, and more particularly, to a method of detecting the number of pixels used for matching by subsampling. The present invention relates to a motion vector estimating device that reduces the number of operations and the circuit scale.

[0002]

2. Description of the Related Art In recent years, MPE has been used as a moving picture coding method.
G1 (ISO / IEC 11172), MPEG2 (I
An interframe coding method using motion compensation prediction such as SO / IEC 13818) is used in the fields of storage, communication, and broadcasting. In these methods, motion-compensated prediction is performed in which each image of a moving image sequence is divided into coding blocks, and a prediction block is obtained using a motion vector detected from a reference image for each coding block.

As a method of detecting a motion vector, a block matching method is known. In the block matching method, the amount of error between a coded block and a predicted block candidate having the same size as the coded block is calculated within the motion vector search range. Then, the candidate with the smallest error amount is set as the prediction block, and the relative shift amount of the prediction block position from the coded block position is set as the motion vector.

Here, assuming that the error amount is a sum of absolute differences (hereinafter referred to as AE) between a pixel in a coding block and a pixel in a search range, AE is represented by equation (1).

[0005]

(Equation 1)

In equation (1), Rx, y is reference pixel data, Tx
x, y is coded pixel data, and AEi, j indicates an error amount from a prediction block candidate whose motion vector is (i, j) when the number of pixels of the coded block is H horizontal pixels × V vertical pixels. I have. The search range of the motion vector is -K to (K-
1), -L to (L-1) in the vertical direction.

As a motion vector detecting device based on the block matching method, Japanese Patent Application Laid-Open No. 10-1 filed by the present applicant has been proposed.
There is a technique described in Japanese Patent No. 36377. FIG. 19 shows a block diagram of a motion vector detecting device described in Japanese Patent Application Laid-Open No. 10-136377. FIG. 11 shows an example in which the block size of the coding block is 4 pixels × 4 pixels. FIG. 19 shows a plurality of processing units (PEs in the figure) 105 to 112 and a data delay unit (12 in the figure) installed between the processing units.
D) 113 to 118 and reference registers (R in the figure) 101 to 104 for holding reference pixel values while sequentially shifting them. The pixel value of the encoded block (hereinafter, referred to as an encoded pixel value) is input from a terminal 119, and the reference pixel value is input from a terminal 120.

FIG. 20 shows the structure of the PE shown in FIG. PE
Are encoding registers 123 to 12 for storing encoded pixel values.
6, difference absolute value calculators 127 to 130, adder 131,
132. One column of coded pixel values is stored in the coding registers 123 to 126, while the outside of FIG.
9 are sequentially input from the reference registers 101 to 104, and the difference absolute value calculators 127 to 130 calculate the error amount between one column of the coded pixel values and one column of the reference pixel values.
The signals are added by the adders 131 and 132 and output. Each PE
Are sequentially cumulatively added by the subsequent PEs.

Hereinafter, as shown in FIG. 21A, the number of pixels of the coding block is 4 pixels in the horizontal direction × 4 pixels in the vertical direction.
The operation of the conventional example when the search range of the motion vector is −4 to +3 in the horizontal direction and −4 to +3 in the vertical direction as shown in FIG.

FIG. 22 shows the relationship between encoded pixels stored in the encoding register and reference pixels input from the reference register. Since the encoding registers 123 to 126 have four pixels for one PE and eight PEs 105 to 112,
There is a capacity of 2 blocks of encoded pixels (4 × 8 images),
The error calculation of two encoded blocks is performed simultaneously. Each PE stores encoded pixel values for one column (4 pixels), and every time an encoded pixel value is input for one column, the reference pixel value for one column (12 pixels) is also stored.
Pixel). While the reference pixel value is input, the encoded pixel value is held in the encoding register. The relationship between the reference pixel and the encoded pixel is always the positional relationship shown in FIG. 22, and the sum of absolute differences between the encoded pixel value held in each PE and the input reference pixel value is calculated. Can be

FIGS. 23 and 24 show timing charts in which the error amounts are cumulatively added. 23 is followed by FIG. 24, and the symbols of the pixels in the figure use those shown in FIG. As the coded pixel value, one column (4 pixels) is input from the terminal 119 in FIG. 19 every 12 clocks. First, the coded pixel values t0, t1, t2, and t3 are set to PE at [time T = 0 to 3].
105, and the encoded pixel values t4, t5, t6, t
7 is input to the PE 106 at [T = 12 to 15]. The reference pixel value is input in the order of r0, r1,... From the terminal 120 in FIG. At this time, one pixel of dummy data is inserted in 12 clock cycles, such as r0, r1, r2,... R10, dummy data, r11, r13,.

First, when the reference pixel values for four clocks are input, the outputs of the reference registers 101 to 104 become (r
0, r1, r2, r3) [T = 4]. Therefore, P
Inside E105, d0 = | r0−t0 | + | r1−t1 | + | r2−t2 | + | r3−t3 | [T = 4] is collectively calculated and becomes the output of the PE 105. Here, d0 corresponds to a portion related to the coded pixel values t0 to t3 in the AE calculation of the motion vector (−4, −4). At the next clock [time T = 5], the reference registers 101 to 101
While the output of 104 is (r1, r2, r3, r4), the input of the encoded pixel value is not performed, and the encoded pixel values stored in the encoding registers 123 to 126 in the PE 105 remain at t0 to t3. Therefore, in the PE 105, d1 = | r1-t0 | + | r2-t1 | + | r3-t2 | + | r4-t3 | [T = 5] is calculated. d1 is A of the motion vector (-4, -3)
This corresponds to a portion related to the coded pixel values t0 to t3 in the E calculation. The above processing is continued, and PE 105 in FIG.
0 to d7 are sequentially output and input to the data delay unit 113.

The data delay unit 113 inputs d0 to d7 to the PE 106 in order from [T = 16] after 12 clocks. In the PE 106, the outputs of the encoding registers 123 to 126 are (t4, t5, t6, t7), and the reference registers 101 to 105 are (r11, r12, r13,
r14). Then, e0 = d0 + | r11−t4 | + | r12−t5 | + | r13−t6 | + | r14−t7 | [T = 16] is the output of the PE 106. e0 is the motion vector (-
In the AE calculation of (4, -4), it corresponds to a portion related to the coded pixels t0 to t7. In this way, the error amount is accumulated for each column, and the PE 108
(H0 to h7) are output.

Incidentally, PE105 to PE108 and PE10
9 to PE 112 perform AE calculation of adjacent encoded blocks in parallel. Then, the encoded pixel 1 is output every 12 clocks.
Since columns are input, the input of one encoded block (four columns) ends every 48 clocks, and the input of the next encoded block starts.

[0015]

Problems to be Solved by the Invention
Japanese Patent Publication No. 77 describes an apparatus for reducing the circuit scale by thinning out pixels used for error calculation of one candidate block. For example, as shown in FIG.
If the error value is determined only for the coded block pixel which is sub-sampled to と も に in both the vertical direction, FIG.
The circuit shown in FIG. 6 can calculate the absolute difference. In FIG. 26, 133 to 136 are arithmetic units,
137 is an input terminal for inputting a coded pixel, 138 is an input terminal for inputting a reference pixel, 139 and 140 are output terminals for outputting absolute difference values, and 101 to 104, 113, 11
4, 116 and 117 are the same circuits as in FIG. FIG.
In FIG. 6, the number of PEs is reduced by half and the number of data delay units is reduced by two compared to FIG. Further, PEs 133 to 136 are circuits shown in FIG.
The differential absolute value calculators 143 and 144 and the adder 145 are provided, and the circuit scale is about half as compared with the PE shown in FIG.

However, the delay amount of each data delay unit is the same as before the sub-sampling of the coding block. In the embodiment of the patent described in JP-A-10-136377, the data delay unit delays input data by 12 clocks. This is the sum of the number of candidate points 8 for the vertical motion vector and the number 4 of pixels of the coding block in the vertical direction, and is the same even when sub-sampling is performed. A value generally used in MPEG2, for example, when the size of an encoded block is 1
If the search range of the motion vector in the vertical direction is -16 to +15 pixels, the coding block is 1
8 PEs even when sub-sampled to / 2
In this case, 2 × 7 = 14 data delay units are provided, and each data delay unit delays input data by 48 clocks. Assuming that the input data to the data delay unit is 10 bits, the total capacity of the data delay unit is 48 × 14 × 10 = 6,720 bits. Generally, the data delay unit has a register configuration,
The 6,720-bit register has a problem that the circuit scale is very large.

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and reduces the amount of calculation by thinning out pixels used for block matching calculation in a motion vector search, and provides a data delay unit provided between calculation units. It is an object of the present invention to provide a motion vector detecting device capable of greatly reducing the circuit size of the motion vector detecting device.

[0018]

According to the present invention, block matching is performed for all prediction block candidates in a search area by using representative pixel values subsampled in a predetermined pattern among pixels constituting an encoding block. , A motion vector estimating apparatus for estimating a motion vector by finding a prediction block that best matches a coding block.

According to a first aspect of the present invention, there is provided an encoding memory for storing an encoded block, a reference memory for storing a reference image value of a prediction block candidate, and a memory controller for controlling input / output of the encoding memory and the reference memory. A reference register for storing a reference pixel value of the reference memory, a plurality of data delay units for delaying data output timing, and a plurality of operation units connected in series via the data delay unit. The memory controller distributes and outputs the representative pixel value of the sub-sampled encoded block from the encoding memory to the arithmetic unit,
Based on the sub-sampling pattern, read a reference pixel value of a prediction block candidate corresponding to a representative pixel value of the coding block from the reference memory, and store the reference pixels of all prediction block candidates in a search area in the reference register. Enter the values in order. The arithmetic unit holds a pixel value of the subsampled encoded block, and calculates an error amount between a pixel value of the encoded block and a pixel value of the reference register corresponding to the pixel value. Do
These error amounts are cumulatively added to output values of other arithmetic units. The data delay unit adjusts the output timing such that the error value output from the preceding operation unit is cumulatively added to the error amount in the same prediction block candidate by the subsequent operation unit. Then, a motion vector is determined using a prediction block candidate having the minimum value among the error amounts output from the last-stage arithmetic unit as a prediction block.

According to a second aspect of the present invention, in the motion vector detecting device according to the first aspect, two sets of the plurality of data delay units and the plurality of arithmetic units are provided, and one set of the arithmetic units is already inputted. The memory controller holds the representative pixel value of the coding block being used, and causes the other set of arithmetic units to output the representative pixel value of the coding block adjacent to the coding block from the coding memory. The arithmetic unit performs an arithmetic operation on a reference pixel of a common prediction block candidate and the representative pixel value.

According to a third aspect of the present invention, in the motion vector detecting device according to the first aspect, two sets of the plurality of data delay units and the plurality of arithmetic units are provided, and the memory controller is provided with one set of the arithmetic units. Causes the representative pixel value of one encoded block to be output from the encoding memory, and the other set of arithmetic units stores the representative pixel value of every other encoded block with respect to the encoded block. , And the two sets of arithmetic units perform an arithmetic operation on the reference pixel of the common prediction block candidate and the representative pixel value.

According to a fourth aspect of the present invention, there is provided the motion vector detecting device according to the first, second or third aspect, wherein the arithmetic unit comprises a number M of encoded pixels on one side of the sub-sampled encoded block. M encoding registers for storing values, M difference absolute value calculators for calculating the absolute value of the difference between the encoded pixel value and the pixel value of the reference register corresponding to the pixel value, An adder for adding the output of the arithmetic unit and the outputs of the M difference absolute value arithmetic units.

According to a fifth aspect of the present invention, there is provided the motion vector detecting device according to the fourth aspect, wherein the number of the reference registers is 2M, and further comprising a selector for selecting and outputting M data from the reference registers, The selector selects only valid M register outputs and supplies them to the arithmetic unit.
An error calculation in a search range overlapping between coding blocks is performed by a common calculation unit by time division.

According to a sixth aspect of the present invention, in the motion vector detecting device according to the first aspect, the arithmetic unit stores the coded pixel values of the number M of pixels on one side of the sub-sampled coded block. M first encoding registers, M second encoding registers for storing M encoded pixels of an encoding block adjacent to the encoding block including the encoded pixel value, and a total of 2M A selector for selecting M register outputs from the first and second encoding registers;
And an adder for adding an output of another arithmetic unit and an output of the absolute difference calculator. The number of the reference registers is 2M, and a selector for selecting and outputting M data from the reference registers is provided. Then, the selector selects only valid M register outputs and supplies them to the arithmetic unit, and performs an error operation in a search range overlapping between coding blocks by time sharing in a common arithmetic unit. I do.

The invention of claim 7 is the invention of claim 4, 5, or 6.
The motion vector detection device according to claim 1, wherein a difference square calculator is used instead of the difference absolute value calculator.

[0026]

Embodiments of the present invention will be described below in detail with reference to the drawings.

<First Embodiment> FIG. 1 is a block diagram showing a first embodiment of a motion vector detecting device according to the present invention. In the conventional example shown in FIG. 26, two sets of operation units connected in series via two data delayers of 12 clocks are provided, and each operation unit performs error calculation of one encoding block, and The error calculation of the coding block was performed simultaneously. On the other hand, in the present embodiment, the input order of the reference pixels is optimized and the reference pixels are input at high speed, so that the ones connected in series via the 5-clock data delay unit
It is characterized in that processing is performed only by a set of arithmetic units. In this embodiment, the number of arithmetic units is reduced by half compared to the conventional example, and four 12-clock data delay units are replaced by one 5-clock data delay unit.

Hereinafter, as in the conventional example, the size of the coding block is 4 pixels horizontally and 4 pixels vertically, and the search range of the motion vector is -4 to +3 pixels in the horizontal direction and -4 to +3 in the vertical direction.
A pixel is set as a pixel, and a matching operation is performed between a reference pixel and a pixel obtained by subsampling the coding block in both the horizontal and vertical directions in the same manner as in FIG. 25 shown in the conventional example, and the matching operation is the sum of absolute differences (AE) Will be described.

This motion vector detecting device includes a coding memory 1 for storing a coding block, a reference memory 2 for storing a reference block, a memory controller 3 for controlling the input / output of the coding memory 1 and the reference memory 2, and a serial memory. , And arithmetic units (hereinafter referred to as PEs) 6, 7 connected in series via a data delay unit 8. The PEs 6 and 7 receive the coded pixel values from the coding memory 1 and the outputs of the reference registers 4 and 5 in common.

FIG. 2 is a block diagram of the PE in FIG.
Each of the PEs 6 and 7 includes encoding registers 21 and 22, absolute difference calculators 23 and 24, and an adder 25. The coding registers 21 and 22 receive the coded pixel values from the coding memory 1, and the difference absolute value calculators 23 and 24 calculate the difference absolute value between the coded pixel value and the reference pixel value input from an external reference register. , And the adder 25 outputs the sum of the absolute difference value and the input from the previous stage.

FIG. 3 is a timing chart showing the operation of the reference registers 4, 5 and the PEs 6, 7 in the embodiment shown in FIGS. 1 and 2. The operation will be described with reference to FIGS. . In FIG. 3, the symbols of the pixels are the symbols shown in FIG. In the conventional example, the coded pixel and the reference pixel are input in the vertical direction, but in the present embodiment, they are input in the horizontal direction.

First, the input order of the coded pixel value and the reference pixel value will be described with reference to FIGS. The coded pixel values are temporarily stored in the coding memory 1 of FIG. 1 and then input to the PEs 6 and 7 in the horizontal direction in block units. In the case of the sub-sampling pattern shown in FIG.
t8, t2, and t10 are input in this order, and t0 and t8 are PEs.
6, and t2 and t10 are stored in PE.
7 is stored in the encoding register.

On the other hand, the reference pixel value is temporarily stored in the reference memory 2 shown in FIG.
5 is input. FIG. 4 shows a pattern based on the sub-sampling pattern of the coded pixels shown in FIG. Pixels are input, and reference pixel values are input with reference points shifted in the order of 1 ″, 1 ′ ″, and input of 10 pixels × 10 pixels, which are all pixels in the reference pixel readout range shown in FIG. 4, is completed. I do.

With this reference pixel input, reference pixels corresponding to all the prediction block candidates in the range of -4 to +3 in the horizontal direction and -4 to +3 in the vertical direction are input. Since the matching operation is performed on the coded pixels subjected to the sub-sampling, the reference pixel readout range is a range slightly smaller than the search range.

In the time chart of FIG. 3, first, the encoding memory 1 outputs t0, t8, t2, and t1 shown in FIG.
The pixel values of the first coding block are input in the order of 0, and t
0 and t8 are stored in the encoding register in PE6, and t
2 and t10 are stored in the encoding register in the PE 7 [time T = 0 to 3]. The coding block is held in the coding register until the next coding block is input.
On the other hand, from the reference memory 2, the reference registers 4 and 5 store r0, r22, r44, r66,
r88 (the symbol of the pixel is shown in FIG. 21B) is input [T = 0 to 4], and the outputs of the reference registers 4 and 5 are also input to the PEs 6 and 7 every clock.

In PE6, the reference register 4,
5 and the encoded pixel values t0 and t8 are calculated. Therefore, the output data of PE6 is: d0 = | t0-r0 | + | t8-r22 | [T = 2] d22 = | t0-r22 | + | t8-r44 | [T = 3] d44 = | t0-r44 | + | T8−r66 | [T = 4] d66 = | t0−r66 | + | t8−r88 | [T = 5]

When the input of the reference pixel value in the first row (5 pixels) is completed, the reference registers 4 and 5 store r2 and r2 in the third row.
r24, r46, r68, and r90 are input, and the outputs of the reference registers 4 and 5 are also input to the PEs 6 and 7 sequentially. P
At E6, a difference absolute value operation from t0 and t8 is performed, and PE
At 7, the difference absolute value calculation with t2 and t10 is performed, and the result of addition with the difference absolute value calculation result of the preceding stage (PE6) delayed by 5 clocks by the data delay unit 8 in FIG. 1 is output.

Therefore, the output data from PE6 is d2 = | t0-r2 | + | t8-r24 | [T = 7] d24 = | t0-r24 | + | t8-r46 | [T = 8] d46 = | t0-r46 | + | t8-r68 | [T = 9] d68 = | t0-r68 | + | t8-r90 | [T = 10] The output data from PE7 is e0 = d0 + | t2-r2 | + | t10-r24 | [T = 7] e22 = d22 + | t2-r24 | + | t10-r46 | [T = 8] e44 = d46 + | t2-r46 | + | t10-r68 | [T = 9] e66 = d68 + | t2-r68 | + | t10-r90 | [T = 10]

E0 is the AE of the coded block with the predicted block candidate whose motion vector is (-4, -4), e22 is (-2, -4), e44 is (0, -4),
e66 is the AE with the (2, -4) prediction block candidate. In this way, the result of PE6 is further cumulatively added by PE7, and AE of the coded block and the prediction block candidate is output from PE7.

Referring to the pattern shown in FIG.
After 5 is input, the reference pixel value is sequentially input by shifting the base point to the right by one pixel (r11, r3 in FIG. 21B).
[T = 25-]. Similarly, input of the reference pixel value is continued by further shifting the base point, and the time [T = 9
9], the input of reference pixel values for 10 pixels × 10 pixels = 100 pixels ends. Then, among the AEs of the prediction block candidates, the block having the minimum AE is selected as the prediction block.

The above operation, that is, 10 operations for inputting the pixel value of one encoded block and inputting the reference pixel of 100 pixels is performed.
The process of 0 clock is repeated, and the prediction block of the encoding block is sequentially selected. As described above, it is possible to realize a motion vector detecting device having a very small circuit scale with a small delay amount of the differential absolute value calculator and the data delay unit while having the same motion vector detecting performance as the conventional example.

<Second Embodiment> FIG. 5 is a block diagram showing a second embodiment of the motion vector detecting device according to the present invention. The present embodiment has a configuration in which the error calculation of two adjacent coding blocks is performed at the same time as in the conventional example shown in FIG. 26, but the conventional example has four delay units of 12 clocks. On the other hand, the present embodiment is characterized in that only two delay units of three clocks are provided.

This motion vector detecting device includes an encoding memory 1, a reference memory 2, an encoding memory 1 and a reference memory 2.
, PEs 6, 7 and 32, 33 connected in series via data registers 34, 35 and reference registers 4, 5, respectively. PE6
7, 32, and 33 have the same configuration as the PE shown in FIG. FIG. 6 is a timing chart showing the operation of the reference registers 4, 5 and PEs 6, 7, 32, 33 in the embodiment shown in FIG. 5, and the operation will be described with reference to FIGS. 6, 7, and 8. In FIG. 6, the symbols of the pixels are shown in FIG.
Use the symbol shown in.

First, the input order of the coded pixel value and the reference pixel value will be described with reference to FIGS. The encoded pixel values are temporarily stored in the encoding memory 1 in FIG. 5 and then input in the horizontal direction in block units. For example, in the case of the coding block 0 in FIG. 8, the input is performed in the order of t0, t8, t2, and t10. The coding registers of PEs 6 and 7 store the coding block 0, the coding registers of PEs 32 and 33 store the adjacent coding block 1, and the PE always holds two coding blocks. You.

On the other hand, the reference pixel values are inputted to the reference registers 4 and 5 in the unit of six columns in the pattern shown in FIG. FIG. 7 shows a pattern based on the sub-sampling pattern of the coded pixels shown in FIG. 25. First, reference pixel values 1 to 15 are input in numerical order, and then the base point is shifted by one pixel to 1 ′ to 1 ′. 15 ′ is input, and reference pixel values are input sequentially shifted from the base point to 1 ″, 1 ′ ″. During the period in which the coding blocks a and b in FIG. 7 are held in the PE, six columns and 60 pixels of 1 to 15 ″ ′ indicated by the reference pixel reading range in FIG. A reference pixel value corresponding to a prediction block candidate in the range of -4 to -1 in the horizontal direction and -4 to -3 in the vertical direction of the coded block b is input. Will be done.

For one coded block, the reference pixel values corresponding to all the prediction block candidates are input twice as the reference pixel values for six columns, and the range of the motion vector is the first reference pixel value. Input Horizontal direction −4 to −1, vertical direction −4 to +3 Second reference pixel value input Reference pixel values corresponding to prediction block candidates in horizontal direction 0 to +3 and vertical direction −4 to +3 are input. Also in this case, since the error calculation is performed on the coded pixels subjected to the sub-sampling, the reference pixel read range is a range slightly smaller than the search range.

After the input of the reference pixel values for the six columns is completed, the coding block on the right side is input, and the reference pixel values for the six columns are input from the position shifted to the right by four columns. This is shown in FIG. First, r0 to r64 are changed to r as shown in FIG.
0, r22, r44,... (It is not necessary to input the reference pixel value at the lowermost stage because sub-sampling is performed).
, R66, r88,...

In FIG. 6, the encoding memories 1 to t0, t0,
The first coding block is input in the order of t8, t2, and t10, t0 and t8 are stored in the coding register in PE6, and t2 and t10 are stored in the coding register in PE7 [time T = 0 ~ 3]. Next, t16, t24, t1
The next coded block is input in the order of 8, t26, and t1
6, t24 are stored in the encoding register in PE32,
t18 and t26 are stored in the encoding register in the PE 33 [T = 4 to 7], and the encoding registers in the PEs 6, 7, 32, and 33 store the encoded pixel values for a total of two blocks. Thereafter, the coded pixel values are updated in units of one block, and the coded pixel values of two blocks are always held in the PE.

After inputting the coding block pixels at t0, t8, t2, and t10, the reference registers 4 and 5
, The first row of reference pixel values r0, r22, and r44 are input [T = 4 to 6], and the outputs of the reference registers 4 and 5 are input to the PE. At time PE6, from time T6, the absolute difference between the outputs of the reference registers 4 and 5 and the coded pixel values t0 and t8 is calculated. Therefore, the output data of PE6 is as follows: d0 = | t0−r0 | + | t8−r22 | [T = 6] d22 = | t0−r22 | + | t8−r44 | [T = 7] In the PE 32, the coded pixel values t16, 24
Is calculated, and g0 = | t16−r0 | + | t24−r22 | [T = 6] g22 = | t16−r22 | + | t24−r44 | [T = 7] is output. .

When the input of the reference pixel value in the first row (three pixels) is completed, the reference registers 4 and 5 store r in the third row.
2, r24 and r46 are input, and the outputs of the reference registers 4 and 5 are sequentially input to the PE. PE6 continues t
The absolute value of the difference between 0 and t8 is calculated.
The difference absolute value calculation with respect to 2 and t10 is performed, and the result of addition with the difference absolute value calculation result of the preceding stage (PE6) delayed by 3 clocks by the data delay unit 34 is output.

Therefore, the output data from PE6 becomes d2 = | t0-r2 | + | t8-r24 | [T = 9] d24 = | t0-r24 | + | t8-r46 | [T = 10], and PE7 The output data from is as follows: e0 = d0 + | t2-r2 | + | t10-r24 | [T = 9] e22 = d22 + | t2-r24 | + | t10-r46 | [T = 10] The reference pixel value is also input to PEs 32 and 33, and P
The output data of E32 is g2 = | t16−r2 | + | t24−r24 | [T = 9] g24 = | t16−r24 | + | t24−r46 | [T = 10] The output data from the PE33 is h0 = d0 + | t18-r2 | + | t26-r24 | [T = 9] h22 = d22 + | t18-r24 | + | t26-r46 | [T = 10]

E0 is the AE of the coded block with the predicted block candidate whose motion vector is (0, -4), e2
2 is the AE with the predicted block candidate of (2, -4).
H0 is the AE of the coded block 1 with the predicted block candidate whose motion vector is (−4, −4), h22
Is the AE with the (-2, -4) prediction block candidate.
In this way, the result of PE6 is further cumulatively added by PE7, the result of PE32 is further cumulatively added by PE33,
The PEs 7 and 33 output AEs of the encoded blocks 0 and 1 and the prediction block candidates, respectively.

Reference image values 1 to 1 in the pattern shown in FIG.
After 5 is input, the base point is shifted 1 pixel to the right by 1 '.
, Sequentially input reference pixel values 1 ′ to 15 ′ (corresponding to r11, r33,... In FIG. 8) [T = 19 to]. Similarly, input of reference pixel values is continued by further shifting the base point, and input of reference pixel values of 60 pixels for six columns at time [T = 63] ends. The error calculation for the prediction block candidates in the entire search range is completed by inputting the reference pixel values for six columns for one block twice, and among the AEs of the prediction block candidates,
The block having the minimum AE is selected as the prediction block. By repeating the above operation every 60 clocks, a prediction block of an encoded block is sequentially selected.

As described above, two sets of a plurality of operation units connected in series via a data delay unit are provided, and the representative pixel of one coded block is input from the coding memory to one of the operation units. The encoding register in the set of operation units holds the representative pixel of the two adjacent encoding blocks of the newly input representative pixel and the already input representative pixel, and stores the representative pixels of the two adjacent encoding blocks. Perform error calculation simultaneously. With one reference pixel input, of the two adjacent encoded blocks, the left encoded block performs an error operation with the right predicted block candidate group within the search range, and the right encoded block is searched. A reference pixel is input from the reference memory so as to perform an error operation with respect to the left prediction block candidate group in the range. By performing the error calculation with the prediction block candidates in the entire search range by two reference pixel inputs, the delay amount of the data delay unit is small and the circuit scale is very large while having the same motion vector detection performance as the conventional example. A small motion vector detecting device can be realized.

In the present embodiment, the number of PEs and data delays is doubled as compared with the first embodiment, but the delay amount of the data delay is five clocks in the first embodiment. On the other hand, in the present embodiment, the number of clocks is as small as 3 clocks, and in the first embodiment, 100 clocks are required for the error calculation of one encoded block. Since the error calculation for one encoded block is completed, the operating frequency can be further reduced.

<Third Embodiment> FIG. 9 is a block diagram showing a third embodiment of the motion vector detecting device according to the present invention. In the second embodiment, two sets of PEs connected in series via a data delay unit are provided, and the matching operation of two adjacent encoded blocks is performed in parallel. Then, every other encoded block is processed in parallel. In the second embodiment, the search range of the motion vector is −4 to +3 in the horizontal direction. On the other hand, in the present embodiment, the data delay unit is changed from 3 clock delays to 5 clock delays, and one encoding is performed. By changing the reference pixel readout range per block from 6 columns to 10 columns, a characteristic feature is that a wide range from −8 to +7, which is twice that of the second embodiment, can be searched.

This motion vector detecting device is different from the motion vector detecting device of the second embodiment shown in FIG.
The control of the memory controller 41 and the data delay unit 42,
The other operations are the same except for the amount of delay. FIG. 10 shows reference registers 4 and 5 in the present embodiment.
And the operations of PEs 6, 7, 32, and 33 are shown in a timing chart. This is an example where the motion vector search range is -4 to +3 in the vertical direction and -8 to +7 in the horizontal direction.
The readout of the reference pixels in the present embodiment is the same as the readout in the first embodiment shown in FIG.
The reading of the coded pixels is different.

FIG. 11 shows the relationship between reference pixels and coded pixels. This figure differs from FIG. 7 in the position of the coding block. First, the coded pixel values at the positions of the coded blocks c and d are input to PEs 6, 7, 32, and 33 in FIG. 9, and at the same time, the reference pixel values are 1 to 25, 1 'to 25',
The data is read out in the order of 1 ″ to 25 ″, 1 ′ ″ to 25 ′ ″. Then, by inputting the reference pixel values for 10 columns shown in the reference pixel readout range in FIG. 11, the horizontal direction of the coding block c is 0 to +7, the vertical direction is -4 to +3, and the horizontal direction of the coding block d is -8 to A reference pixel value corresponding to a prediction block candidate in the range of −1, −4 to +3 in the vertical direction is input. Also in this case, since the error calculation is performed on the coded pixel values subjected to the sub-sampling, the reference pixel readout range is a range slightly smaller than the search range.

FIG. 12 shows the relationship between the reading of the reference pixel and the coding block. First, at the same time as the coded pixel values of the coded blocks 0 and 2 are input to the PE, the reference pixel values of r0 to r108 are input in the order shown in FIG. 11 (in FIG. 12, the order is r0, r22, r44,...). Equivalent) AE is required. Next, at the same time as the coded pixel values of the coded blocks 1 and 3 are input to the PE, the reference pixel values of r44 to r152 whose base points are shifted to the left by four columns from r0 are r44, r66, and r8.
Are input in the order of 8,... And AE is obtained. Next, at the same time as the coded pixel values of the coded blocks 2 and 4 are input to the PE, r88 to r1 with the base point shifted four columns to the left from r44.
96 are input in the order of r88, r110, r132,..., And AE is obtained.

As a result, the first reference pixel value input: horizontal direction 0 to +7, vertical direction -4 to +3 of coding block 0 horizontal direction -8 to -1 and vertical direction -4 to +3 of coding block 2 Second reference pixel value input: horizontal direction 0 to +7, vertical direction -4 to +3 of encoding block 1 horizontal direction -8 to -1, vertical direction -4 to +3 of encoding block 3 Third reference pixel value Input: corresponding to a prediction block candidate in the motion vector search range of the coding block 2 in the horizontal direction 0 to +7, the vertical direction -4 to +3, and the coding block 4 in the horizontal direction -8 to -1 and the vertical direction -4 to +3. A reference pixel is input. Regarding the encoding block 2, the first reference pixel value input is -8 to -1 in the horizontal direction, -4 to +3 in the vertical direction. The third reference pixel value input is 2 in the horizontal direction 0 to +7 and the vertical direction is -4 to +3. The AE with the prediction block candidates in the entire search range is calculated by inputting the reference pixel value twice.

In the time chart of FIG. 10, first, the coded pixel values of the coded blocks 0 and 2 are input, and the coded pixel values of the coded block 0 are stored in the coding registers in the PEs 6 and 7. The encoded pixel value of block 2 is PE3
[T = 0 to 0] stored in the encoding register in
7]. The input of the reference pixel value is started from [T = 2] in parallel with the input of the encoded pixel value. In [T = 2 to 6], reference pixel values r0, r22, r44, r6 of the first row (5 pixels)
6, r88 is input.

The output of PE6 is d0 = | t0-r0 | + | t8-r22 | [T = 4] d22 = | t0-r22 | + | t8-r44 | [T = 5] d44 = | t0-r44 | [T = 6] d66 = | t0-r66 | + | t8-r88 | [T = 7], and the output of PE32 is g0 = | t32-r0 | + | t40-r22 | [T = 4] g22 = | t32−r22 | + | t40−r44 | [T = 5] g44 = | t32−r44 | + | t40−r66 | [T = 6] g66 = | t32−r66 | + | t40− r88 | [T = 7].

Further, at time [T = 7 to 11], the reference pixel values r2, r24, r46, r68, and r90 in the third row are input, and the PE 7 calculates the absolute difference between the reference pixel value and the coded pixel value. Is performed, the sum with the output of the preceding stage (PE6) delayed by the clock by the data delay unit 42 is obtained. Therefore, the output of PE7 is e0 = d0 + | t2-r2 | + | t10-r24 | [T = 9] e22 = d22 + | t2-r24 | + | t10-r46 | [T = 10] e44 = d44 + | t2 -R46 | + | t10-r68 | [T = 11] e66 = d66 + | t2-r68 | + | t10-r90 | [T = 12]

In the PE 33, the absolute value of the difference between the reference pixel value and the coded pixel value is calculated, and at the same time, the data delay unit 43
And the sum with the output of the preceding stage (PE32) delayed by 5 clocks is obtained. Therefore, the output of PE33 is h0 = g0 + | t34-r2 | + | t42-r24 | [T = 9] h22 = g22 + | t34-r24 | + | t42-r46 | [T = 10] h44 = g44 + | t34 −r46 | + | t42−r68 | [T = 11] h66 = g66 + | t34−r68 | + | t42−r90 | [T = 12]

E0, e22, e44 and e66 indicate that the motion vector of the coded block 0 is (0,-
4), AE with prediction block candidates (2, -4), (4, -4), (6, -4). h0, h22, h4
4 and h66 indicate that the motion vector is (-8, -4), (-6, -4), (-
A with the predicted block candidates of (4, -4), (-2, -4)
E. In this way, the result of PE6 is further
And the result of PE32 is further cumulatively added by PE33. PE7 outputs AE of coding block 0 and the prediction block candidate, and PE33 outputs AE of coding block 2 and the prediction block candidate. Is output.

As the reference pixels, 100 pixels for the first 10 columns are input during [T = 2 to 101], and then [T = 10
2-201], 100 pixels for the next 10 columns are input,
Thereafter, this operation is repeated. The encoded pixel is [T = 100
To 107], the coded pixels of the coded blocks 1 and 3 are input, and thereafter, the input is repeated while shifting the coded blocks every 100 clocks.

As described above, two sets of a plurality of arithmetic units connected in series via a data delay unit are provided, and the representative pixels of every other coded block are input from the coding memory to the arithmetic units. The operation unit performs the error calculation of every other encoding block in parallel, so that the motion vector detection enables a wider range of motion vector search with the same circuit scale as in the second embodiment. The device can be realized. That is, with one reference pixel input, of the other coding blocks, the left coding block performs an error calculation with the right prediction block candidate group within the search range, and the right coding block searches the right coding block. A reference pixel is input from the reference memory so as to perform an error operation with respect to the left prediction block candidate group in the range. Then, an error calculation with respect to the prediction block candidates in the entire search range is performed by two reference pixel inputs. In this way, when the circuit scale is almost the same, the search range of the motion vector can be doubled only by increasing the readout amount of the reference pixel by about 1.7 times, and the operating frequency is further increased when searching a wide range. Power consumption can be reduced. Also, comparing this embodiment with the first embodiment, the search range is twice as large and the circuit size is double in this embodiment, but the readout amount of the reference pixels is the same, There is an advantage that the reference pixel read amount per the same search range is halved.

<Fourth Embodiment> The fourth embodiment is a case where the search range is changed in the first to third embodiments. The search range of the motion vector depends on the read range of the reference pixel. For example, in the case of the first embodiment, the readout range of the reference pixels is 10 pixels in the horizontal direction and 10 pixels in the vertical direction as shown in FIG. 4, but by changing this range, the search range of the motion vector also changes. . As an example, consider a case in the first embodiment in which the search range of the motion vector is increased by two pixels in both the horizontal and vertical directions, and expanded to -5 to +4 in the horizontal direction and to -5 to +4 in the vertical direction. In this case, the readout range of the reference pixel is also horizontal,
This can be realized by increasing the number of pixels by 2 in both the vertical and 12 pixels in the horizontal direction and 12 pixels in the vertical direction.

In the first embodiment shown in FIG. 1, the delay amount of the data delay unit 8 is 5 clocks, which is 5 pixels in the horizontal direction every other pixel in the reading order of the reference pixels shown in FIG. It corresponds to reading one by one. Therefore, when the reference pixel readout range in the horizontal direction is 12 pixels, six pixels are read out every other pixel in the horizontal direction, and the delay amount of the data delay unit may be set to six clocks. Also in the second and third embodiments, the search range of the motion vector can be changed by the same change. In addition, when the readout amount of the reference pixel in the vertical direction increases, more clock cycles are required for reading, but the circuit configuration does not need to be changed. As described above, in the present embodiment, it is possible to provide a modification in which the search range of the motion vector is easily changed only by changing the delay amount of the data delay unit and changing the read operation of the memory controller.

<Fifth Embodiment> FIG. 13 is a block diagram showing a fifth embodiment of the motion vector detecting device according to the present invention. This is an application example of the second embodiment shown in FIG. If a larger coding block is targeted in the second embodiment shown in FIG. 5, a large number of arithmetic units are connected to the reference registers 4 and 5, which may increase the load. The embodiment of FIG. 13 is characterized in that two sets of reference registers are provided, the number of arithmetic units connected to one reference register is reduced to half, and the load is reduced.

The motion vector detecting device of FIG. 13 is different from the motion vector detecting device of the second embodiment shown in FIG.
3 and the data delay unit 35 are connected to the reference registers 52 and 53, and the control of the memory controller 51 is different, but the other operations are the same.

FIG. 14 is a time chart showing the operation of the fifth embodiment. FIG. 14 shows the operation when the motion vector search range is -4 to +3 in the vertical direction and -4 to +3 in the horizontal direction. In this embodiment, since the outputs of the reference registers 52 and 53 that supply the reference pixel values to the PEs 32 and 33 are delayed by two clocks from the output timings of the reference registers 4 and 5, the operation timings of the PEs 32 and 33 are also PE6 and PE6.
7, the operation is the same as that of the second embodiment shown in FIG. The timing chart is also P from the time chart of the second embodiment shown in FIG.
Only the operation of E32 and E33 is delayed by two clocks, and the other operations are the same. FIG. 13 shows the second embodiment shown in FIG.
This is an example in which the embodiment is modified, but the third embodiment shown in FIG.
A similar modification can be applied to the embodiment.

<Sixth Embodiment> FIG. 15 is a block diagram showing a sixth embodiment of the present invention. The second shown in FIG.
Although this embodiment and the present embodiment have equivalent functions,
In the second embodiment, four PEs are provided. In the present embodiment, two sets of reference registers are provided, and two sets of encoding registers are further provided in the PE. One of the register outputs is selected. This is characterized in that the number of PEs is two.

The motion vector detecting device shown in FIG. 15 comprises two sets of reference registers 4, 5 and 62, 6 connected in series via an encoding memory 1, a reference memory 2, and a data delay 64.
It is composed of selectors 65 and 66 for selecting one output from three or two sets of reference registers, and PEs 67 and 68 connected in series via a data delay unit 69.

FIG. 16 shows the configuration of the PEs 67 and 68 of the present embodiment. As described above, the PE of FIG. 16 includes two sets of encoding registers (21, 22 and 71, 72), and selects one of the outputs.

The operation of the present embodiment will be described with reference to the time chart of FIG. FIG. 17 shows the operation when the search range of the motion vector is -4 to +3 in the vertical direction and -4 to +3 in the horizontal direction, and the symbol of the pixel value corresponds to FIG.
Reading of the encoded pixel value is the same as in the second embodiment,
At the same time when the reading of the reference pixel values for the six columns is completed, the reading of the next encoded block is started. PE67, 68
Has encoding registers for 4 pixels each, and a total of 8
A pixel, that is, an encoded pixel value for two encoded blocks is held.

FIG. 18 shows the reading order of the reference pixel values in the present embodiment. In the second embodiment, the reference pixel value is read in the horizontal direction as shown in FIG. 7, but in the present embodiment, the reference pixel value is read in the vertical direction. In FIG. 18, PE67,
Reference numeral 68 denotes a coded pixel of the coded blocks a and b. Reference pixel values are read out in the order of 1 to 15 in numerical order, and then the base point is set to 1 ', and 1' to 15 'are read out. , 1 ″ ″ and 60 pixels in six columns from 1 ″ to 15 ″ ″ shown in the reference pixel reading range of FIG.

In the time chart of FIG. 17, first, the pixel values of the coding blocks 0 and 1 are read from the coding memory 1 and input to the PEs 67 and 68 [time T = 0 to 0].
7]. Then, the pixel values of the coding block 0 are stored in the coding registers 21 and 22 in the PE shown in FIG.
The encoding registers 71 and 72 store pixel values of the encoding block 1. The reference pixels are input every six columns according to the pattern of FIG. First, r0, r2, r in the first column
4, r6, and r8 are input [T = 0 to 4] and sequentially stored in the reference registers 5 and 4. The signals r0 to r8 are also stored in the reference registers 62 and 63 after two clock delays in the data delay unit 64 in FIG. 15 [T = 4 to 8]. Next, after three clocks of dummy data, r22, r24,
r26, r28, and r30 are input to the reference registers 5 and 4 [T = 8 to 12]. The selectors 65 and 66 in FIG. 15 operate the reference registers 4 and 5 every four clocks from time [T = 2].
And the output data selection of the reference registers 62 and 63 are switched. The selectors 73 and 7 in the PE
4 also selects the output data of the encoding registers 21 and 22 and the encoding registers 71 and 7 every four clocks from the time [T = 2].
The output data selection of No. 2 is switched.

That is, during the period [T = 2 to 5], the outputs of the reference registers 4 and 5 and t0 and t2 held in the encoding registers 21 and 22 are selected, and the operation result of the PE 67 is d0 = | T0-r0 | + | t2-r2 | [T = 2] d2 = | t0-r2 | + | t2-r4 | [T = 3] d4 = | t0-r4 | + | t2-r6 | [T = 4] d6 = | t0−r6 | + | t2−r8 | [T = 5] During the period of [T = 6 to 9], the reference registers 62 and 6
3 and t1 held in the encoding registers 71 and 72
6, t18 are selected, and the calculation result in PE67 is g0 = | t16-r0 | + | t18-r2 | [T = 6] g2 = | t16-r2 | + | t18-r4 | [T = 7] g4 = | t16−r4 | + | t18−r6 | [T = 8] g6 = | t16−r6 | + | t18−r8 | [T = 9]

Similarly, in the PE 68, the encoding register 21,
T8 and t10 stored in the register 22 and the encoding register 7
T24 and t26 stored in the reference registers 1 and 72 are switched and output.
The preceding stage (PE 67) performs the absolute difference calculation with respect to the output of 63 and delays the data delay 69 by 8 clocks.
E0 = d0 + | t8-r22 | + | t10-r24 | [T = 10] e2 = d2 + | t8-r24 | + | t10-r26 | [T = 11] e4 = d4 + | t8 -R26 | + | t10-r28 | [T = 12] e6 = d6 + | t8 -r28 | + | t10-r30 | [T = 13] h0 = g0 + | t24-r22 | + | t26-r24 | [T = 14] h2 = g2 + | t24-r24 | + | t26-r46 | [T = 15] h4 = g4 + | t24-r26 | + | t26-r28 | [T = 16] h6 = g6 + | t24-r28 | + | t26−r30 | [T = 17] is output.

As a result, e0 is the AE of the motion vector of the coded block 0 with the prediction block candidate of (0, -4), e2 is (0, -2), e4 is (0, 0), and e6 is AE with the prediction block candidate of (0, +2). H0 indicates that the motion vector of the encoded block 1 is (−4,
-4) is the AE with the prediction block candidate, and h2 is (−)
4, -2), h6 is (-4,0), h8 is (-4, +
The AE with the prediction block candidate of 2) is obtained.

In this way, the input of the reference pixel value of five pixels and the input of dummy data of three clocks are repeated, and the time T0
To r64 shown in FIG.
The input of the reference pixel values of the six columns is ended. In the meantime, the error between the prediction block candidate in the motion vector search range in the vertical direction -4 to +3 and the horizontal direction -4 to -3 in the coding block 0 in the vertical direction -4 to +3 and the horizontal direction 0 to +3 in the coding block 1 Perform the operation. Subsequently, the encoding register 2 of the PEs 67 and 68
The pixel values of the encoding block 2 are input to 1, 2 and [T =
96 to 100] The reference pixel values in six columns r44 to r108 are input, and error calculation is sequentially performed.

By repeating the above operation, the AE with all the prediction block candidates of one encoded block every 96 clocks
Is output. In the second embodiment shown in FIG. 5, 60 clocks are required for processing of one encoded block, so that one operation unit can perform twice as many operations with about 1.5 times as many clocks. That is, by increasing the number of clocks by about 1.5 times, equivalent functions can be realized with half the PEs.

In each of the embodiments described above, the difference absolute value sum is used as the error calculation amount, but another index such as the sum of squares of the difference may be used. At this time, for example, only the difference absolute value calculator of FIGS. 2 and 16 is used as a calculator for calculating the square of the difference, and the other components do not need to be changed. Further, the number of pixels, the sub-sampling pattern, and the motion vector search range of the coding block are not limited to those described in the embodiment, and the present invention is applicable to various cases.

[0085]

According to the present invention, the cumulative addition of the matching operation is performed in an order based on the sub-sampling pattern, so that the number of operation units and the circuit scale of the data delay unit are different from those of the conventional example. It can be significantly reduced in comparison. Also, even if the search area in the vertical direction changes, only the readout amount of the reference pixel changes, and there is no need to change the configuration of the arithmetic unit or the data delay unit. Even if the search area in the horizontal direction changes, only the read order of the reference pixels and the delay amount of the data delay unit are changed, and there is no need to change the configuration of the arithmetic unit. Therefore, the search area can be easily changed.

According to the second and third aspects of the present invention, since the error calculation of two encoded blocks is performed in parallel, the operating frequency can be further reduced.

According to the fourth aspect of the present invention, when the circuit scale is substantially the same as that of the third aspect of the present invention, the search range of the motion vector is increased by more than the readout amount of the reference pixel. The operating frequency can be further reduced when searching a wide range, and power consumption can be reduced.

According to the fifth and sixth aspects of the present invention, the motion vector detection processing of adjacent coded blocks is performed by using one arithmetic unit by time division.
If the clock is increased, the number of operation units can be reduced, and the size of the circuit can be reduced.

According to the present invention, the same effect can be obtained even when the square error is used as the matching operation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a motion vector detection device according to the present invention.

FIG. 2 is a block diagram of an arithmetic unit according to the first embodiment.

FIG. 3 is a timing chart illustrating operations of a reference register and an arithmetic unit according to the first embodiment.

FIG. 4 is a diagram illustrating a reading order of reference images according to the first embodiment.

FIG. 5 is a block diagram showing a second embodiment of the motion vector detecting device according to the present invention.

FIG. 6 is a timing chart illustrating operations of a reference register and an arithmetic unit according to the second embodiment.

FIG. 7 is a diagram illustrating a reading order of reference images according to the second embodiment.

FIG. 8 is a diagram illustrating a relationship between a reading order of reference images and an encoding block that performs an error operation according to the second embodiment.

FIG. 9 is a block diagram showing a third embodiment of the motion vector detection device according to the present invention.

FIG. 10 is a timing chart illustrating operations of a reference register and an arithmetic unit according to the third embodiment.

FIG. 11 is a diagram illustrating a reading order of reference images according to the third embodiment.

FIG. 12 is a diagram illustrating a relationship between a reading order of reference images and an encoding block that performs an error operation according to the third embodiment.

FIG. 13 is a block diagram showing a fifth embodiment of the motion vector detection device according to the present invention.

FIG. 14 is a timing chart illustrating operations of a reference register and an arithmetic unit according to the fifth embodiment.

FIG. 15 is a block diagram showing a motion vector detecting device according to a sixth embodiment of the present invention.

FIG. 16 is a block diagram of an arithmetic unit according to the sixth embodiment.

FIG. 17 is a timing chart illustrating operations of a reference register and an arithmetic unit according to the sixth embodiment.

FIG. 18 is a diagram illustrating a reading order of reference images according to the sixth embodiment.

FIG. 19 is a block diagram showing a conventional motion vector detection device.

FIG. 20 is a block diagram showing an arithmetic unit of a conventional motion vector detection device.

FIG. 21 is an example of a motion vector search range in a conventional example.

FIG. 22 is a diagram illustrating a relationship between an encoded pixel and a reference pixel in a conventional example.

FIG. 23 is a time chart for explaining cumulative addition of error amounts in a conventional example.

FIG. 24 is a time chart for explaining cumulative addition of error amounts in a conventional example.

FIG. 25 is an example of a sub-sampling pattern of a coding block.

FIG. 26 is a block diagram showing a conventional motion vector detection device when an encoded block is sub-sampled.

FIG. 27 is a block diagram illustrating an arithmetic unit of a conventional motion vector detection device when an encoded block is sub-sampled.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Encoding memory 2 Reference memory 3 Memory controller 4, 5 Reference register 6, 7 Operation unit 8 Data delay unit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yoichi Fujiwara F-term (reference) in Sharp Corporation 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka 5C059 KK15 KK19 KK49 LB05 MA27 NN01 NN03 NN28 NN31 TA62 TA63 TB08 TC03 TC12 TD05 TD06 UA34 UA38

Claims (7)

[Claims] 1. A pixel constituting an encoding block,
Using a representative pixel value subsampled in a predetermined pattern, block matching is performed on all prediction block candidates in a search area, and a motion vector detection device that detects a motion vector by finding a prediction block that best matches the encoded block is used. An encoding memory that stores an encoding block, a reference memory that stores a reference image value of a prediction block candidate, a memory controller that controls input / output of the encoding memory and the reference memory, and a reference pixel value of the reference memory. A reference register for storing the data, a plurality of data delay units for delaying data output timing, and a plurality of operation units connected in series via the data delay unit, wherein the memory controller has a sub-sampled code. From the encoding memory to the arithmetic unit. In addition to the scattered output, a reference pixel value of a prediction block candidate corresponding to a representative pixel value of the coding block is read from the reference memory based on the sub-sampling pattern, and all predictions in a search area are stored in the reference register. The reference pixel values of the block candidates are sequentially input, and the arithmetic unit holds the pixel values of the sub-sampled encoded block, and stores the pixel value of the encoded block and the reference register corresponding to the pixel value. A calculation is performed to obtain an error amount between the pixel value and the error value, and the error amount is cumulatively added to an output value of another operation unit. The unit adjusts the output timing so that it is cumulatively added to the error amount of the same prediction block candidate, and outputs the error output from the final stage arithmetic unit. A motion vector detecting device, wherein a motion vector is determined using a predicted block candidate having a minimum value in a quantity as a predicted block. 2. A plurality of sets of the plurality of data delay units and the plurality of arithmetic units, wherein one set of arithmetic units holds a representative pixel value of an already inputted coding block, The set of operation units outputs representative pixel values of a coding block adjacent to the coding block from the coding memory, and both sets of the operation units include a reference pixel of the common prediction block candidate and the representative pixel value. 2. The motion vector detecting device according to claim 1, wherein the calculation is performed by: 3. A memory controller comprising two sets of the plurality of data delay units and the plurality of arithmetic units, wherein the memory controller outputs a representative pixel value of one coding block to the one set of arithmetic units from the coding memory. Then, the other set of operation units outputs representative pixel values of every other coded block from the coded memory for the coded block, and both sets of the operation units generate common prediction block candidates. 2. The motion vector detecting device according to claim 1, wherein an operation is performed on a reference pixel and the representative pixel value. 4. The arithmetic unit includes: M encoding registers for storing encoded pixel values of the number M of pixels on one side of a subsampled encoded block; M number of difference absolute value calculators for calculating a difference absolute value from a corresponding pixel value of the reference register, and an adder for adding an output of a preceding stage arithmetic unit and an output of the M number of difference absolute value calculators The motion vector detecting device according to claim 1, comprising: 5. The arithmetic unit according to claim 5, wherein the number of the reference registers is 2M, and further comprising a selector for selecting and outputting M data from the reference registers, and selecting only valid M register outputs by the selector. 5. The motion vector detecting apparatus according to claim 4, wherein the error calculation in a search range overlapping between the coding blocks is performed by a common operation unit by time division. 6. The arithmetic unit includes: M first encoding registers for storing encoded pixel values of M pixels on one side of a subsampled encoded block; and a code including the encoded pixel values. M second coded registers for storing M coded pixels of a coded block adjacent to a coded block, and M register outputs selected from a total of 2M first and second coded registers And a selector for adding the outputs of the other absolute value arithmetic units and the output of the absolute difference value arithmetic unit. The number of reference registers is 2M. A selector for selecting and outputting M data from the reference register, selecting only valid M register outputs and supplying the selected output to the arithmetic unit; Motion vector detecting apparatus according to claim 1, characterized in that the time division the difference calculated by the common calculation unit. 7. The method according to claim 4, wherein a difference square calculator is used instead of the absolute difference calculator.
The motion vector detecting device according to claim 1.