JP2000022159A - Manufacturing for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device having a semiconductor layer with high field-effect mobility. SOLUTION: In a manufacturing method, a polysilicon film 3 is formed on a transparent insulating substrate 1, and the surface of the polysilicon film 4 is oxidized to form a thick silicon dioxide film 4. After the silicon dioxide film 4 is removed, the uneven surface of the polysilicon film 3 is polished and flattened by a CMP(chemical-mechanical polishing) method, and the surface of the polysilicon film 3 is oxidized again to form a thin silicon dioxide film 4a. After that, the silicon dioxide film 4a is removed. Then, the polysilicon film 3 obtained has a flat face and extremely satisfactory characteristics in crystallinity. As a result, field-effect mobility in a TFT(thin-film transistor) with the polysilicon film 3 as an active layer can be made to improve.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a semiconductor layer.

[0002]

2. Description of the Related Art Conventionally, a liquid crystal display device (LCD: Liquid C)
A crystal display includes a display pixel unit arranged in a matrix and a drive circuit unit for driving the display pixel unit. In general, in the case of a liquid crystal display device, a transistor included in a driver circuit portion requires higher mobility (higher speed) than a transistor included in a display pixel portion.

In recent years, a TFT (Th
The use of a polycrystalline silicon film as an active layer of the "Film Transistor" makes it possible to realize a high mobility to some extent. For this reason, TFTs made of a polycrystalline silicon film have been used not only for the transistors forming the display pixel portion but also for the transistors forming the driving circuit portion. Then, T, which constitutes the display pixel portion,
By using a polycrystalline silicon film as an active layer between an FT and a TFT constituting a drive circuit portion, a so-called drive circuit integrated LCD in which a display pixel portion and a drive circuit portion are formed on the same substrate has been developed. I have.

[0004] In an LCD including a TFT using such a polycrystalline silicon film as an active layer, a TFT constituting a drive circuit section is formed with the increase in definition and density of the LCD pixel.
There is a demand for an even faster FT. For this reason, research and development for improving the mobility of the active layer of a TFT made of a polycrystalline silicon film have been conventionally performed.

For example, silane (SiH) is used as a material gas for forming a silicon layer which will later become a polycrystalline silicon film.
₄ ) There are various methods such as changing the gas to disilane (Si ₂ H ₆ ) gas to increase the crystal grain size of the polycrystalline silicon film after the solid phase growth, thereby increasing the speed. Proposed.

[0006]

However, it has been difficult to obtain an active layer of a TFT having a sufficiently high mobility even by the above-mentioned proposed technology. Therefore, when such a TFT is used for an LCD, it is particularly difficult to obtain a higher-speed drive circuit, and as a result,
There is a problem that it is difficult to improve the display characteristics of the LCD.

An object of the present invention is to easily manufacture a semiconductor device having a semiconductor layer having high mobility in a method of manufacturing a semiconductor device. Another object of the present invention is to provide a method for manufacturing a semiconductor device, which reduces crystal defects in a semiconductor layer and reduces irregularities on the surface of the semiconductor layer.

[0008]

According to one aspect of the present invention, a method of manufacturing a semiconductor device includes a step of forming a semiconductor layer on a substrate and a step of forming an oxide film by oxidizing a surface of the semiconductor layer. Removing the oxide film, planarizing the surface of the semiconductor layer, oxidizing the planarized surface of the semiconductor layer to form an oxide film, and removing the oxide film. Exposing the surface of the semiconductor layer.

As described above, if an oxide film is formed by oxidizing the surface of the semiconductor layer and then the oxide film is removed, the crystallinity of the semiconductor layer can be further improved.
The thicker the oxide film, the higher the effect of improving the crystallinity of the semiconductor layer, but on the other hand, the greater the degree of unevenness on the surface of the semiconductor layer. In this invention, after removing the oxide film, the unevenness on the surface of the semiconductor layer is flattened.

In the present invention, since the oxide film is formed again on the surface of the semiconductor layer after the planarization, the damaged layer formed on the surface of the semiconductor layer by the planarization also becomes a part of the oxide film. In this case, the oxide film after the planarization is desirably formed thinner than the oxide film before the planarization so as not to increase the degree of unevenness on the surface of the semiconductor layer again. As described above, in the manufacturing method according to one aspect of the present invention, it is possible to reduce crystal defects in the semiconductor layer and to reduce unevenness on the surface of the semiconductor layer, thereby reducing the field-effect mobility of the semiconductor layer. Can be improved, and as a result, the drain current of the semiconductor layer can be increased. When such a semiconductor layer is used in a liquid crystal display device, high-speed driving of a driving circuit portion can be performed, and high definition and high density of a pixel portion can be realized.

In the method for manufacturing a semiconductor device according to the above aspect, the semiconductor layer is preferably a polycrystalline semiconductor layer formed by polycrystallizing an amorphous semiconductor layer. Further, the semiconductor layer may include a silicon layer. Preferably, the semiconductor layer comprises the active layer of a thin film transistor.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same reference numerals are used for the same components. (First Embodiment) A manufacturing process of a semiconductor device (TFT) according to a first embodiment of the present invention will be described with reference to FIGS.

Step 1a (see FIG. 1A): LPCV is placed on a transparent insulating substrate 1 made of glass or quartz glass.
An amorphous silicon film (amorphous semiconductor film) 2 is formed using Si ₂ H ₆ (disilane gas) as a source gas using a D (Low Pressure Chemical Vapor Deposition) method. The amorphous silicon film 2 has a temperature of about 450 ° C.
It is formed to have a thickness of about nm.

Step 1b (see FIG. 1B): Annealing is performed at a temperature of about 600 ° C. for about 20 hours using solid phase growth (SPC). As a result, the amorphous silicon film 2 is polycrystallized and reformed into a polycrystalline silicon film 3. At this time, the thickness of the polycrystalline silicon film 3 is reduced to about 1000 nm. Step 1c (see FIG. 1C): The surface of the polycrystalline silicon film 3 is oxidized by performing dry oxidation in an oxygen atmosphere at about 1050 ° C. for about 30 minutes. Thus, a silicon dioxide (SiO ₂ ) film 4 having a thickness of about 60 nm is formed on the surface of the polycrystalline silicon film 3.

Step 1d (see FIG. 1D): The silicon dioxide film 4 is removed by wet etching using a hydrofluoric acid-based etchant to expose the surface of the polycrystalline silicon film 3. After the surface of the polycrystalline silicon film 3 is oxidized to form the silicon dioxide film 4 and then the silicon dioxide film 4 is removed, the crystallinity of the polycrystalline silicon film 3 can be improved.

Step 1e (see FIG. 1 (e)): FIG.
Dry oxidation time and polycrystalline silicon film 3 in step 1c
6 is a graph showing the state of irregularities on the surface of FIG. As described above, as the dry oxidation time is lengthened and the thickness of the silicon dioxide film 4 is increased, the unevenness of the surface of the polycrystalline silicon film 3 becomes larger. FIG. 11 shows an uneven state of the surface of the polycrystalline silicon film 3 and a TF using the polycrystalline silicon film 3 as an active layer.
6 is a graph showing the relationship between T and the breakdown voltage. As described above, the larger the unevenness of the surface of the polycrystalline silicon film 3 becomes, the more the TFT becomes.
, The breakdown voltage characteristic is degraded.

Therefore, in this step 1e, a chemical mechanical polishing method (hereinafter referred to as C
The surface of the polycrystalline silicon film 3 is polished by 9 nm using an MP method. Thereby, the irregularities of the polycrystalline silicon film 3 are flattened. As described above, in step 1c, the thicker the silicon dioxide film 4 is formed,
Although the crystallinity of the polycrystalline silicon film 3 can be further improved, on the other hand, the irregularities on the surface of the polycrystalline silicon film 4 are inevitably increased, and this polycrystalline silicon film 3 is used as, for example, an active layer of a transistor. When used, there is a concern that transistor characteristics may be degraded. The polishing operation in the step 1e is extremely effective in that this point can be solved.

However, after the CMP, a thin damage layer 3a may be formed on the surface of the polycrystalline silicon film 4 due to stress caused by application of mechanical pressure.
Note that the CMP method is a method of processing by adding a chemical action to mechanical polishing, and is performed while flowing an abrasive mainly composed of colloidal silica or the like. Step 1f (see FIG. 1 (f)): By performing dry oxidation for about 3 minutes in an oxygen atmosphere at about 1050 ° C.,
The surface of the polycrystalline silicon film 3 including the damaged layer 3a is oxidized again. Thereby, silicon dioxide (SiO ₂ ) having a thickness of about 5 nm is formed on the surface of the polycrystalline silicon film 3.
The film 4a is formed.

Step 1g (see FIG. 1G): The silicon dioxide film 4a is removed by wet etching using a hydrofluoric acid-based etchant to expose the surface of the polycrystalline silicon film 3. As described above, in the present embodiment, in the step 1c, the silicon dioxide film 4 is formed as thick as possible without considering the irregularities formed on the surface of the polycrystalline silicon layer 3, so that the crystal of the polycrystalline silicon film 3 is formed. Process 1
In (e), after flattening the irregularities on the surface of the polycrystalline silicon film 3, in step 1f, an oxide film enough to remove a damaged layer on the surface of the polycrystalline silicon film 3 is formed. The polycrystalline silicon film 3 obtained in the step 1g has a flat surface and extremely excellent crystallinity.

As a result, such a polycrystalline silicon film 3
The field-effect mobility of a TFT using as an active layer can be improved. FIG. 12 is a graph showing the relationship between the dry oxidation time in step 1c and the field-effect mobility of an n-channel TFT using the polycrystalline silicon film 3 obtained in step 1g as an active layer. As in the present embodiment, a very high electric field effect of 190 cm ² / Vs is obtained by performing dry oxidation for 30 minutes to form a silicon dioxide film 4 having a large thickness and then performing a series of processes up to the step 1g. Mobility can be obtained.

Hereinafter, an example in which the polycrystalline silicon film 3 is used as an active layer of a TFT will be described. Step 2 (see FIG. 2): The surface of the polycrystalline silicon film 3 is irradiated with a KrF excimer laser beam having a wavelength of λ = 248 nm to perform laser annealing. Laser irradiation conditions at this time are as follows: substrate temperature is from room temperature to 600 ° C., irradiation energy density is 1;
^{00mJ / cm 2 ~500mJ / cm 2} , the scanning speed is 1m
m / sec to 10 mm / sec.

Note that the scanning speed is actually 1
Scanning is possible at a speed in the range of μm / sec to 100 mm / sec. The laser beam has a wavelength λ = 30.
8nm XeCl excimer laser or wavelength λ = 193nm
ArF excimer laser may be used. Step 2 may be omitted as appropriate.

Step 3 (see FIG. 3): The polycrystalline silicon film 3 irradiated with the laser is etched and patterned. Step 4 (see FIG. 4): A gate insulating film 6 is formed on the patterned polycrystalline silicon film 3 by using the LPCVD method.
An HTO film (High Temparature Oxide: silicon oxide film) is formed. Thereafter, heat treatment is performed.

This heat treatment is performed for about 2 hours at a temperature of about 1050 ° C. in an N ₂ atmosphere by inserting the transparent insulating substrate 1 into an electric furnace. This heat treatment is performed by RTA (Ra
Rapid heat treatment by the pidThermal Annealing method may be used. Conditions of the heat treatment at this time, the heat source is Xe arc lamp, about 1100 ° C. or less temperature of about 900 ° C. or higher (preferably about 950 ° C. or higher to about 1100 ° C. or less), in an N ₂ atmosphere, the 1 to 10 seconds Time. The heating by the RTA method uses a high temperature, but can be completed in a very short time. Therefore, the transparent insulating substrate 1 is deformed while the defects in the crystal of the polycrystalline silicon film 3 are reduced by the high temperature heat treatment. Inconvenience can be prevented.

Step 5 (see FIG. 5): A polycrystalline silicon film 7 doped with phosphorus is formed on the gate insulating film 6 by using the LPCVD method. Step 6 (see FIG. 6): Photolithography technology and RIE
The polycrystalline silicon film 7 and the gate insulating film 6 thereunder are patterned by using a dry etching technique by a method. Thus, a patterned gate electrode 8 and gate insulating film 6 are obtained in a region located on polycrystalline silicon film 3.

Step 7 (see FIG. 7): Polycrystalline silicon film 3
Is implanted into the exposed upper surface and the upper surface of the gate electrode 8. Further, the implanted impurities are activated by performing a heat treatment. As the impurity at this time, arsenic (As) or phosphorus (P) is used in the case of n-type, and the implantation conditions in this case are about 80 keV and about 3 × 10 ¹³ / cm ² . When implanting a p-type impurity, boron (B) is used. In this case, the implantation conditions are about 30 keV and about 1.5.
× 10 ¹³ / cm ² . By the impurity implantation and the heat treatment as described above, the low concentration impurity regions 10 and 11 are formed.
To form

Step 8 (see FIG. 8): An insulating film (not shown) is formed on the transparent insulating substrate 1 by APCVD (normal pressure CVD) so as to cover the polycrystalline silicon film (active layer) 3 and the gate electrode 8. ) Is deposited, this insulating film is etched using anisotropic overall etch-back. This allows
On the side surfaces of the gate electrode 8 and the gate insulating film 6, a sidewall 12 made of an insulating film is formed.

Step 9 (see FIG. 9): sidewall 12
By implanting impurities into polycrystalline silicon film 3 by using as masks, high-concentration impurity regions 14 and 15 are formed in a self-aligned manner. The impurities to be implanted at this time are:
In the case of n-type, phosphorus (P) ions are used, and the implantation conditions are as follows.
It is about 80 keV and about 3 × 10 ¹⁵ / cm ² . further,
In this state, impurities are activated by performing a heat treatment using an electric furnace. The heat treatment condition in this case is about 8
At 50 ° C. for about 30 minutes, the N ₂ gas flow rate is about 5 l / min.

The heat treatment may be a rapid heat treatment by the RTA method. The heat treatment conditions at this time are as follows: a heat source is a Xe arc lamp;
C. or less, the atmosphere is N ₂ , and the time is 1 second or more and 3 seconds or less. Heating by the RTA method uses a high temperature but can be completed in a very short time. Therefore, while reducing defects in the crystal of the polycrystalline silicon film 3 by high-temperature heat treatment,
The deformation of the transparent insulating substrate 1 can be effectively prevented. In this manner, the low-concentration impurity regions 10 and 11 and the high-concentration impurity regions 14 and 15
Source / drain regions having a DD (Lightly Doped Drain) structure are formed.

Through the above steps, a TFT using the polycrystalline silicon film as an active layer is formed. Next, FIG.
The manufacturing process of a liquid crystal display (LCD) incorporating a TFT formed by using the manufacturing process of the first embodiment will be described with reference to FIG. First, after the TFT according to the first embodiment shown in FIG. 9 is formed, as shown in FIG. 13, an ITO (Indium Tin Oxide) is formed on the pixel region of the transparent insulating substrate 1 by using a sputtering method. The storage electrode 17 which forms the storage capacitor made of is formed. This storage electrode 1
7 may be formed at the time of forming the phosphorus-doped polycrystalline silicon film 3 to be the active layer of the TFT.

Next, an interlayer insulating film 33 is formed on the entire surface of the device. As a material of the interlayer insulating film 33, a silicon oxide film, a silicate glass, a silicon nitride film, or the like is used. These films are formed by CVD or P
The CVD method is used. Thereafter, a contact hole 19 reaching the high concentration impurity regions 14 and 15 is formed in the interlayer insulating film 33. Then, after forming an AlSi film (not shown) which fills the contact hole 19 and extends along the upper surface of the interlayer insulating film 33, the AlSi film is patterned. Thus, source / drain electrodes 18 are formed.

After the interlayer insulating film 16 is formed so as to cover the interlayer insulating film 33 and the source / drain electrodes 18, a contact hole is formed in a region of the interlayer insulating film 16 located on one of the source / drain electrodes 18. Form.
The contact hole is buried and an interlayer insulating film 1 is formed.
After forming an ITO film (not shown) extending along the upper surface of 6, the display electrode 20 is formed by patterning the ITO film. Display electrode 20 and interlayer insulating film 1
An alignment film 29 is formed on 6. Thereby, the substrate on the TFT side is completed.

Next, a transparent insulating substrate 1 on which a TFT made of polycrystalline silicon is formed, and a common electrode 21
And the transparent insulating substrate 22 on which the alignment film 29 is formed is opposed to each other. In this state, liquid crystal is sealed between the transparent insulating substrate 1 and the transparent insulating substrate 22 to form a liquid crystal layer 23. Thereby, the pixel portion of the LCD is completed. Thus, the LCD using the TFT according to the first embodiment is
Is formed.

FIG. 14 shows a liquid crystal display panel in which a display pixel portion and a peripheral drive circuit portion are formed on the same substrate.
Referring to FIG. 14, in this liquid crystal display panel, a peripheral drive circuit unit (gate driver 25 and drain driver 2)
The active layer of 6) and the active layer of the display pixel portion are constituted by the polycrystalline silicon film 3 formed by the process of the present embodiment. In the display pixel section, a plurality of display electrodes 20 are arranged in a matrix.

The signal lines 4 are provided between the display electrodes 20.
Connected by 0. Also, the gate driver 25
And the signal wiring 40 also for the drain driver 26, respectively.
Is connected. FIG. 15 is a block diagram of an active matrix type LCD to which the TFT according to the first embodiment is applied.

Referring to FIG. 15, the pixel section 24 includes scanning lines (gate lines) G1... Gn, Gn + 1... Gm and data lines (drain lines) D1.
m are arranged. Each gate line and each drain line are orthogonal to each other, and the pixel portion 24
Is provided. Each gate line is connected to a gate driver 25, and a gate signal (scan signal) is applied.

Each drain wiring is connected to a drain driver (data driver) 26 to which a data signal (video signal) is applied. The gate driver 25 and the drain driver 26 constitute a peripheral drive circuit section 28. An LCD in which at least one of the gate driver 25 and the drain driver 26 is formed on the same substrate as the pixel portion 24 is generally called a driver-integrated (driver built-in) LCD. The gate driver 2
5 may be provided on both sides of the pixel unit 24, and the drain driver 26 may be provided on both sides of the pixel unit 24.

In the LCD shown in FIG. 15, not only the pixel driving elements of the pixel section 24 but also the switching elements of the peripheral driving circuit section 28 are provided with the TFT made of the polycrystalline silicon film according to the first embodiment. Is used. In this case, at the time of manufacturing, the TFT used for the pixel portion 24 and the peripheral drive circuit portion 2
The TFT used for 8 is formed in parallel on the same substrate.
It should be noted that the TFT including the polycrystalline silicon film of the peripheral drive circuit section 28 employs a normal single drain structure instead of an LDD structure. In this case, an LDD structure may be used.

If the TFT made of the polycrystalline silicon film of the peripheral drive circuit section 28 is formed in a CMOS structure,
The formation area of the FT can be reduced. As a result, the formation region of the gate driver 25 and the drain driver 26 can be reduced, and high integration can be achieved. FIG. 16 shows an equivalent circuit of a pixel portion provided in a portion orthogonal to the gate line Gn and the drain line Dn. Referring to FIG. 16, the pixel section 24 includes a TFT as a pixel driving element, a liquid crystal cell LC, and an auxiliary capacitance Cs. The gate of the TFT is connected to the gate wiring Gn, and the drain of the TFT is connected to the drain wiring Dn. A display electrode (pixel electrode) 20 of the liquid crystal cell LC and an auxiliary capacitance electrode (storage electrode or load capacitance electrode) 17 are connected to the source of the TFT.

The liquid crystal cell LC and the storage capacitor Cs constitute a signal storage element. A voltage Vco is applied to a common electrode (an electrode opposite to the display electrode 20) 21 of the liquid crystal cell LC.
m is applied. On the other hand, in the storage capacitor Cs, the TFT
Electrode (opposite electrode) 5 opposite to the side connected to the source
A constant voltage VR is applied to 0. The common electrode 21 of the liquid crystal cell LC is an electrode common to all the pixel units 24. An electrostatic capacitance is formed between the display electrode 20 and the common electrode 21 of the liquid crystal cell LC. Note that in the auxiliary capacitance Cs, the counter electrode 50 may be connected to the adjacent gate line Gn + 1 in some cases.

The operation is as follows. In the pixel section 24 configured as described above, the gate line Gn is set to a positive voltage and the TF
When a static voltage is applied to the gate of T, the TFT is turned on. In this state, a charge corresponding to the data signal applied to the drain wiring Dn is charged in the capacitance of the liquid crystal cell LC and the auxiliary capacitance Cs. On the other hand, the gate wiring Gn
When a negative voltage is applied to the TFT gate by setting
The TFT is turned off.

In this state, the voltage applied to the drain wiring Dn is held by the capacitance of the liquid crystal cell LC and the auxiliary capacitance Cs. In this manner, by supplying a data signal to be written to the pixel portion 24 to the drain wiring and controlling the voltage of the gate wiring, the pixel portion 24 can hold an arbitrary data signal. The transmittance of the liquid crystal cell LC changes in accordance with the data signal held by the pixel unit 24, and an image is displayed.

(Second Embodiment) A manufacturing process according to a second embodiment will be described below with reference to FIGS. The manufacturing process according to the second embodiment includes:
10 shows a case where an offset structure is formed in a TFT formed by using the manufacturing method according to the first embodiment shown in FIGS. In the case where the offset structure is formed as described above, the step 7 according to the first embodiment shown in FIG.
, The impurity is implanted after the sidewall 12 is formed as shown in FIG. Thus, low concentration impurity regions 10 and 11 are formed. Then, after a resist film 30 is formed so as to cover the sidewalls 12 and the gate electrode 8, impurities are implanted by using the resist film 30 as a mask,
The high concentration impurity regions 14 and 15 are formed. By performing such a process, an offset structure can be easily formed in the TFT having excellent characteristics described in the first embodiment.

(Third Embodiment) In the first and second embodiments, the manufacturing process of the top gate type TFT in which the gate electrode 8 is located on the polycrystalline silicon film 3 has been described. In the embodiment, a bottom-gate type TFT in which a gate electrode is located under a polycrystalline silicon film
Will be described.

Step (1) (see FIG. 19): A gate electrode 8 is formed on the transparent insulating substrate 1, and an interlayer insulating film 6 is formed so as to cover the gate electrode 8. The gate electrode 8 is desirably formed using a high melting point metal material such as Ta so as to withstand high-temperature processing to be performed later. Next, a polycrystalline silicon film 3 is formed on the interlayer insulating film 6 by a method similar to the process shown in FIG. 1 (steps 1a to 1g in the first embodiment). This polycrystalline silicon film 3 becomes an active layer of the TFT.

Step (2) (see FIG. 20): KrF of wavelength λ = 248 nm is formed on the surface of the polycrystalline silicon film (active layer) 3.
Laser annealing is performed by irradiating an excimer laser beam. Irradiation conditions and the like at this time are performed under the same conditions as in step 2 of the first embodiment shown in FIG. Also,
As in the first embodiment, various high energy beams other than the KrF excimer laser beam can be used.

This step (2) may be omitted as appropriate. Step (3) (see FIG. 21): Rapid heat treatment is performed by the RTA method. The conditions of the heat treatment at this time are a heat source of Xe arc lamp, a temperature of about 900 ° C. to about 1100 ° C., an atmosphere of N ₂ , and a time of 1 second to 10 seconds. Since the heating by the RTA method is at a high temperature but is completed in an extremely short time, it is possible to prevent inconvenience such as deformation of the transparent insulating substrate 1 while reducing defects in the crystal of the polycrystalline silicon film 3 by the high-temperature heat treatment. can do.

Step (4) (see FIG. 22): Patterning is performed using a photolithography technique and a dry etching technique. Step (5) (see FIG. 23): A resist film 32 is formed on a predetermined portion of the polycrystalline silicon film 3. Then, high-concentration impurity regions 14 and 15 are formed by ion-implanting impurities into polycrystalline silicon film 3 using resist film 32 as a mask. Thereafter, the resist 32 is removed.

Step (6) (see FIG. 24): The interlayer insulating film 33 is formed so as to cover the polycrystalline silicon film 3 and the interlayer insulating film 6.
To form Step (7) (see FIG. 25): After forming a contact hole in a region located on the high concentration impurity regions 14 and 15 of the interlayer insulating film 33, the contact hole is buried and extends over the interlayer insulating film 33. Thus, an AlSi film to be the source / drain electrodes 18 is formed.

Step (8) (see FIG. 26): The source / drain electrodes 18 are formed by patterning the AlSi film. In the third embodiment, after the polycrystalline silicon film 3 is irradiated with a laser and then subjected to a heat treatment, a synergistic effect of the improvement of the crystallinity by the laser irradiation and the improvement of the surface roughness by the heat treatment is obtained. be able to. Thereby, the field effect mobility of the formed TFT can be improved, and as a result, the drain current of the TFT can be increased.

Further, in the laser irradiation step shown in FIG. 20, the laser irradiation may be performed while heating the transparent insulating substrate 1. By doing so, the surface roughness of the polycrystalline silicon film 3 can be further reduced, and the field effect mobility (drain current) of the TFT can be further increased. FIG. 27 is a sectional view showing a liquid crystal display device including a TFT formed by the manufacturing process of the third embodiment. Referring to FIG. 27, this liquid crystal display device is different from the liquid crystal display device shown in FIG. 13 only in that the liquid crystal display device shown in FIG. 27 uses a bottom gate type TFT. The structure is the same. By using a TFT having a large field-effect mobility (a large drain current) in a liquid crystal display device, a high-speed operation of a driving circuit portion is enabled, and high definition and high density of a pixel portion are achieved. can do.

Although the amorphous silicon film is used as the amorphous semiconductor film 2 in the first to third embodiments, selenium (Se), germanium (Ge), gallium arsenide (GaAs), or Gallium nitride (GaN)
Alternatively, an amorphous semiconductor film made of such as may be used. In the first to third embodiments, an excimer laser is used as the high energy beam, but a xenon (Xe) arc lamp may be used.

As a method for polycrystallizing the amorphous silicon film 2, the solid-phase growth method is used in the first to third embodiments, but a melting recrystallization method using a laser or the like may be used. . The silicon dioxide film 4 formed on the surface of the polycrystalline silicon film 3 may be formed by a wet oxidation method. Further, as a method for flattening the irregularities on the surface of the polycrystalline silicon film 3, the CMP method is used in the first to third embodiments. After covering the surface with flat,
Dry etching may be performed under conditions having no selectivity for etching the protective film and the polycrystalline silicon film 3 to flatten the unevenness of the surface of the polycrystalline silicon film 3.

[0054]

According to the method of manufacturing a semiconductor device of the present invention, a semiconductor device having a semiconductor layer having high mobility can be easily manufactured. Further, in the method for manufacturing a semiconductor device according to the present invention, it is possible to reduce crystal defects in the semiconductor layer and to reduce irregularities on the surface of the semiconductor layer.

[Brief description of the drawings]

FIG. 1 shows a semiconductor device (T) according to a first embodiment of the present invention.
FIG. 14 is a cross-sectional view for describing the manufacturing process of (FT).

FIG. 2 shows a semiconductor device (T) according to the first embodiment of the present invention;
FIG. 14 is a cross-sectional view for describing the manufacturing process of (FT).

FIG. 3 shows a semiconductor device (T) according to the first embodiment of the present invention;
FIG. 14 is a cross-sectional view for describing the manufacturing process of (FT).

FIG. 4 shows a semiconductor device (T) according to the first embodiment of the present invention;
FIG. 14 is a cross-sectional view for describing the manufacturing process of (FT).

FIG. 5 shows a semiconductor device (T) according to the first embodiment of the present invention;
FIG. 14 is a cross-sectional view for describing the manufacturing process of (FT).

FIG. 6 shows a semiconductor device (T) according to the first embodiment of the present invention;
FIG. 14 is a cross-sectional view for describing the manufacturing process of (FT).

FIG. 7 shows a semiconductor device (T) according to the first embodiment of the present invention;
FIG. 14 is a cross-sectional view for describing the manufacturing process of (FT).

FIG. 8 shows a semiconductor device (T) according to the first embodiment of the present invention.
FIG. 14 is a cross-sectional view for describing the manufacturing process of (FT).

FIG. 9 shows a semiconductor device (T) according to the first embodiment of the present invention;
FIG. 14 is a cross-sectional view for describing the manufacturing process of (FT).

FIG. 10 is a graph showing the dry oxidation time and the unevenness of the surface of the polycrystalline silicon film.

FIG. 11 is a graph showing the relationship between the unevenness of the surface of a polycrystalline silicon film and the breakdown voltage of a TFT using the polycrystalline silicon film as an active layer.

FIG. 12 is a graph showing a relationship between a dry oxidation time and a field-effect mobility of a TFT using a polycrystalline silicon film as an active layer in the first embodiment.

FIG. 13 is a sectional view showing a liquid crystal display (LCD) to which the TFT according to the first embodiment is applied.

FIG. 14 is a plan view showing a liquid crystal display panel in which a display pixel portion and a peripheral driving circuit are formed on the same substrate.

FIG. 15 is a block diagram showing a circuit configuration of a liquid crystal display (LCD) of the present invention.

FIG. 16 is an equivalent circuit diagram of the liquid crystal display (LCD) of the present invention.

FIG. 17 is a cross-sectional view for explaining the manufacturing process of the semiconductor device (TFT) according to the second embodiment of the present invention.

FIG. 18 is a cross-sectional view for explaining the manufacturing process of the semiconductor device (TFT) according to the second embodiment of the present invention.

FIG. 19 is a cross-sectional view for explaining the manufacturing process of the semiconductor device (TFT) according to the third embodiment of the present invention.

FIG. 20 is a cross-sectional view for explaining the manufacturing process of the semiconductor device (TFT) according to the third embodiment of the present invention.

FIG. 21 is a cross-sectional view for explaining the manufacturing process of the semiconductor device (TFT) according to the third embodiment of the present invention.

FIG. 22 is a cross-sectional view for explaining the manufacturing process of the semiconductor device (TFT) according to the third embodiment of the present invention.

FIG. 23 is a cross-sectional view for explaining the manufacturing process of the semiconductor device (TFT) according to the third embodiment of the present invention.

FIG. 24 is a cross-sectional view for explaining the manufacturing process of the semiconductor device (TFT) according to the third embodiment of the present invention.

FIG. 25 is a cross-sectional view for explaining the manufacturing process of the semiconductor device (TFT) according to the third embodiment of the present invention.

FIG. 26 is a cross-sectional view for explaining the manufacturing process of the semiconductor device (TFT) according to the third embodiment of the present invention.

FIG. 27 is a sectional view showing a liquid crystal display (LCD) to which the TFT according to the third embodiment is applied.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Transparent insulating substrate 2 Amorphous silicon film 3 Polycrystalline silicon film 4 Silicon dioxide film 4a Silicon dioxide film 6 Gate insulating film 7 Polycrystalline silicon film 8 Gate electrode

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Claims (5)

[Claims] A step of forming a semiconductor layer on a substrate, a step of forming an oxide film by oxidizing a surface of the semiconductor layer, and a step of flattening the surface of the semiconductor layer after removing the oxide film. Performing the step of: oxidizing the surface of the semiconductor layer after planarization to form an oxide film; and removing the oxide film to expose the surface of the semiconductor layer. Of manufacturing a semiconductor device. 2. The semiconductor device according to claim 1, wherein the thickness of the oxide film formed after the flattening step is smaller than the thickness of the oxide film formed before the flattening step. Production method. 3. The semiconductor device according to claim 1, wherein the step of forming the semiconductor layer includes a step of forming a polycrystalline semiconductor layer by polycrystallizing the amorphous semiconductor layer. Production method. 4. The method according to claim 1, wherein the semiconductor layer includes a silicon layer. 5. The method according to claim 1, wherein the semiconductor layer includes an active layer of a thin film transistor.