JP2000022093A - Self-destructive semiconductor device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reliably prevent tampering with memory contents of a semiconductor integrated circuit. SOLUTION: An IC chip 12a is flip-chip mounted on an electrode base, and a back surface of the IC chip 12a is connected to a power supply source 6.
Optically shielded with a. A destruction capacitor 3 for storing an electric charge for self-destruction by the destruction circuit 2 is provided integrally with the integrated circuit 1, and is usually provided separately from a power supply source 6 a via a connection terminal 10. The charge is stored in the capacitor 3. When the power supply 6a is removed for the purpose of falsifying the memory contents of the integrated circuit 1, a change in the voltage between the connection terminals is detected by the voltage change detection circuits 5-1 to 5-n,
By switching the control circuit or the element 4a, the charge of the destruction capacitor 3 is supplied to the destruction circuit 2 and self-destruction is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a semiconductor integrated circuit for storing and processing highly confidential and important information. It is about security technology.

[0002]

2. Description of the Related Art A semiconductor integrated circuit (Large-Scale Integrat)
In order to analyze the function, operation method, circuit method, circuit pattern, stored data, and the like of an integrated circuit of a semiconductor device on which an ed circuit (LSI) is formed, a semiconductor device is conventionally provided in the semiconductor device as shown in FIG. There is a method in which a search power supply is connected to the external connection electrode pads 7 (7-1 to 7-8), an electric signal is supplied, and the input / output of terminal signals is measured by an LSI tester or the like.

In order to analyze them, the circuit block configuration and the circuit pattern itself are observed using a shape recognition device such as an optical microscope from the surface of the semiconductor device, and the process proceeds one step further using an electron beam tester or the like. Electrode pad 7
There is a method of observing a potential signal that does not appear on the wiring inside the integrated circuit. Therefore, in the current IC card 13, it is possible to open and dissect the IC module 11, read out the information inside the IC chip 12, analyze the contents of the memory, and falsify it, which is a problem from the viewpoint of security. .

FIG. 12 shows an example of the configuration of an IC module 11 in a current IC card 13. In FIG. 12, (a) is a plan view showing a circuit block arrangement in a semiconductor integrated circuit mounted on the IC card 13. (B) is a sectional view, and (c) is a sectional view showing an example of mounting an IC module. As shown in FIG. 12C, the card thickness is 0.76 mm.
The IC module 11 is mounted on the IC card 13 with a hot melt adhesive 34. in this case,
In the IC module 11, the IC chip 12 is die-bonded to a glass epoxy substrate 36 on which a contact pattern 35 corresponding to an electrode of a contact type IC card is formed, and the external connection electrode pad 7 and each contact pattern 35 are connected by a gold wire 37. After wire bonding, the structure is sealed with a mold resin 38.

[0005] As shown in FIG.
2, a data memory (comprising an EEPROM or a ferroelectric memory element) 14 for storing particularly important information such as an encryption code and an authentication code, and a voltage booster circuit for writing / erasing the data memory And other peripheral circuits 1
5, read-only program memory (comprising ROM etc.) 16, central processing unit (CPU) for performing calculations and controls
17, a random access memory (RAM) 18 as a temporary storage memory, and a security authentication microprocessor (MPU) 19 are formed. A data bus and power supply electrode wiring (not shown) are provided around these components.

The data memory 14, the program memory 16, and the authentication microprocessor 19 mounted on the IC card 13 store protocols such as a protocol required for communication, an authentication number code, a usage amount, and a remaining frequency. Various important data are stored. Therefore, it is necessary to prevent such codes and data, as well as information such as circuit blocks and circuit patterns constituting the semiconductor device, from being read by a third party from the viewpoint of preventing forgery or falsification of the IC card. is there.

However, in the semiconductor device as shown in FIG. 12, the circuit configuration blocks, the functional element circuits, the data memory 14 and the program memory 16 and the authentication microprocessor 19 are observed from above.
In addition, the probing measurement using an electron beam can be used to easily read out the contents of the memory element, or cause the authentication microprocessor 19 to malfunction due to a runaway trigger, thereby skipping the authentication process itself. It was possible to do.

In recent high-density mounting technology, the purpose of preventing optical observation from above is to use ICs.
A mounting substrate (electrode base) on which a bump electrode for obtaining electrical connection is formed on the element surface side of the chip on which the semiconductor integrated circuit is formed, and the IC chip is turned over and a contact electrode for external connection is formed; Flip-chip mounting for connection is frequently employed.

However, a technique for observing a circuit near the front surface of the semiconductor substrate from the back surface of the semiconductor substrate on which the semiconductor integrated circuit is formed has been developed in response to a demand for a failure analysis technique or the like. In this method, the transparency of the semiconductor substrate is enhanced by using infrared light having a wavelength that is hardly absorbed by the semiconductor substrate as an observation light source, and a wiring pattern or the like mainly made of metal is observed from the back side of the semiconductor substrate. Thus, the pattern of the lowermost transistor and the wiring pattern of the first layer can be observed nondestructively.

In the flip chip mounting method, since the back surface of the chip is exposed to the outside, it is easy to observe the pattern from the back surface side of the IC chip 12 rather than the element surface side. Of course,
In the case of flip-chip mounting, the back surface of the IC chip is coated with an epoxy resin film for protecting the chip. However, since these can be easily removed by using a chemical, it is difficult to prevent the pattern observation from the back surface side by the protective film.

Therefore, as a method for solving the above problem, the present inventors have built in a thin power supply source and mounted the thin power supply source on the back surface of the IC chip to perform optical observation from the back surface. A self-destructive semiconductor device for blocking is proposed (Japanese Patent Application No. 10-110527). FIG. 13 shows a basic circuit block diagram of the self-destructive semiconductor device. As shown in FIG. 12, the semiconductor integrated circuit 1 on the semiconductor substrate 9 has a data memory 14, a program memory 16, a central processing unit 17, a random access memory 18, and an authentication Although a microprocessor 19 is formed, it is omitted here.

In this configuration, in addition to the above configuration, a destruction circuit for destructing memory information or a destruction circuit having a fuse / anti-fuse provided in a signal wiring path is added as the destruction circuit 2. On 9, a destruction capacitor 3, a control circuit or element 4, and a voltage change detection circuit 5 are formed. The terminal 10 whose terminal voltage is constantly monitored by the voltage change detection circuit 5
, A thin power supply source 6 is connected and arranged.

As a power supply for driving the destruction circuit 2, electric charges stored in a large-capacity destruction capacitor 3 formed on a semiconductor substrate 9 are used. A power supply 6 is connected to the capacitor 3 via a control circuit or an element 4 in a normal operation state, and an output voltage of the power supply 6 is changed by a capacitive-coupled voltage change detection circuit 5 as needed. Is being monitored. If a third party removes the power supply 6 for the purpose of falsifying the IC chip 12,
The voltage change is detected by the capacitively-coupled voltage change detection circuit 5, and the power of the destruction capacitor 3 is reduced via the control circuit or the element 4 which is turned on by the detection signal from the voltage change detection circuit 5. Is applied to Therefore, the memory information of the semiconductor integrated circuit 1 to be falsified is destroyed.

FIGS. 14A and 14B show a basic structure of the self-destructive semiconductor device, wherein FIG. 14A is a plan view and FIG. 14B is a sectional view. The semiconductor substrate 9 on which the self-destructive IC chip 12 is formed has two electrode pads 10 for connecting to the power supply source 6 in addition to the eight electrode pads 7 necessary for the operation as the IC card 13. (Contact pairs) have been added. As shown in FIG. 14B, the thin power supply source 6 is formed by a laminated structure of a positive electrode current collector / terminal plate 21, a positive electrode 22, a solid electrolyte 23, a negative electrode 24, and a negative electrode current collector / terminal plate 25. The periphery is thermally sealed by a sealing material 26. The connection lead 28 of the power supply source and the power supply connection electrode pad 10 are connected by a bump 27.

FIG. 14 shows a method for mounting the power supply source 6.
As shown in (a), it is also possible to arrange the IC chip 12 in parallel. However, when performing face-down flip-chip mounting in which the front side is shielded by an electrode substrate, in order to prevent the back side observation, it is mounted on the back side via the adhesive film 20 as shown in FIG. Is preferred. Thereby, the back side can be optically shielded.

[0016]

In the case of the mounting method shown in FIG. 14B, the two connection terminals 10 of the self-destruction circuit are connected via the positive electrode lead and the negative electrode lead 28 of the thin power supply 6. Connected to However, in such a connection method, the connection terminal 10 and the lead 28 can be easily understood by a third party. After chemically removing the adhesive film 20, the third party bends the connection lead 28 of the power supply 6 to disconnect the power supply 6 without disconnecting the power supply 6.
The back surface of the C chip 12 can be exposed. Actually, when a thin lithium battery is used as the power supply source 6, since the thickness of the battery is about 0.1 mm, the length and width of the battery is about 1 cm each, and the thickness of the connection lead 28 is about 0.03 mm, the battery can be easily bent. It is possible. In this case, the optical shielding by the power supply source 6 is removed without detecting the voltage change by the voltage change detection circuit 5, so that the self-destructive mechanism does not operate and important information is stored in the IC.
There is a problem that analysis is performed from the back surface of the chip. SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and a self-destructive semiconductor device capable of optically shielding an important part of a semiconductor integrated circuit and reliably preventing tampering of memory contents of the semiconductor integrated circuit. The purpose is to provide.

[0017]

According to a first aspect of the present invention, there is provided a self-destructive semiconductor device having a plurality of (n; n is an integer of 1 or more) connecting leads for a positive electrode and a negative electrode. A destruction circuit 2 which has power supply sources 6a and 6b each of which is provided with a power supply source 6a, 6b, and which self-destructs by destroying at least a part of memory information of the semiconductor integrated circuit 12a or disconnecting at least a part of signal wiring; And a plurality (n) of power supplies provided for the positive electrode and the negative electrode of the power supply source for storing the electric charge in the destruction capacitor, respectively. Source connection terminal 10,
A plurality (n) of voltage change detection circuits 5-5 provided for each pair of power supply source connection terminals for the positive electrode and the negative electrode and monitoring the voltage between the terminals of the terminal pair and outputting a detection signal in accordance with the voltage drop. 1 to 5-n and a power supply source and a destruction capacitor during normal operation via a power supply source connection terminal. When a detection signal is output from at least one voltage change detection circuit, the connection is made. And a control circuit or element 4a for connecting the destruction capacitor and the destruction circuit by shutting off the semiconductor integrated circuit, respectively, on the semiconductor substrate 9a. The power supply sources 6a and 6a are provided on the back side of the element surface of the formed semiconductor substrate.
b is arranged. Power supply source 6a,
6b is, for example, a positive electrode current collector, a positive electrode, a solid electrolyte, a negative electrode,
This is a thin power supply source configured by stacking negative electrode current collectors. The destruction circuit 2 applies a charge stored in a destruction capacitor to at least one word line, thereby erasing some data bits stored in the nonvolatile memory element and destroying the memory contents. Further, the destruction circuit 2 is formed by providing a fuse or an anti-fuse in a part of the signal wiring path of the semiconductor integrated circuit, and applying a charge stored in a destruction capacitor to the fuse or the anti-fuse to form a part. Destroy the signal wiring path.
The control circuit or element 4a is composed of one or more semiconductor elements or micro-mechanical switches terminated by capacitance. The voltage change detection circuits 5-1 to 5-n each include a first capacitor, a second capacitor, and a first resistor connected in series, and connect the connection terminal voltage applied to both ends to the first and second terminals. A voltage divider that divides and outputs a voltage from a connection point of a capacitor, and a field effect transistor in which the divided output of the voltage divider is connected to a gate electrode and a destruction capacitor or a driving capacitor is connected to a source electrode. And a voltage change detection unit comprising a second resistor connected to the drain electrode of the field-effect transistor, and outputs a voltage at which the field-effect transistor is turned off from the voltage division unit in a steady state. Then, the voltage at which the field-effect transistor is turned on is divided and output from the voltage-divided output in accordance with the decrease in the connection terminal voltage, and the destruction capacitor or The charge from the driving capacitor is supplied to the second resistor, and outputs a detection signal in response to an increase in the second voltage across the resistor. In the present invention, the power supply sources 6a and 6b are provided with a plurality of connection leads 28 for the positive electrode and the negative electrode, respectively.
a, connection terminals 10 for connecting to a power supply source
Are provided for the positive electrode and the negative electrode, respectively, and the voltage change detection circuits 5-1 to 5-
n, and the voltage between the terminals is constantly monitored. In order to alter the memory contents of the semiconductor integrated circuit, the power supply 6
In order to remove a and 6b, it is necessary to remove a plurality of pairs (n pairs) of contacts, but if any one is removed, a voltage change detection circuit corresponding to this contact detects a voltage drop. The control signal or the element 4a is turned on by this detection signal, and the destruction circuit 2 and the destruction capacitor 3 are connected. As a result, the electric charge stored in the capacitor 3 is applied to the destruction circuit 2. As a result, some wirings or essential memory data of the integrated circuit to be falsified are destroyed, so that falsification becomes impossible.

Further, as described in claim 2 (FIG. 7),
A plurality of connection leads 28 for the positive electrode and the negative electrode (n;
(n is an integer of 1 or more) power supply sources 6a, 6b
And a self-destruction circuit that destroys at least a part of the memory information of the semiconductor integrated circuit 12b or breaks at least a part of the signal wiring.
A destruction capacitor 3 for storing electric charge for self-destruction by the destruction circuit; and a plurality (n) of the power supply sources for accumulating electric charge in the destruction capacitor. A power supply source connection terminal 10 provided, a voltage dividing circuit 8 for dividing a voltage between each of the positive and negative power supply source connection terminals, and a positive power supply source connection terminal The voltage between the positive power supply connection terminal and the output terminal of the voltage dividing circuit or the negative power supply connection terminal and the voltage is provided for each negative power supply connection terminal. A plurality (2n) voltage change detection circuits 5-1 to 5 that monitor a voltage between output terminals of the circuit and output a detection signal in accordance with the voltage drop
-2n, a power supply source and a destruction capacitor are connected via a power supply connection terminal during normal operation, and at least one
When a detection signal is output from one of the voltage change detection circuits, a control circuit or an element 4b that cuts off the connection and connects the destruction capacitor and the destruction circuit is provided on the semiconductor substrate 9b. The power supply sources 6a and 6b are arranged behind the element surface of the semiconductor substrate on which the semiconductor integrated circuit is formed so that the back surface of the circuit is optically shielded. Thus, the power supply 6
a, 6b are provided with a plurality of connection leads 28 for the positive electrode and the negative electrode, respectively, and the semiconductor integrated circuits 12a, 12b are provided with a plurality of terminals 10 for connecting the power supply source respectively for the positive electrode and the negative electrode. A voltage change detection circuit 5-1 for each power supply connection terminal and each power supply source connection terminal for the negative electrode.
.About.5-2n to constantly monitor the voltage between the terminals. In order to falsify the memory contents of the semiconductor integrated circuit, it is necessary to remove a plurality of pairs (n pairs) of contacts when removing the power supply sources 6a and 6b. The voltage drop detection circuit detects the voltage drop. The control circuit or element 4b is turned on by this detection signal, and the destruction circuit 2 and the destruction capacitor 3 are connected. As a result, the electric charge stored in the capacitor 3 is applied to the destruction circuit 2. As a result, some wirings or essential memory data of the integrated circuit to be falsified are destroyed, so that falsification becomes impossible.

Further, as described in claim 3 (FIG. 6),
A plurality of connection leads 28 (n +
1; n is an integer of 1 or more) power supply sources 6a,
6b, a destruction circuit 2 for self-destruction by destroying at least a part of the memory information of the semiconductor integrated circuit 12b or breaking at least a part of signal wiring, and a charge for self-destruction by the destruction circuit. A plurality of (n + 1) power supply source connection terminals 10 provided for each of the positive electrode and the negative electrode of the power supply source for storing electric charges in the destruction capacitor; A voltage dividing circuit 8 for dividing the voltage between the power supply source connecting terminals, one for each negative electrode, and a voltage dividing circuit 8 provided for each positive power supply source connecting terminal to which no voltage dividing circuit is connected and for the negative electrode Voltage between the positive power supply connection terminal and the output terminal of the voltage divider circuit, or the negative power supply connection terminal and the voltage Monitors the terminal voltage of the output terminal of the road, and outputs a detection signal according to the voltage drop plurality (2
n) The voltage change detection circuits 5-1 to 5-2n are connected to a power supply source and a destruction capacitor via a power supply source connection terminal during normal operation, and are detected from at least one voltage change detection circuit. When a signal is output, a control circuit or an element 4b for disconnecting the connection and connecting the destruction capacitor and the destruction circuit is provided on the semiconductor substrate 9b, and the back surface of the semiconductor integrated circuit is optically controlled. As shielded,
The power supply sources 6a and 6b are arranged behind the element surface of a semiconductor substrate on which a semiconductor integrated circuit is formed.

The power supply source 6a includes an electrode base 32 on which the semiconductor substrate is mounted, on which the external connection terminals 62-1 to 62-8 are formed. Is provided with the connection lead 28 at an end in a plurality of directions including at least both opposing ends.
Is connected to the power supply connection terminal 10 formed on the element surface side of the semiconductor substrates 9a and 9b around the ends of the semiconductor substrates 9a and 9b. 32 so as to face the semiconductor substrate 9.
External connection terminals 7-1 formed on the element surface side of a and 9b
7-8 and the external connection terminals 62-1 to 6-6 of the electrode base 32.
2-8. As described above, the semiconductor integrated circuits 12a and 12b (the semiconductor substrates 9a and
9b) is flip-chip mounted on the electrode base 32. In addition, since the power supply source 6a includes the connection leads 28 at the ends in a plurality of directions including at least the opposite ends,
The connection leads 28 are connected to ends in a plurality of directions including at least both ends of the semiconductor substrates 9a and 9b. For this reason,
It becomes difficult to bend the connection lead of the power supply source and remove the optical shielding by the power supply source as in the related art.

According to a fifth aspect of the present invention, the external connection terminals 62-1 to 62-8 and a plurality (2n or 2 × (n + 1)) of power supply source connection terminals for each of the positive electrode and the negative electrode are provided. And an electrode base 32a on which the semiconductor substrate is mounted.
The external connection terminals 7-1 to 7-8 formed on the element surface side of the semiconductor substrates 9a and 9b and the external connection terminals of the electrode substrate 32a such that the element surfaces a and 9b face the electrode base 32a. 62-1 to 62-8 and 2n or 2 × formed on the element surface side of the semiconductor substrates 9a and 9b.
(N + 1) power supply source connection terminals 10 and electrode bases 3
2a or 2 × (n + 1) power supply source connection terminals 63, and the power supply sources 6a and 6b
The connection leads 28 are provided at the ends in a plurality of directions including at least the opposite ends, and the connection leads 28 are connected to 2n or 2 × (n + 1) power supply source connection terminals 64 of the electrode base 32a. Things. in this way,
Semiconductor integrated circuits 12a and 12b (semiconductor substrates 9a and 9
b) is flip-chip mounted on the electrode substrate 32a, and the power supply 6b is connected to the semiconductor integrated circuits 12a and 12b (semiconductor substrates 9a and 9b) via the electrode pads 63 and 64 of the electrode substrate 32a.
9b). Accordingly, the self-destructive mechanism is activated regardless of whether the power supply source 6b or the electrode base 32a is removed.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] Next, an embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a circuit block diagram of a self-destructive semiconductor device according to a first embodiment of the present invention. FIG. 2A is a bottom view showing an example of the arrangement of the self-destructive semiconductor device in FIG.
2B is a cross-sectional view taken along line AA of FIG. 2A, and FIG. 2C is a side view of the self-destructive semiconductor device.
The same components as in FIG. 4 are denoted by the same reference numerals. 2 (a) and 2 (b) show a state before performing flip chip mounting described later, and FIG. 2 (c) shows a mold resin 38, an anisotropic conductive adhesive resin 61 and an electrode base 32. I see through.

On the semiconductor substrate 9a, as a semiconductor integrated circuit 1 necessary for an original IC card function, a nonvolatile data memory (EEPROM or ferroelectric memory) storing particularly important information such as an encryption code and an authentication code is stored. , A peripheral circuit 15 such as a voltage booster circuit for writing and erasing the same, a read-only program memory (comprising a ROM or the like) 16, a central processing unit for performing calculations and controls Unit (CPU) 17, random access memory (RAM) 1 as a memory for temporary storage
8. Security authentication microprocessor (MP
U) 19 are formed.

In the present invention, in addition to the above configuration, a destruction circuit for destructing memory information or a destruction circuit provided with a fuse / anti-fuse in a signal wiring path is added to the semiconductor substrate 9a as the destruction circuit 2. Further, a destruction capacitor 3, a control circuit or element 4a, and voltage change detection circuits 5-1 to 5-n are added. Thus, a self-destructive IC chip 12a is formed.

Here, the destruction circuit 2 will be described with reference to a specific example. For example, when a flash EEPROM is used for the data memory 14, a voltage of 12 to 15 V is required to erase the memory information, and a booster circuit for erasing that generates such a high voltage is a data memory. Fourteen peripheral circuits 15 are formed.

When a current lithium primary battery is used as the power supply source 6a, the output voltage is 3.6 V and the thickness is 0.1 mm. In this case, a required voltage may be generated by connecting the power supply sources 6a in series and stacking several layers, and the electric power may be accumulated in the destruction capacitor 3 by this power. Further, the power supply source 6a is not limited to a lithium battery, but may be a paper battery or the like.

In a flash EEPROM, when a voltage of 12 to 15 V is applied in a pulsed manner to a word line composed of a control gate made of two-layer polysilicon, electrons are injected from a substrate to a capacitively coupled floating gate electrode. And all the bits are equally rewritten as "1" or "0". Thus, the memory information can be destroyed.

When a ferroelectric memory element is used for the data memory 14, since the erasing voltage is as low as about 5 V, charges are accumulated from two or more power supply sources 6a connected in series. The destruction circuit 2 can be configured more easily by directly connecting a large-capacity destruction capacitor 3.

In any case, in the present invention, the electric charge stored in the large-capacity destruction capacitor 3 formed on the semiconductor substrate 9a is used as a power supply source for driving the destruction circuit 2. It is desirable that the destruction capacitor 3 has a structure in which a thermal oxide film (SiO ₂ ) formed on the semiconductor substrate 9a is used as an insulating film and has a large capacity. This is because, in the case of a thermal oxide film, it is possible to use features such as a very small leak current, and a large amount of electric charges can be accumulated in the capacitor 3 by the thin power supply source 6a having a small energy density, and energy consumption due to leakage is reduced. Because it can be reduced.

As shown in FIG. 2, a thin power supply source 6a for accumulating charges in the destruction capacitor 3 includes a positive electrode current collector / terminal plate 21, a positive electrode 22, a solid electrolyte 23, and a negative electrode 2 as shown in FIG.
4, formed by a laminated structure of the negative electrode current collector and terminal plate 25, and the periphery thereof is heat-sealed and sealed by a sealing material 26. The power supply source 6a is provided with 2n connection leads 28 (n is an integer of 1 or more), that is, n positive leads connected to the terminal plate 21 and n negative leads connected to the terminal plate 25. ing.

On the other hand, on the semiconductor substrate 9a on which the IC chip 12a is formed, eight external connection electrode pads 7 (7-1 to 7-8) necessary for operation as an IC card are provided.
And an electrode pad 1 for connecting to a power supply source 6a.
2n 0s are added, that is, n are added for the positive electrode lead of the power supply source 6a and n are added for the negative electrode lead, thereby realizing multi-contact with the power supply source 6a.

Capacitively-coupled voltage change detection circuits 5-1 to 5-n are provided for each electrode pad pair including one electrode pad 10 for each of the positive electrode and the negative electrode, and at least n breakdown capacitors 3 are provided. Is provided. The voltage change detection circuits 5-1 to 5-n monitor the voltage of the corresponding electrode pad pair, that is, the output voltage of the power supply source 6a as needed.

The control circuit or element 4a includes an OR logic circuit 29 for calculating the logical sum of the detection signals output from the voltage change detection circuits 5-1 to 5-n, and an output of the OR logic circuit 29 as a control input. 2n switches 30 to be used.

In the normal operation state, the positive electrode of the power supply 6a is connected to one end of the destruction capacitor 3 via the positive electrode pad 10 and the switch 30, and the negative electrode of the power supply 6a is The electrode pad 10 and the switch 30 are connected to the other end of the destruction capacitor 3.

Here, the mounting method of the present embodiment will be briefly described. First, the external connection electrode pads 7-1 to 7-8 on the IC chip 12a and the power supply source connection electrode pad 1
A bump 27 made of gold (Au) or the like is formed at 0. The power supply source 6a is connected to the element surface of the IC chip 12a (FIG. 2A).
(A lower surface in FIG. 2C) is adhered by an adhesive film 20 to the back surface. The connection lead 28 of the power supply 6a and the power supply connection electrode pad 10 of the IC chip 12a are connected by the bump 27.

With the self-destruction mechanism activated in this manner, the external connection electrode pad 7 of the IC chip 12a is
-1 to 7-8 are connected to the contact patterns 35 (35-1 to 35-8) formed on the electrode base 32 and corresponding to the electrode terminals of the IC card by the flip chip mounting technique.

FIG. 3 shows an IC chip 12 a on an electrode substrate 32.
FIG. 6 is a diagram showing a state of flip chip mounting on which is mounted.
On the IC chip mounting surface of the electrode substrate 32 made of glass epoxy, the external connection electrode pads 7-
External connection electrode pads 62-1 to 1-8 corresponding to 1 to 7-8
62-8 are formed. Then, each electrode pad 62
-1 to 62-8 are connected to the contact patterns 35-1 to 35-8 by through holes and the like, respectively.

To perform flip-chip mounting, first, an anisotropic conductive adhesive resin 61 is applied to the entire IC chip mounting surface of the electrode substrate 32. The amount of the anisotropic conductive adhesive resin 61 is about 1/2 to 1/3 of the volume of the IC chip 12a. This amount is preferably such that the resin 61 is blown up on the chip side surface in the final mounting shape.

When the area of the IC chip 12a is small, it may be applied to the element surface of the IC chip 12a.
Next, the element surface of the IC chip 12a and the I
The C chip mounting surfaces face each other and the external connection electrode pads 7-1 to 7-8 of the IC chip 12a are connected to the external connection electrode pads 62-1 to 62-8 of the electrode base 32. Electrode pads 7-1 to 7-8 and electrode pad 62-1
６２62-8 are aligned, and pressure is applied from the back surface of the IC chip 12a.

Pressing has two purposes. The first object is to align the element surface of the IC chip 12a and the IC chip mounting surface of the electrode base 32, and to crush the bump 27 by applying pressure (plastic deformation), thereby absorbing a variation in the height of the bump 27. That is.

The second object is to set a gap between the electrode pads 62-1 to 62-8 formed on the electrode base 32 and the bumps 27 formed on the electrode pads 7-1 to 7-8 of the IC chip 12a. Extrudes the anisotropic conductive adhesive resin 61 existing in the electrode pads 62-1 to 62-8 and the electrode pads 7-1 to 7-.
8 is electrically connected via the bump 27.

Next, with the above-mentioned pressurized state,
The anisotropic conductive adhesive resin 61 is cured. The anisotropic conductive adhesive resin 61 is formed on the electrode pads 62-1 to 62-8 formed on the electrode base 32 and the electrode pads 7-1 to 7-8 of the IC chip 12a by shrinkage during curing. The pressed bump 27 is pressed into contact with the bump 27. For this purpose, the anisotropic conductive adhesive resin 61 needs to have such characteristics that the following equation is satisfied.

Α, β>ω> ρ (1) where α is the IC chip 12 a and the anisotropic conductive adhesive resin 6.
1, β is the adhesive force between the electrode substrate 32 and the anisotropic conductive adhesive resin 61, ω is the shrinkage of the anisotropic conductive adhesive resin 61 during curing, and ρ is the anisotropic conductive adhesive resin 61 itself. Represents the thermal stress of

When the anisotropic conductive adhesive resin 61 has photocurability, the resin 61 is cured by irradiating ultraviolet rays.
When the photo-curing resin 61 is used, since the electrode base 32 is opaque, the IC chip 12a and the power supply source 6a are used.
Is irradiated from the side surface of the chip to cure from the resin 61 on the chip side surface, and the resin 61 in the unexposed area is naturally cured (cured at room temperature).

When the anisotropic conductive adhesive resin 61 has thermosetting properties, the resin 61 is cured by heating.
However, when a thin lithium battery in which the conduction of lithium ions in the solid electrolyte 23 is an electromotive force is used as the power supply source 6a, if heating is continued at a high temperature of 70 ° C. or more for a long time, the power supply source 6a It is not preferable because it causes deterioration. That is, the thermosetting resin 6 usable in this case is used.
As a specification of 1, it must have a property of curing at 70 ° C. or lower.

Therefore, it is preferable to use the photocurable resin 61 that cures even at room temperature by irradiation with ultraviolet rays in the present embodiment in which the power supply source 6a and the IC chip 12a are mounted as an integrated structure. When the photo-curing anisotropic conductive adhesive resin 61 is used, there is no need to apply heat and heat-curing at the time of connection, so that excessive heat stress is not applied to the IC chip 12a or the electrode substrate 32, and the power by heating is reduced. The destruction of the supply source 6a can be avoided.

When the curing of the anisotropic conductive adhesive resin 61 is completed, the pressurization is stopped. Thus, the electrical connection between the IC chip 12a and the contact patterns 35-1 to 35-8 and the mechanical holding of the IC chip 12a by the electrode base 32 are completed. Thus, the mounted IC module 11
a is sealed with a mold resin 38 as shown in FIG. 2C, and is mounted on a plastic case of an IC card with a hot melt adhesive as in FIG.

The power supply source 6a supplies power to the destruction circuit 2, the destruction capacitor 3, the control circuit or element 4a, and the voltage change detection circuits 5-1 to 5-n.
Power is supplied to the semiconductor integrated circuit 1 excluding the destruction circuit 2 from the outside via a power supply terminal of the external connection electrode pad 7.

A third party for the purpose of falsifying the IC chip 12a first removes the IC module 11a from the plastic case, and then uses a chemical to mold resin 38a.
Is removed. Then, in order to perform observation from the back surface of the IC chip 12a, the power supply source 6a mounted on the back surface of the IC chip 12a is removed. In this embodiment, however, the power supply source 6a and the IC chip 12a Are connected to the n pairs of connection leads 28 for the positive electrode and the negative electrode by the electrode pad 10, and if any one of these connections is removed, the voltage change detection circuits 5-1 to 5-
The voltage change is detected by one of n.

When voltage change detection circuits 5-1 to 5-n detect a voltage change and output a detection signal, this detection signal
The signal is supplied to the control input of the switch 30 via the R logic circuit 29. As a result, the switch 30 switches to the side where the destruction capacitor 3 and the destruction circuit 2 are connected, and the power of the destruction capacitor 3 is applied to the destruction circuit 2. Thus, the self-destruction mechanism is activated, and the memory information of the semiconductor integrated circuit 1 is destroyed.

The level of memory destruction is determined by simply cutting a fuse or an anti-fuse incorporated in a signal wiring path in an integrated circuit from a level for simply erasing memory information in accordance with the voltage of the power supply source 6a. Semiconductor integrated circuit 1
It can be at the level of destroying itself.

For example, assuming that one thin lithium primary battery is used as the power supply source 6a,
The output voltage due to the electric charge accumulated in the memory becomes about 3.6 V at most, and the operation performed by the destruction circuit 2 is limited to only the erasure of a part of the memory information. In this case, since the important confidential information is deleted, the bit information and the like of the memory are not leaked to a third party. However, the normally operable IC chip 12a remains. The IC chip 12a can be reused if necessary bit information is obtained by another system of fraud and newly written.

In order to avoid reuse of the IC chip 12a, it is necessary to reliably destroy the falsified semiconductor integrated circuit 1. In this case, by connecting a plurality of thin lithium primary batteries in series and using them as the power supply source 6a, the output voltage due to the charges accumulated in the destruction capacitor 3 is increased by 3.6V × the number of battery stages, A current is caused to flow through a destruction circuit 2 including a fuse and an anti-fuse portion provided in the integrated circuit 1, thereby irreversibly destroying a part of the signal wiring of the semiconductor integrated circuit 1.
Avoid reuse of the chip 12a.

The current lithium primary battery is connected to the power supply 6a.
When used as the IC chip, the thickness of the IC chip 12 is 0.05
mm and the battery thickness is 0.1 mm.
Under the condition that the thickness of the lithium secondary battery 3a does not exceed 0.76 mm, five lithium secondary batteries are stacked as a power supply source 6a (3.6).
× 5 = 18V), a total of 0.55mm (= 0.1m
m × 5 + 0.05 mm).

[Second Embodiment] FIG. 4 is a bottom view showing an example of the arrangement of a self-destructive semiconductor device according to a second embodiment of the present invention, and FIG. FIG. 5 is a diagram showing a state of flip-chip mounting, and the same components as those in FIGS. 1 to 3 are denoted by the same reference numerals. FIG. 4A shows a state before flip-chip mounting is performed.

In this embodiment, the circuit block configuration of the self-destructive semiconductor device is the same as that of FIG. Similarly to the first embodiment, the external connection electrode pads 62 corresponding to the external connection electrode pads 7-1 to 7-8 of the IC chip 12a are provided on the IC chip mounting surface of the electrode base 32a of the present embodiment. -1 to 62-8 are formed, and each electrode pad 62-
Nos. 1 to 62-8 are connected to the contact patterns 35-1 to 35-8 by through holes and the like, respectively.

Further, on the IC chip mounting surface of the electrode substrate 32a, there are provided 2n pieces (n for the positive electrode and the negative electrode) corresponding to the 2n power supply source connection electrode pads 10 of the IC chip 12a.
Power supply source connection electrode pads 63 are formed, and 2n power supply source connections (n for the positive and negative electrode leads) corresponding to the 2n connection leads 28 of the power supply source 6b are formed. Electrode pad 64 is formed. Each of the electrode pads 63 corresponds to the corresponding electrode pad 6.
4 and are connected by wiring.

Here, the mounting method of the present embodiment will be briefly described. In order to perform flip-chip mounting, anisotropic conductive adhesive resin 61 is applied to the entire IC chip mounting surface of electrode base 32a, as in the first embodiment.

Subsequently, as shown in FIG.
The element surface of IC chip 2a faces the IC chip mounting surface of electrode base 32a, and electrode pads 7-1 to 7- of IC chip 12a.
8 are connected to the electrode pads 62-1 to 62-8 of the electrode base 32a, and the electrode pads 10 of the IC chip 12a are connected to the electrode pads 63 of the electrode base 32a. Pressure is applied from the back surface of the IC chip 12a.

Next, in the state where the pressure is applied, the anisotropic conductive adhesive resin 61 is cured in the same manner as in the first embodiment, and the pressure is stopped when the curing of the resin 61 is completed. In this manner, the flip chip mounting of the IC chip 12a and the electrode base 32a is performed using all four sides of the IC chip 12a.

Next, the power supply source 6b is bonded to the back surface of the IC chip 12a which is flip-chip mounted on the electrode substrate 32a by the adhesive film 20. The connection lead 28 of the power supply source 6b and the power supply connection electrode pad 64 of the electrode base 32a are connected by a bump (not shown).

As described above, the mounting method in the present embodiment is the same as that in the first embodiment except that the mounting order is different. In the first embodiment, a third party aiming at falsification of the IC chip 12a uses the electrode base 32 and the IC chip 12a.
If the flip chip mounting interface side is removed first, the self-destruction mechanism described above does not start, so that the semiconductor integrated circuit remains operable, and important information may be analyzed.

On the other hand, according to the present embodiment, the first problem of the embodiment can be avoided. That is, a third party aiming at falsification of the IC chip 12a
Unless the power supply source 6b is removed, the IC chip 12a
Of the IC chip 12a cannot be observed unless the electrode base 32a is removed.

In order to remove the power supply source 6b, it is necessary to remove 2n connection leads 28 from the electrode base 32a.
If any one of these connections is removed, the self-destruction mechanism is activated as in the first embodiment, and the memory information of the semiconductor integrated circuit 1 is destroyed.

On the other hand, the power supply source 6b is connected to the electrode base 32a.
Is connected to the IC chip 12a via the electrode pads 63 and 64, and when the electrode base 32a is removed, the power supply source 6b is electrically disconnected, and the self-destruction mechanism is activated. The memory information of the integrated circuit 1 is destroyed. That is, in the present embodiment, the self-destruction mechanism is activated regardless of whether the power supply source 6b or the electrode base 32a is removed.

[Third Embodiment] In the first and second embodiments, the configuration shown in FIG. 1 is used as the circuit block configuration of the self-destructive semiconductor device, but another configuration may be used. FIG. 6 is a circuit block diagram of a self-destructive semiconductor device according to a third embodiment of the present invention. The same reference numerals are given to the same components as those in FIG.

In this embodiment, one or two of the embodiments
In comparison with the power supply source 6a or 6b, the connection leads 28 for the positive electrode and the negative electrode of the power supply source 6b are each increased by one, and the electrode pads 10 for the positive electrode and the negative electrode are similarly increased by one each.

To the newly added pair of electrode pads 10, for example, a voltage dividing circuit 8 in which two capacitors are connected in series is connected. Voltage change detection circuits 5-1 to 5-n
Are provided for each of the positive electrode pads 10 to which the voltage dividing circuit 8 is not connected, and the voltage change detection circuits 5- (n + 1) to
5-2n is provided for each negative electrode pad 10 to which the voltage dividing circuit 8 is not connected.

The voltage change detection circuits 5-1 to 5-
One input of 2n is connected to the output terminal of the voltage dividing circuit 8. The control circuit or the element 4b includes the voltage change detection circuits 5
It has an OR logic circuit 29a for calculating the logical sum of the detection signals output from -1 to 5-2n, and 2n switches 30 having the output of the OR logic circuit 29a as a control input.

The other configuration is the same as that of FIG. In the present embodiment, by connecting the power supply source 6b to the voltage divider circuit 8, the ground potential is internally set to a different potential from the power supply source 6b, and the ground potential (the output of the voltage divider circuit 8) is set. The voltage between the terminal pads (potentials) and the 2n electrode pads 10 is arranged so as to be individually detected by the capacitively-coupled voltage change detection circuits 5-1 to 5-2n.

Thus, the same effect as that of the first embodiment can be obtained. Although the present embodiment and the first embodiment are functionally the same, when considering a manufacturing process, for example, when manufacturing with CMOS, it is easier to make a configuration like this embodiment. This has the effect.

[Fourth Embodiment] In the third embodiment,
Although the number of the connection leads 28 and the number of the electrode pads 10 are increased as compared with the first and second embodiments, the number may be the same as that of the first embodiment. In this case, as shown in FIG. 7, the voltage dividing circuit 8 may be connected to any one of the positive electrode pads 10 and any one of the negative electrode pads 10.

[Fifth Embodiment] Next, a fifth embodiment of the present invention will be described with reference to FIG. In the present invention, the output voltages of the power supply sources 6a and 6b must be constantly monitored by the voltage change detection circuits 5-1 to 5-2n. However, as the power supply sources 6a and 6b,
When a thin lithium battery is mounted, the capacity density is 1.
Since it is as small as about 5 mAh / cm ² (single-stage cell, 0.1 mm), in a circuit configuration in which a large current is constantly flowing,
The battery life becomes extremely short.

Therefore, voltage change detection circuits 5-1 to 5
It is an essential condition for the -2n configuration that a capacitively-coupled circuit configuration that does not allow a leak path to match a current path related to the operation. FIG. 8 shows an example of such a capacitively-coupled voltage change detection circuit. In this embodiment, a MOS field effect transistor is used as the voltage change detecting element.

[0075] Power source 6a, the output voltage of 6b is divided by a voltage voltage-dividing capacitor C _1, C ₂ and the resistor R _1,
The voltage is input to the gate of the voltage change detection transistor 31 from the connection point of the voltage dividing capacitors C ₁ and C ₂ . Since the power consumption of the voltage change detection transistor 31 is very small, the voltage stored in the destruction capacitor 3 can be used as the drive voltage, or a large-capacity capacitor provided separately from the destruction capacitor 3 can be used. The voltage stored in the driving capacitor may be used.

When a third party for the purpose of falsifying the IC card disconnects the power supply source 6a or 6b, the capacitance-divided voltage set near the threshold voltage of the transistor 31 fluctuates. The transistor 31 turns on. Accordingly, current flows between the source and the drain of the transistor 31, a voltage drop occurs between the resistor R ₂ terminals. This voltage drop is output as a detection signal to the control circuit or the elements 4a and 4b via the post-amplifier circuit 33.

[Sixth Embodiment] Next, a sixth embodiment of the present invention will be described with reference to FIG. Since the capacity of the thin power supply sources 6a and 6b to be mounted is limited, the switch 30 in the control circuit or the elements 4a and 4b is limited.
It is desirable that the power consumption be as low as possible. Normally, the switch 30 is a semiconductor switch configured by combining transistors. In this case, however, it is a major problem to reduce power consumption due to a sub-threshold current leak when the switch 30 is off.

In the present invention, as such a switch 30 of low power consumption, it is possible to use a micromechanical switch which is a kind of micromechanical element having a movable portion and opens and closes contacts using electrostatic attraction. is there. FIG. 9 shows an example of a micro-mechanical switch that opens and closes contacts using such electrostatic attraction. In the figure, (a) is a sectional view, and (b) is a plan view. Note that FIG.
0 is shown.

As shown in FIG. 9A, in the micromechanical switch, a movable suction electrode 47 is installed through a support beam 48 and a connection electrode 49a. When no voltage is applied to the fixed suction electrode 50, the movable contact electrode 51
Are pressed against the fixed contact electrodes 52b and 52c by the elastic force (upward) of the support beam 48.

As a result, the COMM input terminal 53 is electrically connected to the output 2 terminal 54b. The fixed contact electrode 52
The b and 52c are supported by the contact electrode support 55, and are electrically connected to the COMM input terminal 53 and the output 2 terminal 54b via the connection electrodes 49b and 49c, respectively. The movable contact electrode 51 is electrically insulated from the support beam 48 by the insulating film 57 and is mechanically fixed to the support beam 48.

When a voltage is applied to the fixed suction electrode 50 from the movable contact operation power supply terminal 56, the support beam 48 is generated by electrostatic attraction acting between the fixed suction electrode 50 and the movable suction electrode 47.
Goes down. Then, the movable contact electrode 51 becomes the fixed contact electrode 5
2b, 52c, the fixed contact electrode 52 on the opposite side
a, 52d. As a result, the COMM input terminal 53 becomes the output 1 terminal 5 via the movable contact electrode 51.
4a.

When the application of the voltage to the fixed suction electrode 50 is stopped, the movable contact electrode 51 moves upward by the elastic force of the support beam 48. As a result, the movable contact electrode 51 is again pressed against the fixed contact electrodes 52b and 52c, and the COMM
The input terminal 53 conducts with the output 2 terminal 54b. Thus, the current path is switched by the micro mechanical switch.

Although the OR logic circuit 29 is not shown in FIG. 9, the OR logic circuit 29 can be composed of a CMOS or the like, and its output may be connected to the movable contact operating power supply terminal 56. Further, one end of the destruction capacitor 3 may be connected to the COMM input terminal 53, one end of the destruction circuit 2 may be connected to the output 1 terminal 54a, and the electrode pad 10 may be connected to the output 2 terminal 54b.

[Seventh Embodiment] Next, a seventh embodiment of the present invention will be described with reference to FIG. In the present invention, the configuration of the destruction circuit 2 is important for avoiding reuse of the IC chip 12a. In the present invention, the function of the integrated circuit is reliably destroyed by destroying a partial circuit including a fuse or an anti-fuse by using the power stored in the breakdown capacitor 3.

As shown in FIG. 10, the most important RO in the operation of the IC chip 12a is the circuit to be destroyed.
A readout circuit of an M boot circuit is considered as an example. In FIG. 10A, a decoder input / output line portion of an address signal of a read circuit, for example, signal lines C _A0 , C _{A1 ,.}
An antifuse 39 is provided in a part of C _A2 , C _A3 , R _A0 , R _A1 , R _A2 , and R _A3 to constitute a destruction circuit 2.

FIG. 10B shows a plan pattern diagram of the cell configuration in each cell portion. Input / output of the row decoder 40 is performed via a polysilicon word line constituting a gate electrode of a cell transistor constituting each of the cells 100 to 133, and a bit line of the first layer Al is perpendicular to the word line. 43 (B ₀ , B ₁ , B ₂ , B ₃ ) is running.
Here, it is provided with antifuse 39 by a thin oxide film on the portion of the signal output line R _A1 of the gate G _R1 row decoder 40 (in the drawing "×" mark).

FIGS. 11A and 11B show the structure of the antifuse. FIG. 11A is a plan view and FIG. 11B is a sectional view taken along the line AA ′. As shown in FIG. 11B, a polysilicon word line 42 normally runs on a P-type Si semiconductor substrate while being insulated by an element isolation insulating film (LOCOS) 46. The antifuse 39 does not partially form the element isolation insulating film 46, but after forming a thin gate oxide film 39a thereon, implants phosphorous at a high concentration to provide an N + diffusion layer 45, which is used as a ground. .

N + insulated by this gate oxide film 39a
When a voltage is applied to the polysilicon word line 42 running on the diffusion layer 45 from the large-capacity destruction capacitor 3 storing the charge from the power supply source 6, the gate oxide film 39a is broken down, and the word line 42 is broken. Short circuit with the board. As a result, all the cells addressed by the row decoder 40 using the word line 42 (cells 101, 111,
121, 131) cannot be read, and reading from the ROM is reliably prevented.

The thickness of the gate oxide film 39a is 8
nm, 20 MV / cm
A very high electric field is required. In this case, the voltage required for destruction is 16 V. When a thin lithium secondary battery is used as the power supply source 6, the voltage is 3.6 V × 5 stages = 18 V. Therefore, four to five stages are connected in series. By storing this power in the large-capacity destruction capacitor 3, sufficient destruction power can be obtained.

Alternatively, a portion of the polysilicon word line 42 operating as the signal input / output line R _A1 may be thinned to be used as a fuse.
That is, a large current is applied to the signal line from the large-capacity destruction capacitor 3 storing the electric charge, and the thinned portion of the polysilicon wiring is scattered by thermal melting. Thus,
It is to break the fuse portion provided in the middle of the signal output line R _A1, can also be destroyed the reading circuit of ROM boot circuit.

In the above embodiment, an IC card is used as an example of a semiconductor device. However, when the present invention is applied to a device other than an IC card, for example, an IC card is installed in a computer.
When arranging the chips, it goes without saying that the electrode bases 32 and 32a become printed wiring boards.

In the above embodiment, the number of the power supply source connection electrode pads 10, 63, 64 and the number of connection leads 28 are the same for the positive electrode and the negative electrode. However, the present invention is not limited to this. By providing connection leads and electrode pads, the number of positive electrodes and negative electrodes may be changed.

[0093]

According to the present invention, a power supply source and a semiconductor integrated circuit are connected by a plurality of pairs of connection leads for a positive electrode and a negative electrode and a connection terminal. Therefore, if any one of these connections is disconnected, the voltage change is detected by any of the plurality of voltage change detection circuits. In addition, since the back surface of the semiconductor integrated circuit is optically shielded by the power supply source, optical observation of the back surface can be avoided. In particular, for backside observation, it is necessary to remove the power supply used for shielding from the semiconductor integrated circuit, but if a third party who intends to tamper with the semiconductor integrated circuit attempts to remove the power supply, In addition, the destruction circuit operates reliably, and the falsification of the memory content of the semiconductor integrated circuit due to partial destruction of the memory information or disconnection of some signal wiring can be reliably prevented.

In addition, the semiconductor substrate (semiconductor integrated circuit) is flip-chip mounted on the electrode substrate such that the element surface of the semiconductor substrate faces the electrode substrate. Not only on the back of the circuit,
The element surface of the semiconductor integrated circuit can also be optically shielded. Moreover, since the power supply source is provided with connection leads at ends in a plurality of directions including at least both end portions facing each other,
The connection leads are connected to power supply source connection terminals arranged in a plurality of directions including at least both ends of the semiconductor substrate. This makes it difficult to expose the back surface of the semiconductor integrated circuit without disconnecting the power supply source,
Observation of the back surface of the semiconductor integrated circuit can be reliably prevented.

Further, the semiconductor substrate (semiconductor integrated circuit) is flip-chip mounted on the electrode substrate such that the element surface of the semiconductor substrate and the electrode substrate face each other. Not only on the back of the circuit,
The element surface of the semiconductor integrated circuit can also be optically shielded. Moreover, since the power supply source is provided with connection leads at ends in a plurality of directions including at least both end portions facing each other,
The connection leads are connected to power supply connection terminals arranged in a plurality of directions including at least both ends of the electrode base.
This makes it difficult to expose the back surface of the semiconductor integrated circuit without disconnecting the power supply source, so that observation of the back surface of the semiconductor integrated circuit can be reliably prevented.
Further, since the power supply source is connected to the semiconductor substrate via the power supply source connection terminal of the electrode substrate, the self-destruction mechanism can be activated even if the power supply source or the electrode substrate is removed. Thus, security can be further improved.

[Brief description of the drawings]

FIG. 1 is a circuit block configuration diagram of a self-destructive semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a bottom view, a cross-sectional view, and a side view showing an example of an arrangement configuration of the self-destructive semiconductor device of FIG. 1;

FIG. 3 is a diagram illustrating a state of flip-chip mounting according to the first embodiment of the present invention.

FIGS. 4A and 4B are a bottom view and a cross-sectional view illustrating an arrangement configuration example of a self-destructive semiconductor device according to a second embodiment of the present invention; FIGS.

FIG. 5 is a diagram showing a state of flip-chip mounting according to a second embodiment of the present invention.

FIG. 6 is a circuit block diagram of a self-destructive semiconductor device according to a third embodiment of the present invention.

FIG. 7 is a circuit block diagram of a self-destructive semiconductor device according to a fourth embodiment of the present invention.

FIG. 8 is a circuit diagram illustrating a configuration example of a voltage change detection circuit according to a fifth embodiment of the present invention.

9A and 9B are a cross-sectional view and a plan view illustrating a configuration example of a control circuit or an element according to a sixth embodiment of the present invention.

FIG. 10 is an explanatory diagram illustrating a configuration example of a destruction circuit using an antifuse according to a seventh embodiment of the present invention.

FIG. 11 is an explanatory diagram showing a configuration example of an antifuse.

FIG. 12 is an explanatory diagram showing a configuration example of a general IC card.

FIG. 13 is a circuit block configuration diagram of a conventional self-destructive semiconductor device.

14A and 14B are a plan view and a cross-sectional view illustrating an example of an arrangement configuration of the self-destructive semiconductor device in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit, 2 ... Destruction circuit, 3 ... Destruction capacitor, 4a, 4b ... Control circuit or element, 5-1 to 5-2
n: voltage change detection circuit, 6a, 6b: power supply source, 7-
1-7-8: electrode pad for external connection, 8: voltage dividing circuit, 9
a, 9b: semiconductor substrate, 10: power supply source connection electrode pad, 11a: IC module, 12a, 12b: IC
Chip, 14 data memory, 15 peripheral circuit, 16 ...
Program memory, 17 central processing unit, 18 random access memory, 19 microprocessor for authentication, 20 adhesive film, 21 positive electrode current collector / terminal plate,
Reference numeral 22: positive electrode, 23: solid electrolyte, 24: negative electrode, 25: negative electrode current collector / terminal plate, 26: sealing material, 27: bump, 28
... Connection lead, 29, 29a. OR logic circuit, 30. Switch, 32, 32a .. Electrode base, 35-1 to 35-8.
... contact pattern, 38 ... mold resin, 61 ... anisotropic conductive adhesive resin, 62-1 to 62-8 ... external connection electrode pads, 63, 64 ... power supply source connection electrode pads.

Continuing on the front page (72) Katsuyuki Machida, Inventor 3-192-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo Japan Telegraph and Telephone Corporation (72) Inventor Takahisa Masayo 3-192-2, Nishi-Shinjuku, Shinjuku-ku, Tokyo F-term (reference) in Nippon Telegraph and Telephone Corporation 5F083 AD00 BS00 CR12 CR14 EP00 ER22 FR00 GA06 GA30 LA10 ZA13 ZA14 ZA20 ZA23 ZA29 ZA30

Claims (5)

[Claims] 1. A semiconductor device having a semiconductor integrated circuit in which a semiconductor memory element and a central processing element for processing data stored in the memory element are formed on the same semiconductor substrate, wherein connection leads for a positive electrode and a negative electrode are provided. A power supply source comprising a plurality of power supply circuits, and a destruction circuit for self-destruction by destroying at least a part of memory information of the semiconductor integrated circuit or disconnecting at least a part of signal wiring; A destruction capacitor for storing electric charge for self-destruction by the power supply source, and a plurality of power supply source connection terminals respectively provided for a positive electrode and a negative electrode of the power supply source for storing electric charge in the destruction capacitor A power supply source connection terminal pair is provided for each of the positive electrode and the negative electrode. A plurality of voltage change detection circuits that output detection signals in response to the power supply source and the destruction capacitor via a power supply connection terminal during normal operation; and a detection signal from at least one voltage change detection circuit. Is output, a control circuit or an element for disconnecting the connection and connecting the destruction capacitor and the destruction circuit is provided on the semiconductor substrate, and the back surface of the semiconductor integrated circuit is optically shielded. A self-destructive semiconductor device, wherein the power supply source is arranged behind the element surface of a semiconductor substrate on which a semiconductor integrated circuit is formed. 2. A semiconductor device having a semiconductor integrated circuit in which a semiconductor memory element and a central processing element for processing data stored in the memory element are formed on the same semiconductor substrate. A destruction circuit that self-destructs by destructing at least a part of the memory information of the semiconductor integrated circuit or disconnecting at least a part of the signal wiring, A destruction capacitor for storing electric charge for self-destruction by the power supply source, and a plurality of power supply source connection terminals respectively provided for a positive electrode and a negative electrode of the power supply source for storing electric charge in the destruction capacitor A voltage dividing circuit for dividing the voltage between the power supply source connection terminals, one for each of the positive electrode and the negative electrode; and a power supply for the positive electrode. A voltage between the terminals of the power supply connection terminal for the positive electrode and the output terminal of the voltage divider circuit, or a power supply source for the negative electrode, provided for each of the power supply connection terminals and provided for each of the negative power supply connection terminals. A plurality of voltage change detection circuits that monitor the voltage between the connection terminal and the output terminal of the voltage divider circuit and output a detection signal in response to the voltage drop, and a power supply connection terminal during normal operation. When a detection signal is output from at least one voltage change detection circuit, a control circuit or an element that connects the destruction capacitor and the destruction capacitor is disconnected when at least one voltage change detection circuit outputs a detection signal. Having the respective power supply sources on the semiconductor substrate, and disposing the power supply source behind the element surface of the semiconductor substrate on which the semiconductor integrated circuit is formed so that the back surface of the semiconductor integrated circuit is optically shielded. Special Self-destructive type semiconductor device according to. 3. A connection device for a positive electrode and a negative electrode in a semiconductor device having a semiconductor integrated circuit in which a semiconductor memory element and a central processing element for processing data stored in the memory element are formed on the same semiconductor substrate. A power supply source comprising a plurality of power supply circuits, and a destruction circuit for self-destruction by destroying at least a part of memory information of the semiconductor integrated circuit or disconnecting at least a part of signal wiring; A destruction capacitor for storing electric charge for self-destruction by the power supply source, and a plurality of power supply source connection terminals respectively provided for a positive electrode and a negative electrode of the power supply source for storing electric charge in the destruction capacitor A voltage dividing circuit for dividing the voltage between the power supply source connection terminals, one for each of the positive electrode and the negative electrode, and a voltage dividing circuit. The power supply source connection terminal for the positive electrode, which is not provided, is provided for each power supply source connection terminal for the negative electrode, and the voltage divider circuit is provided for each terminal for the power supply source connection for the negative electrode, which is not connected. A plurality of voltage changes that monitor the voltage between the output terminals of the voltage circuit or the voltage between the terminal for connecting the power supply source for the negative electrode and the output terminal of the voltage divider circuit and output a detection signal in response to the voltage drop A detection circuit, connecting a power supply source and a destruction capacitor via a power supply connection terminal during normal operation, and disconnecting the connection when a detection signal is output from at least one voltage change detection circuit; And a control circuit or an element for connecting the destruction capacitor and the destruction circuit on the semiconductor substrate, wherein the semiconductor integrated circuit is formed such that the back surface of the semiconductor integrated circuit is optically shielded. Self-destroying semiconductor device, characterized by disposing the power supply on the back side of the element surface of the plate. 4. The self-destructive semiconductor device according to claim 1, further comprising an electrode base on which an external connection terminal is formed and on which the semiconductor substrate is mounted, wherein the power supply source comprises: The connection lead is provided at an end in a plurality of directions including at least both opposing ends, and the connection lead is formed on the element surface side of the semiconductor substrate so as to rotate around the end of the semiconductor substrate. And connecting the external connection terminal formed on the element surface side of the semiconductor substrate and the external connection terminal of the electrode substrate such that the element surface of the semiconductor substrate and the electrode substrate face each other. Self-destructive semiconductor device. 5. The self-destructive semiconductor device according to claim 1, wherein an external connection terminal and a plurality of power supply source connection terminals each for a positive electrode and a negative electrode are formed. An external connection terminal formed on the element surface side of the semiconductor substrate and an external connection terminal of the electrode substrate such that the element surface of the semiconductor substrate and the electrode substrate face each other. In addition, the power supply source connection terminal formed on the element surface side of the semiconductor substrate and the power supply source connection terminal of the electrode substrate are connected, and the power supply source includes a plurality of directions including at least opposite ends. A self-destructive semiconductor device, wherein the connection lead is connected to a power supply connection terminal of the electrode substrate.