JP2000021894A - Bipolar transistor and method of manufacturing the same - Google Patents

Abstract

[PROBLEMS] To improve the device characteristics of a thin film bipolar transistor using a thin polycrystalline silicon layer as an active layer. A p-type base layer is formed with high precision by self-alignment by using first and second spacer layers as part of a mask when forming a p-type base layer by ion implantation. I do. Also,
By removing the pn junction formed by the p-type base layer 24 and the n-type emitter layer 25 in the contact region where the base electrode is provided, an invalid current not contributing to the operation of the bipolar transistor is generated between the emitter and the base. To prevent flowing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bipolar transistor formed on a polycrystalline silicon layer or an SOI layer and a method for manufacturing the same, and more particularly, to a bipolar transistor formed with high precision by self-alignment and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the development of element miniaturization technology, the trend of integration of various circuits and integration of systems on one chip has become clear. Under such circumstances, integration of different types of circuits such as high-voltage elements, power elements, analog circuits and digital circuits is required.

On the other hand, in order to reduce the cost of transistors, which are basic elements of integrated circuits, there is a trend to use polycrystalline silicon instead of expensive single crystal silicon. Thus, for example, an attempt has been made to form a control circuit for a vertical high-voltage element by using an element made of polycrystalline silicon to form a single chip.

[0004] However, if it is attempted to form them simultaneously with a vertical element, there is a problem that the process becomes complicated. For this reason, it is conceivable to produce a bipolar transistor at the same time as a TFT (Thin Film Transistor). In this case, however, it is necessary to make the bipolar transistor horizontal because the thickness of the TFT is thin.

By the way, when doping a device made of polycrystalline silicon, there is a problem that when a diffusion method is used, abnormal diffusion occurs along a crystal grain boundary. For this reason, each layer of the bipolar transistor is manufactured not by diffusion but by selective ion implantation and heat treatment at a low temperature.

FIG. 21 is a manufacturing process diagram of this type of bipolar transistor. That is, as shown in FIG. 21A, an amorphous silicon film 2 is deposited on an insulating layer 1 on a substrate surface (not shown), and heat-treated at 600 ° C. for 8 hours.
The amorphous silicon film 2 is polycrystallized. Subsequently, FIG.
As shown in (b) to (c), an insulating layer 4 is formed on the high-resistance n-type active layer 3 made of the polycrystalline silicon film,
A mask 5 made of a resist or the like is selectively formed on the insulating layer 4, and a p-type base layer 6 is formed in the n-type active layer 3 by ion implantation or the like.

Similarly, an n-type collector layer 7 is formed in n-type active layer 3. Subsequently, FIGS. 21 (d) to 21 (e)
As shown in FIG. 5, a mask 8 is formed on the insulating layer 4 and is ion-implanted or the like to form an n-type emitter layer 9 having a high impurity concentration.
And an n-type collector layer 10 is formed. Further, a p-type base layer 11 having a high impurity concentration is formed on the surface of the p-type base layer 6, an emitter electrode 12, a base electrode 13, and a collector electrode 14 are formed, thereby completing a bipolar transistor.

[0008]

[SUMMARY OF THE INVENTION However, the bipolar transistors described above, since the length of affecting the base thickness t _B of the characteristic fluctuates depending on the deviation of mask alignment, the variation device characteristics, the base There is a problem that the thickness t _B cannot be shortened.

According to the study of the present inventor, in the case of this type of lateral element, a pn junction between the n-type emitter layer 9 and the p-type base layer 6 which does not contribute to the operation of the bipolar transistor occurs depending on the element structure. Since an ineffective current flows through the pn junction, it has been found that the amplification factor of the element is reduced.

The present invention has been made in view of the above-mentioned circumstances. Even when a thin polycrystalline silicon layer is used as an active layer, the base thickness t _B can be reduced and the operation of the bipolar transistor flowing between the emitter and the base can be improved. An object of the present invention is to provide a thin film bipolar transistor that can suppress an ineffective current that does not contribute.

[0011]

Means for Solving the Problems [Structure] In order to achieve the above object, a bipolar transistor according to the present invention comprises:
An active layer having a high resistance and a first conductivity type formed on the insulating layer;
A second conductive type base layer formed on the active layer, a first conductive type collector layer formed on the active layer and forming a pn junction with the base layer, and the collector layer formed on the active layer. An emitter layer of a first conductivity type formed in a different region and forming a pn junction with the base layer; and a collector layer or the collector layer formed on the collector layer or on the collector layer and the base. And the base is provided with an insulated spacer layer, and a separation layer is provided between the contact region where the base electrode of the base layer is provided and the emitter layer to separate them from each other. No pn junction is formed on the emitter layer side.

A more specific configuration of the present invention is as follows. (1) The base layer, the collector layer, the emitter layer, and the contact layer are formed so as to penetrate the active layer and reach the insulating layer. (2) The active layer is a polycrystalline silicon layer. (3) The spacer layer is a first spacer layer made of silicon nitride or polycrystalline silicon formed on the collector layer, or a nitride layer formed on the first spacer layer and the base layer and on the side wall of the first spacer layer. And a second spacer layer made of silicon or polycrystalline silicon.

[0013] The method of manufacturing a bipolar transistor according to the present invention includes a step of forming a spacer layer insulated from the collector layer on an active layer of the first conductivity type formed on the insulating layer; A second conductivity type impurity is ion-implanted into the active layer using one side of the spacer layer as a mask, and a second conductive type impurity is present below the one side of the spacer layer.
Forming a conductive type base layer, and ion-implanting a first conductive type impurity into the base layer using the spacer layer as a mask so that the base layer formed under one side of the spacer layer remains. Forming a first conductivity type emitter layer in the base layer; and forming a separation layer between the contact region of the base layer where the base electrode is provided and the emitter layer by separating the emitter layer from the contact region. Forming a pn junction on the emitter layer side so as not to be formed. According to the action present invention, by forming a self-aligned base layer with a spacer layer, even when a thin-film polycrystalline silicon layer as an active layer, a highly accurate base layer of the base thickness t _B Since it can be formed, excellent element characteristics can be realized.

Further, according to the present invention, among the base layers,
Since the contact region where the base electrode is provided does not form a pn junction with the emitter layer, it is possible to prevent an invalid current not contributing to the operation of the bipolar transistor from flowing between the emitter and the base. As a result, it is possible to prevent a decrease in the amplification factor of the element.

[0015]

Embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a plan view of a thin film bipolar transistor according to a first embodiment of the present invention, FIG. 2 is a sectional view taken along the line AA 'of FIG. 2, and FIG. View B-
FIG. 4 is a cross-sectional view taken along the line CC ′ in the plan view of FIG. 1, and FIG. 1 shows the arrangement of the n-type layer and the p-type layer on the surface of the active layer, and FIG. Only one spacer layer and the second spacer layer on its side wall are shown.

In the figure, reference numeral 21 denotes a silicon substrate.
On this silicon substrate 21, a thickness of 100 nm to 500 n
A silicon oxide film 22 having a thickness of about m is formed, and a high-resistance n-type active layer 23 made of polycrystalline silicon having a thickness of about 100 nm to 500 nm is formed thereon.

Since the figure shows the n-type active layer 23 on which each layer is formed, the n-type active layer 23 before the element is formed is shown.
Is not shown.

When a high breakdown voltage element or an element having a large potential difference with respect to the silicon substrate 21 is formed in the n-type active layer 23, the silicon oxide film 22 is preferably thicker. For example, when forming a high withstand voltage element of 500 V, the thickness of the silicon oxide film 22 is desirably about 3 μm.

The n-type active layer 23 has a p-type base layer 24, a high impurity concentration n-type emitter layer 25, and a high impurity concentration first layer.
A high impurity concentration p-type contact layer 27 for contacting the n-type collector layer 26 and the p-type base layer 24 with the electrode is formed, and a region sandwiched between the p-type base layer 24 and the first n-type collector layer 26 is The second n-type collector layer 28 is formed.

The region between the p-type contact layer 27 and the n-type emitter layer 25 is a p-type layer (p-type base layer which does not contribute to the operation of the bipolar transistor) 29. A portion where a pn junction is formed between the emitter layers 25 is removed by etching.

However, the p-type layer 29 is not always necessary. In this case, the p-type contact layer 27 and the n-emitter layer 2
The portion where a pn junction between 5 is formed is removed by etching.

A first spacer layer 31 made of polycrystalline silicon is formed on the second n-type collector layer 28 via a thin silicon oxide film 30, and a second spacer made of silicon nitride is formed on a side wall of the first spacer layer 31. A layer 32 is formed.

The p-type base layer 24 corresponds to a region just below the second spacer layer 32 on the side closer to the n-type emitter layer 25. An oxide film 33 is formed on the upper surface of the first spacer layer 31, and an insulating film 34 is further formed on the whole.

Then, three openings are formed in the insulating film 34, and the n-type emitter layer 25,
First n-type collector layer 26 and p-type contact layer 27
, An emitter electrode 35, a collector electrode 36, and a base electrode 37 are formed respectively.

Although the present embodiment is an example in which a polycrystalline silicon layer formed on a silicon substrate is used as an active layer, it can be used for another type of substrate, for example, an SOI substrate.

The first spacer layer 31 may be made of a silicon oxide film or silicon nitride instead of polycrystalline silicon. For the second spacer layer 32, polycrystalline silicon, a silicon oxide film, or the like can be used instead of silicon nitride.

FIGS. 5 (a) to 5 (e) and FIGS. 6 (a) to 6 (a) to 6 (c) show a method of manufacturing the thin film bipolar transistor of the present embodiment.
This will be described with reference to FIG. The sectional views of FIGS. 5A to 5E correspond to the sectional views taken along lines AA ′ and BB ′ of FIG. 1 in common, and FIGS. Is arrow B in FIG.
This corresponds to a cross-sectional view taken along line -B '. FIG. 7 is a plan view of a resist pattern used in the manufacturing process.

First, as shown in FIG. 5A, a silicon oxide film 22 having a thickness of about 100 to 500 nm is formed on a silicon substrate 21 by thermal oxidation. This may be formed by CVD. Specific crystalline silicon is deposited thereon by LPCVD to a thickness of about 100 nm to 500 nm. This is subjected to solid-phase growth by annealing at, for example, 600 ° C. for 8 hours to obtain polycrystalline silicon. An n-type impurity, for example, phosphorus is ion-implanted on the entire surface to make it n-type (the n-type impurity is activated by an after-mentioned heating step to become the n-type active layer 23).
The ion implantation may be performed before the solid phase growth. Alternatively, an n-type impurity such as phosphorus or arsenic may be doped simultaneously with the deposition of amorphous silicon.

Next, as shown in FIG.
After forming a silicon oxide film 30 having a thickness of about
A polycrystalline silicon film serving as the spacer layer 31 is deposited by a method such as LPCVD. Since the first spacer layer 31 serves as a mask in later silicon RIE, it is desirable that the polycrystalline silicon film be as thick as possible. Next, 10 nm is formed on the surface of the polycrystalline silicon film by thermal oxidation or CVD.
An oxide film 33 having a thickness of about 100 nm is formed. Then, using a resist mask of the form shown at 40 in FIG.
As shown in FIG. 3B, the polycrystalline silicon film is patterned by RIE to form a first spacer layer 31.

The first spacer layer 31 may be formed using a silicon oxide film, silicon nitride, or the like instead of the polycrystalline silicon film. In FIG. 7, those indicated by broken lines around the resist pattern 40 correspond to the subsequent steps (FIG. 5).
(Corresponding to (d)).

Next, as shown in FIG.
8 (attached to the outside of 41 in FIG. 7) and the first spacer layer 31 (and the oxide film 33 thereon) are used as masks, and a p-type impurity such as boron (B) is ion-implanted to a predetermined concentration. A mold base layer 24 is formed.

Next, as shown in FIG. 5D, a second spacer layer 32 is formed on the side wall of the first spacer layer 31. This step is carried out by depositing a silicon nitride film over the entire surface by LPCVD and then performing RIE under conditions that make it almost just etching, so that etching residue is left on the side surfaces of the first spacer layer 31. The thickness of the second spacer layer 32 can be adjusted with high precision by the thickness of the deposited silicon nitride film. Note that the second spacer layer 32 may use a film of polycrystalline silicon or the like instead of silicon nitride.

The region corresponding to the p-type contact layer 27 is protected by a resist (not shown) (not shown outside the hatched region 42 in FIG. 7), and arsenic (As) or phosphorus (as shown in FIG. 5E). An n-type impurity such as P) is ion-implanted at a high concentration to form an n-type emitter layer 25 and a first n-type collector layer 2.
6 is formed.

At this time, the first spacer layer 31 and the second spacer
Since the spacer layer 32 serves as a mask, the second spacer layer 3
The p-type base layer 24 whose thickness is controlled by the thickness of 2 is formed.

That is, the first spacer layer 31 and the second
The p-type base layer 24 can be formed by self-alignment using the spacer layer 32. Therefore, the thickness (lateral dimension) of the p-type base layer 24 can be adjusted with high precision by the thickness of the silicon nitride film deposited when the second spacer layer 32 is formed. Element characteristics can be realized.

Further, a p-type impurity such as boron is ion-implanted into the hatched region 43 of FIG. 7 at a high concentration using a resist mask to form a p-type contact layer 27. After this,
A heat treatment is performed to activate the impurities.

First spacer layer 31 and second spacer layer 32
The region between the p-type base layer 24 and the first n-type collector layer 26 below becomes the second n-type collector layer 28. Therefore, the horizontal length of the first spacer layer 31 determines the horizontal length of the second n-type collector layer 28. The length of the first spacer layer 31 is adjusted according to the required element withstand voltage. Further, the p-type contact layer 27 and the n-type emitter layer 2
The region sandwiched by 5 is a p-type layer 29.

Next, as shown in FIG. 6A, a resist (mask) 39 is formed in a region 44 indicated by sand hatching in FIG.
To form As shown in FIG. 7, the resist 39 has an outer periphery corresponding to the element region and an opening 45 provided therein. The opening 45 is, in a plan view seen from above,
The pn junction between the p-type layer 29 and the n-type emitter layer 25 is completely contained therein.

Using the resist 39, the first spacer layer 31, and the second spacer layer 32 as a mask, as shown in FIG. 6B, the silicon oxide film 30 and the polycrystalline silicon active layer are etched by RIE. The pn junction generated between the p-type layer 29 and the n-type emitter layer 25 is removed in this step. At the same time, element isolation by the groove is performed.

In this step, the first spacer layer 31, the oxide film 33 and the second spacer layer 32 serve as a mask to protect the underlying p-type base layer 24 and the second n-type collector layer 28. Therefore, it is desirable to set the etching selectivity between the polycrystalline silicon layer, which is the active layer, and the first spacer layer 31 and the second spacer layer 32 to be large.

Further, the silicon oxide film 30 is made thin, and the first
It is desirable that the spacer layer 31 and the oxide film 33 be thick. In particular, when the first spacer layer 31 or the second spacer layer 32 is formed of polycrystalline silicon, the first spacer layer 31 and the oxide film 33 are made thicker. Even if the active layer made of polycrystalline silicon below opening 45 is completely removed in this manner, first spacer layer 31 and second spacer layer 3
2 is left partially.

Next, as shown in FIG. 6C, the insulating film 34
After forming a contact opening in the insulating film 34, as shown in FIG.
An unillustrated emitter electrode 35 and base electrode 37 are formed.

According to the manufacturing method described above, the thickness of the p-type base layer 24 can be accurately reduced, and the p-type contact layer 27 (or the p-type layer 29) and the n-type
A thin-film bipolar transistor having no pn junction between the mold emitter layers 25 is formed.

If this pn junction exists, an invalid current which does not contribute to the operation of the bipolar transistor flows between the emitter and the base, which causes a reduction in the amplification factor of the element. In the present embodiment, such a pn junction is completely removed to obtain a thin film bipolar transistor having good characteristics.

FIG. 8 is a plan view showing a first modification of the present embodiment. FIG. 7 is a plan view of a thin-film bipolar transistor according to a second embodiment in which the planar structure of the element is partially modified.

In order to avoid complication, the arrangement of the n-type layer and the p-type layer on the surface of the active layer and the first
Only the spacer layer and the second spacer layer on its side wall are shown. The cross section taken along the line AA ′ and the cross section taken along the line BB ′ of the element of this modified example are the same as those shown in FIGS. 2 and 3, respectively.

In this modification, a first spacer layer 31 is provided in the element region so as to surround the n-type emitter layer 25 and the p-type contact layer 27, and a first n-type collector layer 26 is provided therearound.
Are formed. Further, a second spacer layer 32 is formed on a side wall of the first spacer layer 31.

The manufacturing method is the same as that of the present embodiment, and the thin p-type base layer 24 is formed with high accuracy.
Moreover, there is no pn junction between the p-type contact layer 27 and the n-type emitter layer 25 through which an ineffective current flows, and the current amplification factor is improved.

FIGS. 9 to 12 are plan views showing second to fifth modifications of the present embodiment. Also in these figures, the arrangement of the n-type layer and the p-type layer on the surface of the active layer and only the first spacer layer and the second spacer layer on the side wall thereof are shown. The cross-section taken along the line AA 'and the cross-section taken along the line BB' of the elements of these modified examples are the same as those shown in FIGS. 2 and 3, respectively.

Since the resistance of the p-type base layer 24 makes it difficult to function in a portion far from the p-type contact layer 27, as a countermeasure, in the modification of FIGS. The contact layer 27 is provided, and in the modification of FIGS. 10 and 12, the n-type emitter layer 25 is divided into two and formed on both sides of the p-type contact layer 27. Similarly, more n-type emitter layers 2 are provided in a portion surrounded by or sandwiched by the first spacer layer 31.
5 and the p-type contact layer 27 may be formed alternately. (Second Embodiment) FIG. 13 is a plan view of a thin film bipolar transistor according to a second embodiment of the present invention, FIG. 14 is a cross-sectional view taken along the line DD ′ of the plan view, and FIG. 13 is a sectional view taken along line EE ′ of FIG.
A cross-sectional view corresponding to the -C 'cross-sectional view is the same as FIG. In order to avoid complication, FIG. 13 shows only the arrangement of the n-type layer and the p-type layer on the surface of the active layer and only the first spacer layer.

This embodiment differs from the first embodiment in that the second spacer layer is not provided. Further, as a result of the absence of the second spacer layer, the method of forming the p-type base layer 24 is different from that of the first embodiment.

Next, FIGS. 16A to 16D and FIG.
The manufacturing method will be described with reference to (a) to (d). The sectional views of FIGS. 16 (a) to 16 (d) commonly correspond to the sectional views taken along the lines DD 'and EE' of FIG.
(A) to (d) correspond to a cross-sectional view taken along the line EE 'in FIG.

The steps up to the formation of the first spacer layer 31 (FIGS. 16A and 16B) are the same as in the first embodiment.

Next, as shown in FIG. 16C, the resist 38 and the first spacer layer 31 (and the oxide film 3 thereon) are formed.
Using p) as a mask, a p-type impurity such as boron is ion-implanted to a predetermined concentration to form a p-type base layer 24.

At this time, p-type impurities are implanted obliquely to the substrate surface, for example, at an angle of 30 ° to 60 °, to the depth of the edge of the first spacer layer 31. According to the acceleration voltage and the incident angle of this ion implantation, p
The thickness of the mold base layer 24 can be controlled.

This ion implantation is performed in two parts.
That is, after the substrate is fixed and ion implantation is performed so as to be below the edge of one first spacer layer 31, ion implantation is performed while changing the direction so as to be under the edge of the other first spacer layer 31. . Alternatively, the ion implantation may be performed while rotating the substrate around a rotation axis perpendicular to the substrate surface.

Next, as shown in FIG. 16D, an n-type impurity such as As or P is ion-implanted at a high concentration in the same manner as in the first embodiment to form an n-type emitter layer 25 and a first n-type collector layer. 26 is formed. Hereinafter, as shown in FIG. 17, an element is formed in the same process as in the first embodiment except that the second spacer layer is not provided.

Since the p-type base layer 24 is defined by the amount of ions obliquely implanted below the first spacer layer 31, the thickness (lateral length) is controlled by the ion implantation acceleration voltage and the incident angle. A thin p-type base layer can be realized. For example, when p-type impurities are ion-implanted at an angle of 60 ° with respect to the substrate surface, if the implantation depth is 100 nm, the thickness of the p-type base layer 24 is about 50 nm.

According to the manufacturing method described above, the thickness of the p-type base layer 24 can be accurately reduced, and the p-type contact layer 27 (or the p-type layer 29) and the n-type
A thin-film bipolar transistor having good characteristics and having no pn junction between the emitter layers 25 can be obtained.

In the step of FIG. 16C, a heat treatment is performed once after ion implantation of the p-type
The impurity in the p-type base layer 24 may be slightly diffused before the impurity in the n-type emitter layer by performing rapid annealing at 0 to 1000 ° C. for about 30 seconds.

The present invention is not limited to the above embodiment. For example, in each of the above embodiments, the element isolation is performed by the groove, but the element isolation may be performed by the LOCOS. FIGS. 18 to 20 show a thin-film bipolar transistor according to the first embodiment, in which elements are separated by LOCOS. In the figure, reference numeral 46 denotes an element isolation oxide film formed by LOCOS. 18 to 20 correspond to FIGS. 1 to 3, respectively.

In each of the above embodiments, the case where the first conductivity type is n-type and the second conductivity type is p-type has been described. However, the present invention is not limited to this. To p
Even if the second conductivity type is the n-type and the second conductivity type is the n-type, the same effect can be obtained by implementing the present invention in the same manner.

In each of the above embodiments, each layer is formed so as to penetrate the active layer and reach the insulating layer thereunder.
It may be formed on the surface of the active layer so as not to reach the insulating layer.

Further, a pn junction may remain on the contact region side of the base layer with respect to the separation layer provided for separating the collector region and the emitter layer of the base layer from each other. In this case, the remaining n-layer (remaining portion of the emitter layer) exists only in isolation, and the effect on the device operation can be ignored.

In addition, the present invention can be variously modified and implemented without departing from the gist thereof.

[0066]

As described above in detail, according to the present invention, by forming the base layer by self-alignment using the spacer layer, even when a thin polycrystalline silicon layer is used as the active layer, the thickness accuracy can be improved. Since a high base layer can be formed, excellent element characteristics can be realized.

According to the present invention, among the base layers,
Since the contact region where the base electrode is provided does not form a pn junction with the emitter layer, it is possible to prevent an ineffective current not contributing to the operation of the bipolar transistor from flowing between the emitter and the base, thereby preventing a reduction in amplification factor. Become like

[Brief description of the drawings]

FIG. 1 is a plan view of a thin film bipolar transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line A-A ′ of the plan view.

FIG. 3 is a cross-sectional view taken along the line B-B 'in the plan view.

FIG. 4 is a sectional view taken along the line C-C ′ in the plan view.

FIG. 5 is a process sectional view illustrating the method for manufacturing the thin-film bipolar transistor according to the first embodiment of the present invention.

FIG. 6 is a process sectional view illustrating the method of manufacturing the thin-film bipolar transistor following FIG. 5;

FIG. 7 is a view showing a shape of a resist pattern used in a manufacturing process of the thin film bipolar transistor.

FIG. 8 is a plan view showing a first modification of the bipolar transistor.

FIG. 9 is a plan view showing a second modification of the bipolar transistor.

FIG. 10 is a plan view showing a third modification of the bipolar transistor.

FIG. 11 is a plan view showing a fourth modification of the bipolar transistor.

FIG. 12 is a plan view showing a fifth modification of the bipolar transistor.

FIG. 13 is a plan view of a thin film bipolar transistor according to a second embodiment of the present invention.

FIG. 14 is a sectional view taken along the line D-D ′ in the plan view.

FIG. 15 is a sectional view taken along the line E-E ′ of the plan view.

FIG. 16 is a process cross-sectional view showing the method for manufacturing the thin-film bipolar transistor according to the second embodiment of the present invention.

FIG. 17 is a process sectional view illustrating the method of manufacturing the thin-film bipolar transistor following FIG. 16;

FIG. 18 is a plan view of a thin film bipolar transistor in which element isolation is performed by LOCOS in the first embodiment.

FIG. 19 is a sectional view of the thin bipolar transistor taken along line FF ′.

FIG. 20 is a sectional view of the thin film bipolar transistor taken along line GG ′.

FIG. 21 is a process cross-sectional view showing a conventional method for manufacturing a thin film bipolar transistor.

[Explanation of symbols]

Reference Signs List 21 silicon substrate 22 silicon oxide film 23 n-type active layer 24 p-type base layer 25 n-type emitter layer 26 n-type collector layer 27 p-type contact layer 28 n-type collector layer 29 p-type layer Reference Signs List 30 silicon oxide film 31 first spacer layer 32 second spacer layer 33 oxide film 34 insulating film 35 emitter electrode 36 collector electrode 37 base electrodes 38 and 39 resist 40 for forming first spacer Resist pattern 41: A resist pattern for forming a p-type base layer 42: A resist pattern for forming an n-type emitter layer and a first n-type collector layer 43: A resist pattern for forming a p-type contact layer 44: A resist for forming an element isolation region Pattern 45: Opening 46: Element isolation insulating film

Claims (5)

[Claims] A first conductive type active layer formed on an insulating layer; a second conductive type base layer formed on the active layer; a base layer formed on the active layer; A collector layer of a first conductivity type forming a pn junction with the collector layer; an emitter layer of a first conductivity type formed in a region different from the collector layer in the active layer to form a pn junction with the base layer; And a spacer layer formed on the collector layer and the base and insulated from the collector layer or the collector layer and the base, wherein a base electrode of the base layer is provided. A separation layer is provided between the contact region and the emitter layer, and a pn junction is not formed on the emitter layer side by the separation layer. Register. 2. The device according to claim 1, wherein the base layer, the collector layer, the emitter layer, and the contact region are formed so as to penetrate the active layer and reach the insulating layer. Bipolar transistor. 3. The bipolar transistor according to claim 1, wherein said active layer is a polycrystalline silicon layer. 4. The spacer layer is a first spacer layer made of silicon nitride or polycrystalline silicon formed on the collector layer, or a side wall of the first spacer layer and the base layer and of the first spacer layer. 2. The bipolar transistor according to claim 1, comprising a second spacer layer made of silicon nitride or polycrystalline silicon formed in the portion. 5. A step of forming a spacer layer insulated from the collector layer on an active layer of the first conductivity type formed on the insulating layer, and using one side of the spacer layer as a mask. Ion-implanting an impurity into the active layer to form a base layer of the second conductivity type, a part of which is present below the one side of the spacer layer; Ion-implanting an impurity into the base layer, and forming a first conductivity type emitter layer in the base layer so that the base layer formed under one side of the spacer layer remains; Forming a separation layer between the contact region where the base electrode of the base layer is provided and the emitter layer so that a pn junction is not formed on the emitter layer side of the separation layer. To Method of manufacturing a bipolar transistor to be butterflies.