JP2000020332A - Parity generation method - Google Patents

Abstract

(57) [Summary] [Problem] To prevent a bit error from disappearing at a stage of dividing into a plurality of parities and converting to a single original parity again. Kind Code: A1 When data having a 1-bit parity with respect to a certain data length is divided into a plurality of data and a 1-bit parity is generated for each data, the first parity is converted to the last one. Until the previous parity, odd parity of the data part is generated, and the final parity is
This is achieved by generating an exclusive OR of the data portion excluding the last part and one parity before division.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for generating a parity of each data when the data is divided into a plurality of data.

[0002]

2. Description of the Related Art In the field of scientific and technical calculations, generally, a data string of 8 bits and a parity of the data is added, and a bit string composed of a total of 9 bits is handled in one unit.
When the bit string of one unit shifts to the left or right or the length of data changes due to arithmetic processing,
Parity must be corrected taking this into account. Here, in order to simplify parity correction, there is a method of dividing data into a certain length and adding a parity bit to each of the divided data.

In the process of dividing data having a 1-bit parity for a certain data length into a plurality of data and generating a 1-bit parity for each data,
It is necessary that bit errors propagate correctly.

Referring to FIG. 3, a method of generating two parities by dividing two data according to the prior art will be described below.

There are the following data strings and parity bits for the data strings. Data strings: a (0), a (1), a (2),..., A (k), a (k + 1), a (k +
2),..., A (n-1), a (n) Parity: P However, parity is assumed to be odd parity.

The first half of the data is a (0), a (1), a
(2),..., A (k)
When the data is divided into 2),..., A (n), the method of generating the parity bit of each data is as follows.

Parity of first half data: Ph = a (k + 1) xor a (k + 2) xor ...
xor a (n-1) xor a (n) xor P Parity of second half data: Pl = a (0) xor a (1) xor a (2) x
or ... xor a (k) xorP Here, xor indicates exclusive OR. The conversion of the parity bits (Ph and Pl) of each of the divided data into the parity bits (P) before the division is performed as follows.
Is realized by inverting the exclusive OR of

Parity before division: P = not (Ph xor Pl) Here, not indicates bit inversion.

[0009]

In the parity generation method according to the above prior art, when a bit error occurs in the data before division, an error occurs in both parity bits (Ph and Pl) of each divided data. When the signal propagates and is converted again into one parity bit, bit errors cancel each other out and disappear.

An object of the present invention is to provide a parity generation method in which a bit error does not disappear even if the parity is divided into a plurality of parities and converted into one parity again.

[0011]

When data having a 1-bit parity for a certain data length is divided into a plurality of data and a 1-bit parity is generated for each data, a first bit is generated. From the parity to the last previous parity, odd parity of the data part is generated, and the final parity is generated by exclusive OR of the data part excluding the last part and one parity before division. Is achieved by

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a method of generating parity bits of each data when data division is performed in the same manner as described above will be described below.

Parity of first half data: Ph = not (a (0) xor a (1) xor a
(2) xor ... xor a (k)) Parity of second half data: Pl = a (0) xor a (1) xor a (2) x
or ... xor a (k) xor P In other words, the parity of the first half data simply generates an odd parity using the first half data as it is, and the parity of the second half data is exclusive of the first half data and one parity before division. Is generated by logical disjunction.

According to this method, the parity bit in which the bit error propagates is only the parity of the second half data,
Even if it is converted into one parity bit again, there is no possibility that the bit error disappears.

A specific example of parity generation will be described below.

Data: 10100111 Parity: 1 There is an 8-bit data portion having a 1-bit error and a bit string composed of 1 bit parity of the data portion. When this data width is divided into two by a 4-bit width to generate respective parities, first, in the prior art, the parity of the first four bits: Ph = (0 xor 1 xor 1 xor 1)
xor 1 = 0 Parity of the latter 4 bits: Pl = (1 xor 0 xor 1 xor 0)
xor 1 = 1 and the byte parity restored again is not (0 xor
1) = 0, and the bit error disappears.

Next, in the generation method of the present invention, the parity of the first four bits: Ph = not (1 xor 0 xor 1 xor
0) = 1 Parity of the last 4 bits: Pl = (1 xor 0 xor 1 xor 0)
xor 1 = 1 and the byte parity restored again is not (1 xor
1) = 1 and the bit error does not disappear.

The above-mentioned example of the byte parity returned to the original state is as follows. When the bit position has not changed or the shift is performed in units of 8 bits, the shift is performed in units of 4 bits. The original byte parity changes.

In the prior art method, since one parity error moves to the data portion in the shifting direction, the bit errors do not cancel each other out.

In the method of the present invention, when shifting right,
One parity error moves to the data portion in the right-shifted direction, and at the time of left shift, remains in the data portion as it is, so that the bit error does not disappear. Therefore, when shifting is performed in units of 4 bits, there is no problem in both the prior art and the generation method of the present invention.

The above case is based on two data divisions.
FIG. 2 shows a case where the number of parities is generated. Next, a case where the data is divided into a plurality of parities and then converted into one parity again is shown. From the first parity P (1) to the last previous parity P (m-1), an odd parity is simply generated as it is, and only the final parity P (m) is added to the data portion excluding the last part. It is generated by exclusive OR of one parity before division. This means that a bit error propagates only to the last part as in the case of two data divisions,
There is no danger that the bit error will disappear.

In the field of scientific computing, a floating-point data format is used as a data representation method. The format of floating-point data used in commercial large-scale computers generally includes a 1-bit sign part, a 7-bit exponent part, and a 3/7 / 14-byte mantissa part depending on expression precision. The exponent is represented by a power of 16.

The floating-point addition / subtraction instruction executes pre-scale and post-normalization in the course of the operation. Prescale is to digitize the mantissa of the operand with the lower exponent to the right by the number of digits of the exponent difference (4 bits)
In the shift and post-normalization, digit shift is performed to the left by the number of digits of consecutive digit zeros from the upper part of the intermediate sum. When the amount of the shift operation is an even digit, there is no particular problem even with byte (8-bit) parity, but in the case of an odd digit, one digit is shifted before and after the shift operation. To take this into account,
The replacement is performed from the parity bit unit to the digit unit. Here, if the digit parity is generated by the method of the present invention, it is possible to return to the correct byte parity.

[0024]

When a plurality of parity bits are divided by the method of the present invention, bit errors do not disappear in the process of returning to the original one parity bit.

[Brief description of the drawings]

FIG. 1 is a diagram showing two parity generation / conversion circuits of the present invention.

FIG. 2 is a diagram showing a plurality of parity generation / conversion circuits of the present invention.

FIG. 3 is a diagram showing a conventional two parity generation / conversion circuits.

[Explanation of symbols]

1. Exclusive OR circuit, 2. Exclusive OR circuit, 3. NOT gate.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Makoto Takiguchi 1 Horiyamashita, Hadano-shi, Kanagawa Prefecture Inside Nichi Information Technology Co., Ltd. (72) Inventor Yoshimasa Kashihara 1-ori Horiyamashita, Hadano-shi, Kanagawa Prefecture Nichi Information Technology Co., Ltd. (72) Inventor Chiaki Takahashi 1 Horiyamashita, Hadano-shi, Kanagawa F-term in Hitachi Information Technology Co., Ltd. 5B001 AA01 AB03 AC01

Claims (1)

[Claims] 1. When data having a 1-bit parity for a certain data length is divided into a plurality of data and a 1-bit parity is generated for each data, a bit error is accurately propagated. A parity generation method characterized by being performed.