JP2000019201A - Source voltage detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the circuit scale preventable from being enlarged and becom ing complicate by connecting a variable resistance adjustment means and a detection voltage selection means in series between power sources and connecting a waveform-shaping means to a connection point of the variable resistance adjustment means and the detection voltage selection means. SOLUTION: When an L, H control signal 124 is inputted to a gate of a PMOS 121, a detection voltage selection means 12 is selected, or not selected respectively and an L, H output is generated from a waveform-shaping circuit 13 depending on which of a source voltage and a detection voltage is larger. When a control signal 125 is H and an NMOS 123 is on, the PMOS 121 is turned off by the H control signal 124. Detection resistors Rx-Rz do not divide a voltage between the ground and a power source, impressing a signal which is L to a source voltage VSS to a gate of an NMOS 122 and turning off the NMOS, whereby a resistance of the NMOS is infinitely large. The H control signal 2 is impressed to the NMOS 123 to turn on the NMOS to invalidate the resistor Rz. At this time, if the L control signal 124 is input, the PMOS 121 is turned on and the NMOS 122 becomes a resistance body dependent on the source voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply voltage detecting circuit for detecting a change in a power supply voltage in a timepiece IC using a power generating element represented by a solar cell as a power supply.

[0002]

2. Description of the Related Art In a conventional example, as a means for informing a user of a voltage state of a power supply voltage, there is a method of detecting a power supply voltage state of a battery or the like by a power supply voltage detection circuit and displaying the state on an external display element or the like. FIG. 2 is a block diagram showing a configuration of a conventional power supply voltage detection circuit.

The conventional power supply voltage detection circuit shown in FIG.
This is a configuration for detecting a voltage change of one power supply. The conventional power supply voltage detection circuit includes a variable resistance adjustment unit 31, a detection voltage selection unit 32, a waveform shaping unit 33, and a variable resistance control signal output unit 34. .

The internal structure of the variable resistance means 31 constituting the power supply voltage detection circuit of the conventional example shown in FIG. 2 is composed of a reference resistance R0, n adjustment resistances R1 to Rn, and n P-type field effect transistors (hereinafter referred to as PMOS). 311 to 31n).

The internal structure of the detection voltage selection means 32 constituting the power supply voltage detection circuit of the prior art shown in FIG. 3 is composed of a first detection voltage resistance Rx, a second detection voltage resistance Ry, and a PMOS 32.
1 and an N-type field effect transistor (hereinafter referred to as NMOS) 322.

The internal configuration of the variable resistance control signal output means 34 constituting the power supply voltage detection circuit of the conventional example shown in FIG.
And a decode circuit having m input terminals and n control signal output terminals O1 to On. At this time, m and n are positive integers and the relationship between m and n is n
= 2m. The variable resistance adjusting means 31 includes a reference resistance R0
And n adjustment resistors R1 to Rn are connected in series, and the reference resistor R0 is connected after the adjustment resistor Rn. A PMOS3 that connects the source terminal to the ground voltage and the gate terminal to the control signals 1 to n is connected to one terminal on the release side of the adjustment resistor R1 and the connection point where the adjustment resistors R1 to Rn are connected in series.
Drain terminals 11 to 31n are connected.

The detection voltage selection means 32 is a PMOS3
21 is connected to the ground voltage,
Is connected to one terminal of a first detection voltage resistor Rx, and the other terminal of the first detection resistor Rx is connected to one terminal and a source terminal of a second detection voltage resistor Ry to a power supply voltage. Connected to the gate terminal of the NMOS 322,
The other terminal of the detection voltage resistor Ry is connected to the power supply voltage.

The gate terminal of the PMOS 221 is connected to the selection control signal, and the other terminal of the reference resistor R 0 constituting the variable resistance adjusting means 31 is connected to the drain terminal of the NMOS 322 constituting the detection voltage selecting means 32 and the waveform shaping circuit 33. Connected to input terminal.

The variable resistance control signal output means 34 connects an external input terminal to an input terminal of a decode circuit 341,
Output terminals O1 to On of the decode circuit 341 are connected to gate terminals of PMOSs 311 to 31n constituting the variable resistance adjusting means 31.

Next, the operation of the conventional power supply voltage detecting circuit shown in FIG. 2 will be described. In the conventional power supply voltage detection circuit, the PMOS 321 constituting the detection voltage selection means 32 is turned on by a selection control signal, and the voltage between the ground and the power supply is divided by the first detection resistor Rx and the second detection resistor Ry. The divided voltage is applied to the gate terminal of the NMOS 322.

The PMOS constituting the variable resistance means 31
311 to 31n are control signals 1 to 3 at their gate terminals.
n is selectively turned on by inputting n.
n is selectively connected to a ground voltage. Thus, the variable resistance means 31 can change the resistance value by connecting the variable resistances R1 to Rn and the reference resistance R0 in series.

The NMOS 322 utilizes the characteristic that the on-resistance of the NMOS 322 increases when the voltage applied to the gate terminal decreases, so that the output of the waveform shaping circuit 2 is inverted when the power supply voltage reaches a desired detection voltage. PMO
The control signals 1 to n input to the respective gate terminals of S311 to S31n are set.

A decoding circuit 341 constituting the variable resistance control signal output means 34 receives a setting signal from an external input terminal, decodes the setting signal, and outputs the result to the output signals of the decoding circuit output terminals O1 to On. Set.

Since the power supply voltage detection circuit is formed on a semiconductor substrate, the detection voltage varies due to variations in the manufacture of the semiconductor device. However, the accuracy of the detection voltage can be improved by adjusting the variable resistance means 31. it can.

[0015]

However, in the configuration of the detection voltage selection means of the conventional power supply voltage detection circuit, after the resistance value of the variable resistance adjustment means is fixed, the detection voltage is similarly fixed at one value. Therefore, in order to detect a plurality of voltages, it is necessary to prepare a detection circuit having a configuration of the related art, and there is a problem described below that the circuit scale becomes large.

The power consumption of a logic gate is consumed every time an input signal of the logic gate is switched, and increases in proportion to the number of logic gates.

When a plurality of conventional power supply voltage detection circuits are integrated in a semiconductor integrated circuit, the circuit scale increases, the chip area of the semiconductor integrated circuit increases, the number of semiconductor integrated circuits per wafer decreases, and the yield decreases. Causes a decline.

An object of the present invention is to solve the above-mentioned problems and to provide a power supply voltage detection circuit for detecting a plurality of voltages without increasing the circuit scale and the circuit complexity.

Further, it is an object of the present invention to provide a power supply voltage detecting circuit which does not cause a large chip area even when integrated on a semiconductor integrated circuit, reduces the number of semiconductor integrated circuits per wafer, and does not reduce the yield. It is.

[0020]

The configuration of the power supply voltage detection circuit is such that a variable resistance adjustment means and a detection voltage selection means are connected in series between power supplies, and a waveform is provided at a connection point between the variable resistance adjustment means and the detection voltage selection means. The shaping means is connected, and the variable resistance adjusting means connects at least one resistor having one end connected to the drain of the PMOS in series between the power supply VDD and the power supply voltage selecting means, and connects the PMOS source to VDD. , The control signal is input to the gate, the voltage selection means connects the source to VDD, the PMOS having the gate input the voltage selection signal, the drain is connected to the variable resistance adjustment means, and the source is the power supply VS.
An NMOS connected to S, a resistor having one end connected to the NMOS gate and the other end connected to the drain of the PMOS,
An NMO having one end connected to the gate of the NMOS, a source connected to VSS between the other end and VSS, a second voltage selection signal input to the gate, and a drain connected to one end of the resistor
It is characterized in that S is constituted by at least one or more resistors connected in series.

In the detection voltage selection means, a resistor and an NMO
By connecting S in parallel and short-circuiting the NMOS to VSS by a control signal, the resistance value of the resistor can be nullified.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A power supply wherein variable resistance adjusting means and detection voltage selecting means are connected in series between power supplies, and a waveform shaping means is connected to a connection point between the variable resistance adjusting means and detection voltage selecting means. It is a voltage detection circuit.

[0023]

FIG. 1 is a block diagram showing a configuration of a power supply voltage circuit according to the present invention. First, the circuit configuration of the power supply voltage detection circuit will be described with reference to FIG.

The power supply voltage detection circuit of the present invention shown in FIG.
The power supply voltage detection circuit according to the present invention includes a variable resistance adjustment unit 11, a detection voltage selection unit 12, a waveform shaping unit 13, and a variable resistance control signal output unit 14. .

The internal structure of the variable resistor means 11 constituting the power supply voltage detecting circuit of the present invention shown in FIG. 1 is composed of a reference resistor R0, n adjusting resistors R1 to Rn, and n P-type field effect transistors (hereinafter referred to as PMOS transistors). 111-11n).

The internal configuration of the detection voltage selection means 12 constituting the power supply voltage detection circuit of the present invention shown in FIG. 1 includes a first detection voltage resistor Rx, a second detection voltage resistor Ry, and a third detection voltage resistor Rz. , PMOS 121, N-type field effect transistor (hereinafter referred to as NMOS) 122, and second NMOS
It consists of:

The internal configuration of the variable resistance control signal output means 14 constituting the power supply voltage detection circuit of the present invention shown in FIG.
And a decode circuit having m input terminals and n control signal output terminals O1 to On. At this time, m and n are positive integers and the relationship between m and n is n
= 2m. The variable resistance adjusting means 11 includes a reference resistance R0
And n adjustment resistors R1 to Rn are connected in series, and the reference resistor R0 is connected after the adjustment resistor Rn. A PMOS1 that connects the source terminal to the ground voltage and the gate terminal to the control signals 1 to n is connected to one terminal on the release side of the adjustment resistor R1 and the connection point where the adjustment resistors R1 to Rn are connected in series.
Drain terminals 11 to 11n are connected.

The detection voltage selection means 12 is a PMOS
21 is connected to the ground voltage and the PMOS 121
Is connected to one terminal of the first detection voltage resistor Rx, and the other terminal of the first detection resistor Rx is connected to one terminal and the source terminal of the second detection voltage resistor Ry to the power supply voltage. Connected to the gate terminal of the NMOS 122;
The other terminal of the detection voltage resistor Ry is connected to one terminal of the third detection voltage resistor Rz, the other terminal of the third detection voltage resistor Rz is connected to VSS, and the drain terminal of the second NMOS 123 is connected to The second detection voltage resistor Ry is connected to the connection point of the third detection voltage resistor, the source terminal of the second NMOS 123 is connected to VSS, and is connected to the power supply voltage.

The gate terminal of the PMOS 121 is connected to the first selection control signal 124, the gate terminal of the second NMOS 123 is connected to the second selection control signal 125, and the reference resistance R0 constituting the variable resistance adjusting means 11 is connected. Is connected to a first NMOS 12 which constitutes the detection voltage selection means 12.
2 and the input terminal of the waveform shaping circuit 13.

The variable resistance control signal output means 14 connects an external input terminal to an input terminal of the decode circuit 141,
Output terminals O1 to On of the decode circuit 141 are connected to gate terminals of PMOSs 111 to 11n constituting the variable resistance adjusting means 11.

Next, the operation of the power supply voltage detecting circuit of the present invention shown in FIG. 1 will be described. First, the detection voltage selection means 12
Is low and the second control signal 125
The case where the MOS 123 is insulated will be described.

First, the operation of the variable resistance adjusting means 11 will be described. PMOS 111 constituting variable resistance means 11
11n are selectively turned on by inputting control signals 1 to n from their external input terminals to their respective gate terminals, thereby setting the resistance value of the adjustment resistor to 0. Therefore, the resistance value of one adjustment resistor is r, the resistance value of R2 is 2r, and the resistance value of R3 is 4r.
Assuming that the resistance value of R4 is 8r, the combined resistance between R1 and Rn is a variable resistance in r steps from r to n * r depending on the combination.

As described above, the variable resistance means 11 can change the resistance value by connecting the selectable adjustment resistors R1 to Rn and the reference resistor R0 in series.

Now, assume that the resistance values of the adjustment resistors R1 to Rn constituting the variable resistance means 11 are r, the resistance value of the reference resistor R0 is r0, and the selection signal 1 input to the external input terminal is
To n, i.sub.k signal level is "low", other signal levels are "high", and the resistance value of the variable resistance means 11 is rd. The resistance value rd is rd = r0 + k * r.
At this time, k is a natural number satisfying 1 <= k <= n.

Next, the operation of the detection voltage selection means 12 shown in FIG. 1 will be described. When the selection control signal 123 of “high” is applied to the gate terminal of the PMOS 121 constituting the detection voltage selection means 11, the PMOS 121 is turned “off”.

Then, the first detection resistor Rx, the second detection resistor Ry, and the third detection resistor Rz do not divide the voltage between the ground and the power supply, and supply a "low" signal with respect to the power supply voltage VSS, that is, the ground. Apply to the gate of the NMOS 122 and set the NMOS 1
22 turns "off", and the on resistance of the NMOS 122 becomes an infinite resistance value.

On the contrary, when the selection control signal 123 of “low” is applied to the gate terminal of the PMOS 121,
Is turned on, the first detection resistor Rx and the second detection resistor Rx are turned on.
y, the third detection resistor Rz divides the voltage between the ground and the power supply, and applies the divided voltage to the gate of the NMOS 122. At this time, the NMOS 122 becomes a resistor that depends on the power supply voltage according to the characteristics of the N-type transistor.

FIG. 3 is a diagram showing the relationship between the power supply voltage and the divided voltage of the power supply voltage detection circuit of the present invention. As shown in FIG. 3, a first detection resistor Rx and a second detection resistor R, which are constant resistors,
Since the division ratio by y and the third detection resistor Rz is constant, when the power supply voltage becomes higher than the arbitrary detection voltage Vd1, the potential difference between the divided voltage and the power supply voltage becomes larger.

On the other hand, when the power supply voltage becomes smaller than the detection voltage, the voltage difference between the divided voltage and the power supply voltage becomes smaller. This indicates that the on-resistance of the NMOS 122 decreases as the power supply voltage increases according to the characteristics of the N-type transistor, and the on-resistance increases as the power supply voltage decreases.

Next, the first waveform shaping means 13 shown in FIG.
Will be described. The first waveform shaping means 13 is a buffer, which outputs "high" when receiving a "high" side input signal at the boundary of a half of the power supply voltage which is a threshold, and conversely, outputs a "low" side input signal. Outputs "low" when receiving.

Next, the operation of the entire power supply voltage detecting circuit according to the embodiment of the present invention will be described. FIG. 4 is a diagram showing the operation timing of the power supply voltage detection circuit of the present invention. A signal is input to the external input terminals PAD1 to PADn constituting the variable resistance means 11 to make the variable resistance means 11 a constant resistance having a resistance value rd.

Next, P constituting the detection voltage selection means 12
A selection control signal as shown in FIG. 4 is applied to the gate terminal of the MOS 121.

The selection control signal shown in FIG. 4 selects the detection voltage selection means 12 when it is "low", and deselects it when it is "high". Accordingly, as shown by the detection signal in FIG. 4, the power supply voltage is detected during the selection period, and when the power supply voltage is higher than the detection voltage, the waveform background board 13 outputs "low", and when the power supply voltage is lower than the detection voltage, the waveform shaping is performed. The circuit 13 outputs "high".

Next, when the second control signal 125 constituting the detection voltage selection means 12 is "high" and the second NMOS 123
Voltage detecting means 12 shown in FIG.
Will be described. When the selection control signal 123 of “high” is applied to the gate terminal of the PMOS 121 constituting the detection voltage selection means 11, the PMOS 121 is turned “off”.

Then, the first detection resistor Rx, the second detection resistor Ry, and the third detection resistor Rz do not divide the voltage between the ground and the power supply, and supply a low voltage signal to the power supply voltage VSS, that is, the ground. Apply to the gate of the NMOS 122 and set the NMOS 1
22 turns "off", and the on resistance of the NMOS 122 becomes an infinite resistance value.

The second NMOS 123 is turned on because the "high" level of the second control signal 2 is applied to the second NMOS 123, and the second detection resistor Ry and the third detection resistor Rz are electrically connected between the source and the drain. Becomes the power supply level, and the third detection resistor Rz is invalidated.

At this time, the gate terminal of the PMOS
When the first selection control signal 124 of “low” is applied, the PMO
S121 is turned “ON”, and the first detection resistor Rx and the second detection resistor Ry divide the voltage between the ground and the power supply, and apply the divided voltage to the gate of the NMOS 122. At this time, the second NMOS 122 becomes a resistor that depends on the power supply voltage according to the characteristics of the N-type transistor.

FIG. 5 is a diagram showing the relationship between the power supply voltage and the divided voltage of the power supply voltage detection circuit of the present invention. As shown in FIG. 5, a first detection resistor Rx and a second detection resistor R which are constant resistors are provided.
Since the second division ratio 2 based on y is constant, when the power supply voltage becomes larger than the second arbitrary detection voltage Vd2, the potential difference between the divided voltage and the power supply voltage becomes larger.

Conversely, when the power supply voltage is lower than the second detection voltage Vd2, the voltage difference between the divided voltage and the power supply voltage becomes smaller. This indicates that the on-resistance of the NMOS 122 decreases as the power supply voltage increases according to the characteristics of the N-type transistor, and the on-resistance increases as the power supply voltage decreases.

When the second NMOS 123 conducts, the slope of the second division ratio 2 is such that the resistance value of the third detection resistor Rz is invalidated, and the first detection resistor Rx and the second detection resistor Ry are invalidated.
Since the division is performed only by the power source, the division ratio changes and the power supply side tilts. Therefore, the potential difference between the divided voltage and the power supply voltage at an arbitrary power supply voltage is smaller than when the second NMOS 123 is off. Accordingly, the second detection voltage Vd2 is a power supply voltage that is equal to the potential difference between the divided voltage and the reduced voltage when the detection voltage is Vd1, so that the potential difference between the divided voltage and the reduced voltage is increased, that is, the power supply voltage is increased. The direction becomes larger.

In the above-described embodiment of the present invention, the detection voltage of the power supply voltage is adjusted by changing the ratio of the detection resistors constituting the detection voltage selection means 12, but the channel width or the channel length of the NMOS 122 is adjusted. It is clear that the detection voltage can be adjusted in any way.

[0052]

As is apparent from the above description, according to the power supply voltage detection circuit of the present invention, the resistor and the NMOS are connected in parallel in the detection voltage selection means, the gate signal of the NMOS is controlled, and the resistance is directly controlled. By invalidating the resistance value of the body, a plurality of voltages can be detected, and a circuit corresponding to the number of detected voltages is not required, so that the circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a power supply voltage detection circuit according to the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional power supply voltage detection circuit.

FIG. 3 is a diagram illustrating a relationship between a power supply voltage and a divided voltage of a power supply voltage detection circuit according to an embodiment of the present invention.

FIG. 4 is a diagram showing operation timings of the power supply voltage detection circuit in the embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Variable resistance means 111 P-type field-effect transistor 112 P-type field-effect transistor 113 P-type field-effect transistor 114 P-type field-effect transistor 12 Detection voltage selection means 121 P-type field-effect transistor 122 N-type field-effect type Transistor 13 Waveform shaping means Rx First detection voltage resistance Ry Second detection voltage resistance

Claims (3)

[Claims] 1. A power supply voltage detection method comprising: connecting a variable resistance adjustment means and a detection voltage selection means in series between power supplies; and connecting a waveform shaping means to a connection point between the variable resistance adjustment means and the detection voltage selection means. circuit. 2. The variable resistance adjusting means connects at least one resistor having one end connected to a drain of a PMOS in series between VDD and a power supply voltage selecting means, connects the PMOS source to VDD, and connects a gate to the PMOS source. The power supply voltage detection circuit according to claim 1, wherein a control signal is input to the power supply voltage detection circuit. 3. The detecting voltage selecting means sets the source to VDD.
Connected to the gate and a voltage selection signal input to the gate
And the drain connected to the variable resistance adjusting means, and the source connected to V
An NMOS connected to SS, a resistor having one end connected to the NMOS gate and the other end connected to the drain of the PMOS, and one end connected to the gate of the NMOS and the other end connected to VSS, and a source connected to VSS. NM with a second voltage selection signal input to the gate and a drain connected to one end of the resistor
2. The power supply voltage detection circuit according to claim 1, wherein the OS is constituted by at least one resistor connected in series.