JP2000013001A - Manufacture of printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve insulating reliability between circuits, and to prevent the lack of a conductor circuit and circuit precision by removing the chemical plating of a part except for a part becoming a circuit and burying an unnecessary chemical plating catalyst left on the surface of a substrate in the surface of the insulating substrate. SOLUTION: A chemical plating catalyst 4 is applied to the surface of the insulating resin layer 3 of an insulating substrate 1, chemical plating is executed on the whole face of the insulating substrate 1 and a chemical plating layer 5 is formed. Plating resist 6 is applied on a part which does not become a circuit, the chemical plating layer 5 is conducted and the electric plating layer 7 of copper is formed on a part becoming the circuit by an electrolytic plating method. Then, plating resist 6 is removed, the exposed chemical plating layer 5 is dissolved/removed by etching and a conductor circuit 8 is obtained. The chemical plating catalyst 4 left between the conductor circuits 8 on the surface is buried in the insulating resin layer 3. Thus, the exposure of the chemical plating catalyst on the surface of the insulating substrate can be reduced and insulating reliability between the circuits is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board used for electronic circuits and the like.

[0002]

2. Description of the Related Art A printed wiring board used for an electronic device or the like is formed by laminating a conductive pattern such as a copper foil on one or both sides of a plate-shaped insulating layer. 2. Description of the Related Art In recent years, with the demand for miniaturization and high performance of electronic devices, it has been desired that printed wiring boards used therein have higher density and thinner.

As a method of manufacturing a multilayer printed wiring board corresponding to high density, a semi-additive method can be cited. The following procedure is shown as an example of the semi-additive method. An insulating resin layer is formed on the entire surface of the substrate by coating or the like. After applying a chemical plating catalyst to the entire surface of the insulating resin layer, chemical copper plating is performed to form a thin copper plating layer. After forming a plating resist on the part that does not become a circuit,
A copper plating layer is further laminated on a portion of the chemical copper plating layer to which electrolytic plating is performed and no plating resist is applied. The plating resist is removed. A thin chemical copper plating layer that has not been electrolytically plated with a resist is dissolved and removed with an etchant, and a conductive circuit is formed leaving a thick electrolytically plated copper layer. The semi-additive method has a feature that a fine circuit can be formed with high accuracy because the copper layer to be etched is thin.

[0004]

However, in the method of manufacturing a printed wiring board using the above-described semi-additive method, the exposed chemical copper plating layer is dissolved and removed by etching, and then the exposed surface of the insulating resin layer is chemically removed. There is a problem that the plating catalyst remains. Since the remaining chemical plating catalyst causes remarkable deterioration of the insulation reliability between the conductor circuits formed due to the conductivity of the chemical plating catalyst itself, a method of etching and removing the remaining chemical plating catalyst together with the insulating resin has been proposed. (Japanese Unexamined Patent Publication No.
167694, JP-A-8-8513).
However, in this method, when the conductive circuit is fine, if the etching amount of the insulating resin becomes excessive, the insulating resin below the conductive circuit is dissolved and removed, and the conductive circuit falls off. It was very difficult. This is shown in FIG. In FIG. 2A, reference numeral 1 denotes an insulating substrate in which an insulating resin layer 3 is formed on a substrate 2 formed of a laminated plate or the like. Chemical plating is performed by applying a chemical plating catalyst 4 on the insulating resin layer 3 to form a chemical plating layer 5. Electroplating is further performed on the chemical plating layer 5 to form an electrolytic plating layer 7. The conductor circuit 8 is formed by combining the chemical plating layer 5 and the electrolytic plating layer 7 after etching unnecessary portions. In the state shown in FIG. 2A, the insulating resin layer 3 below the conductor circuit 8 is removed, and the conductor circuit 8 is in an unstable state.
The conductor circuit 8 may fall off from the insulating substrate 1.

Further, a method of removing the remaining chemical plating catalyst by etching with an acidic solution (JP-A-61-55989)
Japanese Patent Application Publication No. 4-19719), however, a new problem arises in that the conductor circuit is dissolved at the same time as the etching of the chemical plating catalyst, and the circuit accuracy deteriorates. That is, the state is as shown in FIG. The reference numerals in FIG. 2B are the same as those in FIG. In the state shown in this figure, a part of the conductor circuit 8 is dissolved and removed, which causes a disconnection or the like and adversely affects the circuit accuracy.

The present invention has been made in view of the above points, and provides a method of manufacturing a printed wiring board which is excellent in insulation reliability between circuits and does not cause dropout of a conductor circuit and deterioration of circuit accuracy. The purpose is to do so.

[0007]

According to a method of manufacturing a printed wiring board according to the present invention, a chemical plating is applied to the surface of an insulating substrate 1 and then a chemical plating is performed. A conductor circuit 8 is formed by further plating a part to be a circuit, then the plating resist 6 is removed, and after removing the chemical plating other than the part to be a circuit, the unnecessary chemical plating catalyst 4 remaining on the substrate surface is removed. Is buried in the surface of the insulating substrate 1.

According to a second aspect of the present invention, there is provided a method of manufacturing a printed wiring board, wherein an unnecessary chemical plating catalyst remaining on the surface of the insulating substrate is used.
Is buried in the surface of the insulating substrate 1 at least 50% of the total surface area.

According to a third aspect of the present invention, there is provided a method of manufacturing a printed wiring board, wherein an unnecessary chemical plating catalyst remaining on the surface of the insulating substrate is used.
Is buried in the surface of the insulating substrate 1 at least 50% of the total weight.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a printed wiring board, wherein an unnecessary chemical plating catalyst remaining on the surface of the insulating substrate is used.
Is embedded in the surface of the insulating substrate 1 by heat treatment.

According to a fifth aspect of the present invention, in the method of manufacturing a printed wiring board, the temperature used in the heat treatment is equal to or higher than the glass transition temperature of the resin forming the surface of the insulating substrate 1.

[0012]

Embodiments of the present invention will be described below.

As the insulating substrate 1, a substrate in which an insulating resin layer 3 is laminated on a surface of a substrate 2 formed of a laminated plate or the like can be used. A chemical plating catalyst 4 is applied to the surface of the insulating resin layer 3 of the insulating substrate 1 (FIG. 1A), and then the entire surface of the insulating substrate 1 is chemically plated to form a chemical plating layer 5 (FIG. 1B). ). The metal used for the chemical plating can be exemplified by copper or nickel, but copper is particularly common. In the insulating resin layer 3 used in this example, the chemical plating catalyst 4 remaining on the surface of the insulating substrate 1 is buried in the insulating resin layer 3 on the surface of the insulating substrate 1 in the heat treatment of the insulating substrate 1 after the removal of the chemical plating layer 5. It is necessary that the material be softened by heating. Therefore, as the resin forming the insulating resin layer 3, a thermoplastic resin or a thermosetting resin in a semi-cured state is used. For example, a semi-cured epoxy resin or a photocurable An epoxy resin or the like can be used. The method for forming the insulating resin layer 3 is not particularly limited, and a printing method, a curtain coating method, or the like can be applied. Further, the chemical plating catalyst 4 is not particularly limited as long as it is a substance such as copper or nickel which has a catalytic action in chemical plating, but a palladium-tin colloid can be mentioned as an example widely used.

Next, as shown in FIG. 1 (c), after a plating resist 6 is laminated on a portion that does not become a circuit, a current is applied to the chemical plating layer 5 and electrolytic plating such as copper is performed on a portion that becomes a circuit by an electrolytic plating method. Layer 7 is laminated on chemical plating layer 5. A metal layer for forming the conductor circuit 8 is formed by laminating the electrolytic plating layer 7 and the chemical plating layer 5. In this example, the chemical plating layer 5 is further plated to form a conductor circuit 8.
Although electroplating was used to form a metal layer for forming a metal layer, other plating methods may be used. As the plating resist 6, a dry film or a liquid resist can be used.

Next, the plating resist 6 is removed (FIG. 1).
After (d)), the exposed chemical plating layer 5 is dissolved and removed by etching (FIG. 1 (e)), and the conductor circuit 8 is obtained by leaving the electrolytically plated portion. The etchant used for the etching is not particularly limited, but a cupric chloride solution or an acidic solution of sodium persulfate can be used. The chemical plating catalyst 4 such as a palladium-tin colloid is hardly dissolved in this etching solution. Therefore, as shown in FIG. 1E, the palladium-tin colloid, which is the chemical plating catalyst 4, remains between the conductor circuits 8, and the insulation reliability is deteriorated.

Therefore, in the present invention, as shown in FIG. 1 (f), the chemical plating catalyst 4 remaining between the conductor circuits 8 on the surface is buried in the insulating resin layer 3. The remaining chemical plating catalyst 4
As a method of burying the insulating resin layer 3 in the insulating resin layer 3, a method of softening the insulating resin layer 3 by heat treatment and burying the insulating resin layer 3 is preferable because a complicated process is not required. The heating temperature during this heat treatment is preferably set to be equal to or higher than the glass transition temperature of the resin forming the insulating resin layer 3, and the chemical plating catalyst can be buried in the insulating resin layer in a short time. The upper limit of the heating temperature is not particularly limited, but is preferably about glass transition temperature + 20 ° C.

The amount of the chemical plating catalyst 4 buried in the insulating resin layer 3 is 5% of the total surface area of the chemical plating catalyst 4.
0% or more, or 50% of the total weight of the chemical plating catalyst 4
% Or more is preferable from the viewpoint of securing insulation reliability. Of course, it is ideal that 100% of the total surface area and 100% of the total weight of the chemical plating catalyst 4 are buried, and this is the upper limit.

[0018]

The present invention will be described below in detail with reference to examples. (Example 1) A thermosetting epoxy resin was applied to the surface of a substrate 2 formed of a copper-clad laminate by a curtain coating method,
It was cured at a temperature of 150 ° C. for 2 hours to provide a semi-cured insulating resin layer 3. At this time, when the glass transition point of the epoxy resin of the insulating resin layer 3 was measured using DSC, a value of 145 ° C. was obtained. Next, the surface of the insulating resin layer 3 was roughened with a permanganic acid solution in order to enhance the adhesion of the chemical plating. Next, a palladium tin colloid type chemical plating catalyst 4 was applied to the surface of the insulating resin layer 3 (FIG. 1).
(A)). Next, chemical plating was performed to form a chemical plating layer 5 on the surface of the insulating resin layer 3 (FIG. 1B). Thereafter, a photosensitive dry film, which is a plating resist 6, is laminated on the surface of the chemical plating layer 5, and is exposed and developed to leave the photosensitive dry film in a portion where a circuit is not formed. The volatile dry film was removed. Then, by electrolytic copper plating, thickness 2
After forming a 5 μm electrolytic plating layer 7 (FIG. 1C),
The photosensitive dry film was peeled off (FIG. 1 (d)). Next, the exposed chemical plating layer 5 was removed by etching with a cupric chloride etching solution to form a conductor circuit 8 (FIG. 1).
(E)). Further, heat treatment was performed at 130 ° C. for 30 minutes to obtain a printed wiring board as shown in FIG. (Example 2) Except that the heat treatment temperature was 150 ° C,
A printed wiring board was produced in the same manner as in Example 1. (Example 3) Except that the heat treatment temperature was 170 ° C,
A printed wiring board was produced in the same manner as in Example 1. (Comparative Example) Except that the heat treatment performed in Example 1 was not performed,
A printed wiring board was produced in the same manner as in Example 1.

Further, in order to evaluate the percentage of the chemical plating catalyst buried in the insulating substrate 3 in the heat treatments of Examples 1 to 3 and the comparative example, the immersion of the chemical plating catalyst 4 on the insulating substrate 3 was carried out. The surface area ratio and the burial weight ratio were measured.

First, in the same manner as in Example 1, as shown in FIG.
Was applied to the surface of the insulating resin layer 3. Then, each of Examples 1 to
An insulating substrate sample subjected to the heat treatment under the same conditions as in No. 3 and an insulating substrate sample not subjected to the heat treatment corresponding to the comparative example were prepared. The method of measuring the buried surface area ratio and the buried weight ratio is shown below. 1. Buried surface area ratio For each of the insulating substrate samples corresponding to the above Examples 1 to 3 and Comparative Example, a chemical copper plating treatment was performed for 15 seconds, and the weight of copper deposited on the surface of the insulating substrate was measured. The measurement of the weight was performed by immersing each of the insulating substrate samples after the chemical copper plating treatment in aqua regia to dissolve the precipitated copper, and quantifying the amount of copper in the aqua regia by ICP emission analysis. The weight of the copper deposited on the surface of the insulating substrate sample is proportional to the surface area of the plating catalyst remaining on the surface of the insulating substrate sample. The rate is 0%
It is. Therefore, assuming that the amount of copper deposition of the insulating substrate sample heat-treated under the conditions of Examples 1 to 3 is S _E , and the amount of copper deposition of the insulating substrate sample of the comparative example not heat-treated is Sc, the buried surface area ratio is It is represented by the following equation (1). Table 1 shows the results. 1. Buried surface area ratio (%) = {(Sc−S _E ) / Sc} × 100 (1) Buried weight ratio Unlike the previous section, each of the above insulating substrate samples was subjected to an X-ray microanalyzer (XM
According to A), quantitative analysis of palladium in the chemical plating catalyst remaining on the surface of each insulating substrate sample was performed. The analyzed area is a 1 cm × 1 cm portion on the insulating substrate.
The burial weight ratio of the substrate of each example was calculated by comparing the quantitative values. Surface residual amount W _E of palladium electroless plating catalyst of the insulating substrate samples heat treated under the conditions of Examples 1 to 3, the surface residual palladium in the chemical plating catalyst insulating substrate samples of Comparative Examples not subjected to heat treatment Wc the amount
Then, the burial weight ratio is represented by the following equation (2). Table 1 shows the results. Buried weight ratio (%) = {(Wc- W E) / Wc} × 100 (2) was then measured insulation resistance between the conductor circuit for the printed wiring board obtained in Examples 1 to 3 and Comparative Examples . The method is as follows. The conductor circuit is formed as a comb-shaped electrode pattern (circuit interval 150 μm, circuit width 75 μm)
The insulation resistance between the electrodes before and after the temperature cycle test was measured.

The temperature cycle test conditions were as follows: first at −65 ° C. for 15 minutes, then at room temperature for 5 minutes, then at 150 ° C. for 15 minutes, returned to room temperature for 5 minutes, and again at −65 ° C. for 15 minutes. Become. This was repeated for 300 cycles. Table 1 shows the results
Shown in

[0022]

[Table 1] In the resistance values shown in Table 1, the resistance values of the 0 cycle and the 300 cycle that do not change so much are those having good insulation reliability. In the comparative example, it was confirmed that the resistance value was greatly reduced as compared with the case of 0 cycle, and the insulation reliability was considerably inferior.

In Example 1 in which the heat treatment was performed at a temperature lower than the glass transition temperature of the epoxy resin forming the insulating resin layer on the surface of the insulating substrate, the amount of buried chemical plating catalyst was not sufficient. It becomes 1/100, which indicates that the insulation reliability is not very good. In Examples 2 and 3, since the heat treatment was performed at a temperature higher than the glass transition temperature of the epoxy resin forming the insulating resin layer on the insulating substrate surface, the buried amount of the chemical plating catalyst was sufficient, and the insulation reliability was improved. Was confirmed.

[0024]

As described above, in the method for manufacturing a printed wiring board according to the present invention, a chemical plating catalyst is applied to the surface of an insulating substrate to perform chemical plating. After forming a conductor circuit in the part that becomes the part, then removing the plating resist and removing the chemical plating other than the part that becomes the circuit, unnecessary chemical plating catalyst remaining on the substrate surface is buried in the insulating substrate surface, The exposure of the chemical plating catalyst on the surface of the insulating substrate can be reduced, and the insulation reliability between circuits can be increased. In addition, there is no need to remove the chemical plating catalyst by etching, and the conductor circuit falls off. In addition, it is possible to manufacture a printed wiring board that does not cause a decrease in circuit accuracy.

In the invention according to claim 2 of the present invention, 50% or more of the total surface area of the unnecessary chemical plating catalyst remaining on the surface of the insulating substrate is buried in the surface of the insulating substrate. It is possible to manufacture a highly secured printed wiring board.

In the invention according to claim 3 of the present invention, 50% or more of the total weight of the unnecessary chemical plating catalyst remaining on the surface of the insulating substrate is buried in the surface of the insulating substrate. It is possible to manufacture a highly secured printed wiring board.

In the invention according to claim 4 of the present invention, since the method of burying unnecessary chemical plating catalyst remaining on the surface of the insulating substrate on the surface of the insulating substrate is performed by heat treatment, a complicated process is not required, and Thus, it is possible to easily manufacture a printed wiring board having the above-mentioned insulation reliability.

In the invention according to claim 5 of the present invention, the temperature used in the heat treatment is equal to or higher than the glass transition temperature of the insulating material. It is possible to bury a chemical plating catalyst in the insulating substrate surface in a short time, and to more reliably manufacture a printed wiring board having excellent insulation reliability between circuits.

[Brief description of the drawings]

FIG. 1 shows an example of an embodiment of the present invention,
(A)-(f) is sectional drawing.

FIG. 2 shows a conventional example, and (a) and (b) are cross-sectional views.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Insulating substrate 4 Chemical plating catalyst 5 Chemical plating layer 6 Plating resist 8 Conductor circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Satoru Ogawa 1048 Kadoma Kadoma, Osaka Pref.Matsushita Electric Works, Ltd. (72) Inventor Shuji Maeda 1048 Kadoma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Works Co., Ltd. Matsushita Electric Works, Ltd., 1048, Kazuma, Kadoma, Osaka Prefecture (72) Inventor Shinya Nishimoto 1048, Kazuma, Kazuma, Kadoma, Osaka Pref. Address Matsushita Electric Works Co., Ltd. F-term (reference) 5E343 AA02 BB24 BB44 BB67 CC73 DD33 DD43 ER11 ER26 ER33 ER39 GG11 GG14

Claims (5)

[Claims] After a chemical plating catalyst is applied to the surface of an insulating substrate to perform chemical plating, a plating resist is applied to a portion other than a portion to be a circuit, and a portion to be a circuit is further plated to form a conductor circuit. After removing the resist and removing the chemical plating other than the part that will become the circuit,
A method for manufacturing a printed wiring board, comprising burying an unnecessary chemical plating catalyst remaining on a substrate surface on an insulating substrate surface. 2. The method according to claim 1, wherein at least 50% of the total surface area of the unnecessary chemical plating catalyst remaining on the surface of the insulating substrate is buried in the surface of the insulating substrate. 3. The method according to claim 1, wherein 50% or more of the total weight of the unnecessary chemical plating catalyst remaining on the surface of the insulating substrate is buried in the surface of the insulating substrate. 4. The method according to claim 1, wherein the unnecessary chemical plating catalyst remaining on the surface of the insulating substrate is buried in the surface of the insulating substrate by heat treatment. 5. The method according to claim 4, wherein a temperature used in the heat treatment is equal to or higher than a glass transition temperature of a resin forming a surface of the insulating substrate.