JP2000012789A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a well boundary, where a high breakdown voltage CMOSFET is formed, to be improved in breakdown voltage. SOLUTION: At least either of an N-type diffused layer 61 and a P-type diffused layer 74 which are formed at the same time with the offset source/drain diffused layers of a high breakdown voltage FET is formed apart from a boundary between an N-type well 2 and a P-type well 3 in a high-breakdown voltage CMOS semiconductor integrated circuit. With this setup, an electric field is restrained from concentrating on a well boundary, whereby a well boundary can be enhanced in the breakdown voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a semiconductor substrate on which a high breakdown voltage element is formed.

[0002]

2. Description of the Related Art Semiconductor devices (semiconductor integrated circuit devices) have been diversified in use as their integration and speed have increased. A CMOS transistor (hereinafter referred to as an FET) driven by a voltage used for a general logic circuit and a high voltage MOSF on the same semiconductor chip.
A large-scale semiconductor integrated circuit device in which an ET and a ET are juxtaposed has been put to practical use. For example, in a semiconductor device used for driving a liquid crystal, a high breakdown voltage MOSFET is used in a peripheral circuit connected to an output terminal from a semiconductor chip to the outside, and a low voltage operation integrated to control the high breakdown voltage MOSFET is provided in an area inside the semiconductor chip. A CMOSFET forming a high-level circuit is formed.

The structure of a high breakdown voltage CMOSFET forming region used in such a semiconductor device will be described with reference to FIG. Here, FIG. 5A shows a high breakdown voltage CMOSF.
FIG. 5B is a plan view showing a pattern layout of a portion where the ET is formed, and FIG. 5B is a cross-sectional view taken along a line AB shown in FIG. High breakdown voltage P channel MO on left half
SFET, N-channel MOS with high breakdown voltage on the right half
An FET is formed.

In FIG. 5, reference numeral 1 denotes a P-type silicon substrate, 2 denotes an N-type well formed on a P-type silicon substrate 1, 3 denotes a P-type well formed on a P-type silicon substrate 1, The surface of the P-type silicon substrate 1 has a so-called LOC
A thick LOCOS oxide film 8 also serving as element isolation is formed by the OS method.

In the P-channel MOSFET part,
Reference numeral 14 denotes a gate insulating film formed on the surface of the N-type well 2, and a gate electrode 15 is formed on the gate insulating film 14. The gate electrode 15 on the surface of the N-type well 2
A P-type drain diffusion layer 18 and a P-type source diffusion layer 19 are formed on both sides. Each of these diffusion layers 18 and 19 has a high impurity concentration. Reference numeral 7 denotes a P-type offset diffusion layer, and a current flows between a source and a drain through the P-type offset diffusion layer 7 in a high-breakdown-voltage P-channel MOSFET.

Also, a high breakdown voltage N-channel MOSFET
Has a similar structure. That is, 16 is an N-type drain diffusion layer, 17 is an N-type source diffusion layer, 6 is an N-type offset diffusion layer, and a current flows between the source and the drain through the N-type offset diffusion layer 6. .

An N-type guard band diffusion layer 4 is formed on the surface of the N-type well 2 so as to surround the periphery of the P-channel MOSFET, and a P-type guard band diffusion layer 5 is formed so as to surround the periphery of the N-channel MOSFET. The guard band diffusion layers 4 and 5 are formed on the surface of the mold well 3.
Are also electrodes for preventing latch-up in the CMOSFET region and for applying each well potential. Under the LOCOS oxide film 8, a diffusion layer 6 formed simultaneously using the process of the N-type offset diffusion layer 6 is formed.
There are diffusion layers 71, 72, 73 formed simultaneously using the steps of 1, 62, 63 and the P-type offset diffusion layer 7. Particularly, the diffusion layers 61 and 71 are formed at the boundary between both wells to form a junction. These diffusion layers 61 to 63 and 7
Channels 1 to 73 have a channel under the LOCOS oxide film 8 and have a leak between the source and drain of each MOSFET and MO.
It serves as a channel stop for preventing leakage between SFETs. Although not shown in FIG. 5, in the completed high breakdown voltage CMOSFET, an aluminum (AL) wiring connecting to the source, gate, drain and the like over the LOCOS oxide film 8 is arranged. Since a voltage of V is applied, the surface of the silicon substrate under the LOCOS oxide film 8 is very easily inverted without a channel stop, and a leak current flows. For these reasons, a channel stop is indispensable for a high breakdown voltage element.

[0008]

However, in a high breakdown voltage CMOSFET, several tens of volts to 100
It is normal to drive by applying a voltage of about V, and C
Depending on the circuit configuration using MOSFETs, almost the same high voltage is applied to the N-type guard band diffusion layer 4 or the P-type guard band diffusion layer 5 that gives a well potential.

In the well boundary structure of a conventional semiconductor device having a high breakdown voltage CMOSFET, when a high voltage is applied to either the N-type guard band diffusion layer 4 or the P-type guard band diffusion layer 5, the surface concentration is usually N-type well 2
1.5 × 10 ¹⁵ / cm ³ , P-type well 3 1.0 × 1
It is about 0 ¹⁵ / cm ³ , but the diffusion layer 61 bordering both wells has a high concentration of about 4.0 × 10 ¹⁶ / cm ³ and the diffusion layer 71 has a high concentration of 4.0 × 10 ¹⁶ / cm ^3. And the diffusion layer 6
The electric field is concentrated at the junction between the first layer and the diffusion layer 71 to form a high electric field portion, and the breakdown voltage between the wells 2 and 3 cannot be handled with sufficient margin in practical use. The impurity concentration of the diffusion layers 61 and 71 is necessary and cannot be reduced because the above-described channel leak is prevented. As described above, the conventional technique has a problem.

An object of the present invention is to improve the breakdown voltage of a well boundary where a high breakdown voltage CMOSFET is formed in such a semiconductor device.

[0011]

In a semiconductor device according to the present invention, at least a portion of a first conductivity type well and a portion of a second conductivity type well are formed on a surface of a first conductivity type substrate so as to be in contact with each other. The surface region of the one conductivity type well has a first diffusion layer having a higher impurity concentration than the first conductivity type well, and the surface region of the second conductivity type well has a higher impurity concentration than the second conductivity type well. A second diffusion layer having a concentration, wherein both the first diffusion layer and the second diffusion layer are formed without being in contact at the same portion of a boundary where the first conductivity type well and the second conductivity type well are in contact with each other. It is characterized by having.

According to the present invention, a high breakdown voltage CMOSFE
A semiconductor device having an improved withstand voltage at the well boundary where T is formed can be obtained.

[0013]

According to the first aspect of the present invention, at least a part of a first conductivity type well and a second conductivity type well are formed on a surface of a first conductivity type substrate,
The surface region of the first conductivity type well has a first diffusion layer having a higher impurity concentration than the first conductivity type well, and the surface region of the second conductivity type well has a higher concentration than the second conductivity type well. It has a second diffusion layer of high impurity concentration, without contacting both the first diffusion layer and the second diffusion layer at the same portion of the boundary where the first conductivity type well and the second conductivity type well contact It is characterized by being formed, the first conductivity type diffusion layer to be formed at the boundary between the first conductivity type well and the second conductivity type well, at least one of the second conductivity type diffusion layer, By providing a distance from the well boundary, at least one of the well boundaries has a low impurity concentration at least in the well itself, so that the electric field concentration at the well boundary when a high voltage is applied to the guard band diffusion layer is reduced. And withstand pressure It has the effect that above.

According to a second aspect of the present invention, in the first aspect, a high breakdown voltage element is formed in each of the first conductivity type well and the second conductivity type well. This has the effect that the inter-well breakdown voltage when a voltage is applied to the high breakdown voltage element is improved as compared with the conventional case.

The invention according to claim 3 is the invention according to claim 1 or claim 2, wherein the first diffusion layer has the same conductivity type as the first conductivity type well, and The diffusion layer is characterized by having the same conductivity type as the second conductivity type well, and has the function of serving as a channel stop.

According to a fourth aspect of the present invention, a second conductivity type well is formed on the surface of the first conductivity type substrate, and a high breakdown voltage element is formed on each of the first conductivity type substrate and the second conductivity type well.
In the surface region of the first conductivity type substrate, the first conductivity type substrate has a higher impurity concentration and has a first diffusion layer of the first conductivity type, the surface region of the second conductivity type well, the A second diffusion layer having a higher impurity concentration than the second conductivity type well and a second conductivity type, wherein both the first diffusion layer and the second diffusion layer are located at the same portion of a boundary of the second conductivity type well; It is characterized by being formed without contact with
Since both the first diffusion layer and the second diffusion layer are formed without contact at the same portion of the boundary of the second conductivity type well, one of both well boundaries has at least a low impurity concentration of the well itself. This has the effect of reducing the electric field concentration at the well boundary when a high voltage is applied to the high withstand voltage element, and improving the withstand voltage.

An embodiment of the present invention will be described below with reference to the drawings. The same components as those of the conventional example shown in FIG. 5 are denoted by the same reference numerals, and description thereof is omitted. FIG. 1 is a sectional structural view of a P-well / N-well boundary of a semiconductor device having a high breakdown voltage CMOSFET according to an embodiment of the present invention. This diagram corresponds to the well boundary portion including the diffusion layers 61 and 71 in FIG. Further, the structure of the portion other than the portion shown in FIG. 1 where the high breakdown voltage CMOSFET exists is the same as that of FIG.

In this embodiment, the concentration of the N-type well 2 formed on the P-type silicon substrate 1 is set to 1.5 × 10 ¹⁵ /
cm ³ and the concentration of the P-type well 3 are set to 1.0 × 10 ¹⁵ / cm ³ . Further, the concentration of each of the N-type guard band diffusion layer 4 and the P-type guard band diffusion layer 5 is set to 2.0 × 10 ²⁰ / c.
m ³ , 5.0 × 10 ¹⁹ / cm ³ . This concentration is
It is about the same as the source / drain of a high breakdown voltage CMOSFET not shown.

The LOCOS oxide film 8 for element isolation has a thickness of about 800 nm, and the region of the N-type well 2 and the P-type well 3 under the LOCOS oxide film 8 mainly serves as a channel stop. An N-type diffusion layer 61 of 0 × 10 ¹⁶ / cm ³ and a P-type diffusion layer 74 of about 4.0 × 10 ¹⁶ / cm ³ are also formed. These N-type diffusion layers 6
1 and the P-type diffusion layer 74 have a width in the horizontal direction of about 6 μm to 1 μm.
It is about 0 μm. Here, in the present embodiment, the P-type diffusion layer 74 is approximately 4 μm from the boundary region between the N well 2 and the P well 3.
One feature is that they are arranged m apart.

With this arrangement, the N-type diffusion layer 61 is in contact with the well boundary on the N-well 2 side at the N-well 2 side, so that the concentration is about 4.0 × 10 ¹⁶ / cm ^3. On the P well 3 side, the P well 3 itself, that is, a concentration of about 1.0 × 10 ¹⁵ / cm ³ can be obtained. Therefore, the arrangement in which the concentration is reduced as described above can greatly improve the breakdown voltage between wells. In fact, in the conventional configuration described above, the high breakdown voltage FE
The withstand voltage when a voltage is applied to the drain region of T is about 100
In contrast to V, the breakdown voltage between wells was as low as about 80 to 90 V, but was increased to about 160 V when the arrangement in this embodiment was adopted.

The N-type diffusion layer 61 and the P-type diffusion layer 74 need not be limited to the arrangement shown in FIG. Even if the diffusion layer 61 is separated from the well boundary by a few microns from the well boundary, the diffusion layer 74 is separated from the well boundary by the diffusion layer 74.
Reference numeral 4 is effective in improving the breakdown voltage since the impurity concentration on both sides or one side of the well boundary can be reduced even when the structure is kept in contact with the well boundary. The diffusion layer 6
Needless to say, it is desirable that the ends 74 are spaced over the entire well boundary portion where the ends thereof face each other.

Next, the high breakdown voltage CMOS of the present invention shown in FIG.
A method of manufacturing a semiconductor device having an FET, particularly a well boundary portion, will be described with reference to FIGS. First, as shown in FIG. 2A, the surface of the P-type silicon
A mold well 2 and a P-type well 3 are formed by ion implantation and heat treatment.

Next, as shown in FIG. 2B, a protective oxide film 9 is grown on the surfaces of the N-type well 2 and the P-type well 3,
Further, a silicon nitride film 10 is grown on the surface of the protective oxide film 9.

Next, as shown in FIG. 2C, a photoresist pattern 11 is formed to form a diffusion layer region in which a guard band is to be formed, and dry etching is performed using the photoresist pattern 11 as a mask. Then, a part of the silicon nitride film 10 is removed.

Next, as shown in FIG. 3A, ions are implanted so as to have a higher impurity concentration than the N-type well 2 using a photoresist pattern 12 formed so as to cover the region of the P-type well 3 as a mask. , An N-type diffusion layer 61 is formed. High voltage NMOSFE by ion implantation in this process
A T offset diffusion layer is also formed at the same time.

After the photoresist pattern 11 is completely removed, as shown in FIG. 3B, unlike the conventional case, the region of the N-type well 2 is covered and the boundary between the N-type well 2 and the P-type well 3 is removed. Using the photoresist pattern 13 extended to the P-type well 3 side by about 4 μm as a mask, ions are implanted so as to have a higher impurity concentration than the P-type well 3 to form a P-type diffusion layer 74. In this process, high withstand pressure PM
The offset diffusion layer of the OSFET is formed at the same time. After the ion implantation into the diffusion layers 61 and 74, 1000 ° C.
A 0 minute heat treatment is performed.

As described above, according to the present invention, the diffusion layers 61 and 74 are provided.
Can be formed simultaneously with the offset diffusion layer of the high breakdown voltage CMOSFET, and the advantage of low cost with a small number of steps can be avoided.

After the photoresist pattern 13 is further removed, as shown in FIG.
Select LOC at 1000 ° C. to cover mold diffusion layer 74
An OS oxide film 8 is formed. Next, after removing the silicon nitride film 10a, a gate insulating film and a gate electrode of a high breakdown voltage CMOSFET (not shown) are formed. Thereafter, as shown in FIG. The band diffusion layer 4 and the P-type guard band diffusion layer 6 having a higher impurity concentration than the P-type diffusion layer 74 are formed by a masking process, ion implantation, and heat treatment at 1100 ° C. for 40 minutes and 1000 ° C. for 10 minutes. The protective oxide film 9 is removed.

In the present embodiment, a P-type silicon substrate is used, but an N-type substrate may be used. Also, P
It is apparent that the present invention is effective for a semiconductor device having only one well, in addition to a semiconductor device having both a well and an N-type well. The order of forming the N-type offset diffusion layer and the P-type offset diffusion layer is not limited.

[0030]

As described above, according to the present invention, the structure in which the N-type diffusion layer and the P-type diffusion layer serving as the channel stop at the boundary of the well are separated from each other can be realized without increasing the number of steps. The advantageous effect that the withstand voltage between wells of a semiconductor integrated circuit having a withstand voltage CMOSFET can be greatly improved can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional structural view of a well boundary of a high-voltage integrated circuit of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of the high breakdown voltage integrated circuit of the semiconductor device.

FIG. 3 is a cross-sectional view showing a step of manufacturing the high breakdown voltage integrated circuit of the semiconductor device.

FIG. 4 is a cross-sectional view showing a step of manufacturing the high breakdown voltage integrated circuit of the semiconductor device.

FIG. 5 is a sectional structural view of a high-voltage integrated circuit including a well boundary of a conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 P-type silicon substrate 2 N-type well 3 P-type well 4 N-type guard band diffusion layer 5 P-type guard band diffusion layer 6 N-type offset diffusion layer 7 P-type offset diffusion layer 8 LOCOS oxide film 9 Protective oxide film 10 Silicon nitride Film 10a Silicon nitride film 11 Photoresist pattern 12 Photoresist pattern 13 Photoresist pattern 14 Gate insulating film 15 Gate electrode 16 N-type drain diffusion layer 17 N-type source diffusion layer 18 P-type drain diffusion layer 19 P-type source diffusion layer 61, 62, 63 N-type diffusion layer 71, 72, 73, 74 P-type diffusion layer

Claims (4)

[Claims] At least a portion of a first conductivity type well and a second conductivity type well are formed on the surface of a first conductivity type substrate, and the surface region of the first conductivity type well includes the first conductivity type well. A first diffusion layer having a higher impurity concentration than the one conductivity type well; a second diffusion layer having a higher impurity concentration than the second conductivity type well in a surface region of the second conductivity type well; A semiconductor device, wherein both the one diffusion layer and the second diffusion layer are formed without contacting at the same portion of a boundary where the first conductivity type well and the second conductivity type well contact. 2. The semiconductor device according to claim 1, wherein a high breakdown voltage element is formed in each of the first conductivity type well and the second conductivity type well. 3. The method according to claim 1, wherein the first diffusion layer has the same conductivity type as the first conductivity type well, and the second diffusion layer has the same conductivity type as the second conductivity type well. The semiconductor device according to claim 1. 4. A second conductivity type well is formed on a surface of the first conductivity type substrate, and a high breakdown voltage element is formed on each of the first conductivity type substrate and the second conductivity type well. The region has a higher impurity concentration than the first conductivity type substrate and has a first diffusion layer of the first conductivity type, and a surface region of the second conductivity type well has a higher impurity concentration than the second conductivity type well. Having a second diffusion layer of a second conductivity type with a concentration, wherein both the first diffusion layer and the second diffusion layer are formed without contacting at the same portion of the boundary of the second conductivity type well A semiconductor device characterized by the above-mentioned.