JP2000011671A - Semiconductor storage device - Google Patents

Abstract

(57) [Problem] To provide a semiconductor memory device in which the temperature dependency of an internal voltage has the same tendency as the temperature dependency of a memory cell threshold voltage, and a read voltage margin can be secured. SOLUTION: This is a 256M flash memory in which a memory cell current at the time of reading is about 1 μA or less, which comprises a memory matrix composed of a plurality of memory cells, its peripheral circuits, and the like. A temperature-dependent compensation circuit having a negative temperature dependency is included for compensating for the internal voltage at the time and corresponding to the negative temperature dependency of the memory cell threshold voltage. The temperature compensating circuit 22 of the temperature-dependent compensating circuit includes a NMOS transistor TN on the right side.
, TN22,..., TN22 are different from the constant Wleft of the left NMOS transistor TN6, and a combination in which the constant Wr is larger than the constant Wleft is trimmed to obtain negative temperature dependence.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device technology, and more particularly, to a method for ensuring that a temperature dependency of an internal voltage has the same tendency as a temperature dependency of a memory cell threshold voltage to secure a read voltage margin. Flash EE
The present invention relates to a technology effective when applied to a semiconductor storage device such as a PROM (flash memory).

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventors, in a semiconductor memory device such as a flash memory, the temperature dependency of an internal voltage at the time of reading is + 2%, and the temperature dependency of a memory cell threshold voltage is-. A technology having an internal power supply circuit having a temperature characteristic of a positive characteristic with respect to a memory cell threshold voltage having a temperature characteristic of a negative characteristic so as to have a dependence opposite to 2% is considered.

As a technique relating to an internal power supply circuit in a semiconductor memory device such as a flash memory, for example, “Advanced Electronics I-9 Ultra L” issued by Baifukan Co., Ltd. on November 5, 1994.
SI memory "on page 239 to P324.

[0004]

By the way, in a semiconductor memory device such as a flash memory as described above,
Since the temperature dependence of the memory cell threshold voltage has an inverse dependence on the internal voltage at the time of reading, the temperature at the time of writing and at the time of reading greatly affects, and the reading at a low temperature after writing at a high temperature, It is conceivable that the read voltage margin is reduced in the high-temperature read after the low-temperature write.

It is an object of the present invention to provide a semiconductor memory device such as a flash memory in which the temperature dependency of an internal voltage has the same tendency as the temperature dependency of a memory cell threshold voltage, and a read voltage margin can be secured. Is provided.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the semiconductor memory device of the present invention is applied to a semiconductor memory device including an internal power supply circuit for generating a predetermined internal voltage, and the temperature characteristic of the memory cell threshold voltage shows a large negative characteristic. Therefore, the internal power supply circuit
A temperature-dependent compensation circuit with negative temperature dependence is provided to compensate for the internal voltage during reading, and the temperature dependence of the internal voltage during reading and the temperature dependence of the memory cell threshold voltage are combined to ensure a read voltage margin. Is what you do.

In this configuration, the temperature-dependent compensation circuit includes:
It includes a buffer circuit in which the constants of a pair of NMOS transistors or PMOS transistors are unbalanced, and further includes a trimming circuit that can arbitrarily vary the temperature dependency of the internal voltage. In particular, multi-valued memory cells,
Applied to a flash memory, the memory cell current at the time of reading is set to about 1 μA or less.

Therefore, according to the semiconductor memory device, a read voltage margin can be secured by matching the temperature dependency of the internal voltage with the temperature dependency of the memory cell threshold voltage. The temperature dependency of the internal voltage can be arbitrarily varied by a trimming circuit.

In particular, in a multi-valued memory cell, it is necessary to improve the voltage accuracy as compared with a conventional product, and if a voltage margin can be secured as in the present invention, the reliability of the multi-valued memory cell is increased. The trimming circuit can cope with process variations. This is effective when applied to a flash memory, particularly to a multi-level flash memory that needs to secure a voltage margin.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a configuration diagram showing a semiconductor memory device according to one embodiment of the present invention, FIG. 2 is a configuration diagram showing a read voltage generation circuit portion in the semiconductor memory device of this embodiment, and FIGS. 6 is a circuit diagram showing a temperature-dependent compensation circuit, FIG.
8 is a circuit diagram showing a buffer circuit, FIG. 8 is a characteristic diagram showing temperature dependency, FIG. 9 is an explanatory diagram showing a comparison result of temperature dependency between the present embodiment and a comparative technique, and FIGS. FIG. 12 is an explanatory diagram showing a memory cell, and FIG. 12 is a circuit diagram showing a modification of the buffer circuit.

First, the configuration of the semiconductor memory device according to the present embodiment will be described with reference to FIG.

In the semiconductor memory device of the present embodiment, for example, the memory cell current at the time of reading is 25
6M flash memory, a memory matrix 1 composed of a plurality of memory cells, an X address buffer 2 for designating an arbitrary address, an X predecoder 3, an X decoder 4, a Y address counter 5, and a Y decoder 6
And an input / output buffer 7 for reading / writing data, a main amplifier 8, a Y gate 9 and a data register 10, a control signal input buffer 11, a controller 12, a system clock circuit 13, and an internal power supply circuit 1.
4. It has a general configuration such as a voltage conversion circuit 15, and is formed on one semiconductor chip by a known semiconductor manufacturing technique.

In this flash memory, the chip enable signal CEB,
A write enable signal WEB, a reset signal RESB,
Control signals such as a command data enable signal CDEB, an output enable signal OEB, and a serial clock signal SC are input, an internal control signal is generated based on these control signals, and a clock generated through the controller 12 and the system clock circuit 13. Signal CLK
The internal circuit is controlled in synchronization with. Further, the power supply voltage VCC and the ground voltage VSS are externally input to the internal power supply circuit 14, and various internal voltages are generated and supplied to the internal circuits.

In the flash memory, an X address by an X address buffer 2, an X predecoder 3 and an X decoder 4, and an X address by a Y address counter 5 and a Y decoder 6 based on externally input address signals A0 to A13. When a Y address is designated and an arbitrary memory cell in the memory matrix 1 is selected, and at the time of reading,
Output data I / O0 to I / O from the input / output buffer 7 via the data register 10, the Y gate 9, and the main amplifier 8
7 is output, and at the time of writing, input data I / O0-I
/ O7 is input from the input / output buffer 7.

The memory matrix 1 is made up of, for example, four-valued multi-valued memory cells, and therefore has a memory capacity of 16384 × (2048 + 64) × 4 I / Os.
There are times. Since the input / output configuration is multivalued, the memory matrix is 4 I / O and the input / output of the chip is 8 I / O.

The X address buffer 2 stores the input X address signals A0 to A13.

The X predecoder 3 outputs an X address signal A0.
To A13 are decoded twice. This is two times more than decoding the X address signals A0 to A13 once.
This is because it is more efficient to decode each time. The X predecoder 3 also includes a circuit for changing a signal from the X address buffer 2 from a VCC / VSS amplitude to a VCP / VSS amplitude. This is because the X decoder 4 has a VCP
This is because the logic is (internal power supply voltage) / VSS.

The X decoder 4 transmits a predetermined voltage to a word line in the memory matrix 1 corresponding to the X address signal of the X address buffer 2. The predetermined voltage is, for example, -16 V during erasing, 17 V during writing, and 2.4 to 4.0 V during reading. The logic circuit in this X decoder 4 is not VCC / VSS, but 7 V internal power supply voltage VC.
It operates with P / VSS.

The Y address counter 5 receives the input data I /
When inputting O0 to I / O7 into the data register 10, when outputting the output data I / O0 to I / O7 from the data register 10, the Y address signal is incremented in order to serially access Y = 0 to 2048 + 64.

The Y decoder 6 turns on the Y gate 9 corresponding to the Y address signal in the Y address counter 5.

The input / output buffer 7 includes address signals A0 to A0.
A13 and input / output data I / O0-I / O7,
The address signal is divided into two signals A0 to A7 and A8 to A13.

The main amplifier 8 amplifies data from the data register 10 through the Y gate 9.

The Y gate 9 connects between the data register 10 corresponding to the Y address signal selected by the Y decoder 6 and the main amplifier 8.

The data register 10 stores input / output data I /
O0 to I / O7 are stored. For multi-valued memory cells, for example, the number of Y addresses of memory matrix 1 is 2048 + 6
4 times, ie 2048 + 64 data registers 1
There are two sets of 0s.

The control signal input buffer 11 is an input buffer for an external control signal.

The controller 12 determines which mode has been entered from the control signal, and generates a control signal in each block in synchronization with the clock signal CLK. The modes include read, erase, and write.

The system clock circuit 13 receives a start signal from the controller 12 and generates a clock signal CL having a predetermined period.
K, for example, 10 MHz and 20 MHz.

The internal power supply circuit 14 internally generates a voltage in order to apply a voltage other than VCC to the word line, and particularly includes a temperature-dependent compensation circuit described later. VSS to V
It comprises a step-down circuit for generating CC and a step-up circuit for generating a voltage higher than the negative voltage / VCC. The booster circuit performs a boosting operation using the clock signal CLK.

The voltage conversion circuit 15 converts the signal input to the sub-gate decoder and the main decoder of the X decoder 4 to VCC /
This is a circuit for changing the VSS amplitude to the VCP / VSS amplitude.

In the flash memory configured as described above, the internal power supply circuit 14 compensates for the internal voltage particularly at the time of reading, and responds to the negative characteristic of the temperature dependence of the memory cell threshold voltage. A temperature-dependent compensating circuit 16 having a temperature dependency is included, and the temperature dependency of the internal voltage at the time of reading and the temperature dependency of the memory cell threshold voltage are combined to ensure a read voltage margin. It has become.

As shown in FIG. 2, for example, as shown in FIG. 2, a temperature-dependent compensation circuit 16 is connected between a reference voltage generation circuit 17 and a read voltage generation circuit 18, The temperature dependence of the reference voltage VREFxx output from the voltage generation circuit 17 is compensated through the temperature dependence compensation circuit 16 to the same temperature dependence as the memory cell threshold voltage, and the compensated voltage SREFxx is supplied to the read voltage generation circuit 18. Is done.

The temperature dependent compensation circuit 16 includes, for example, a signal generation circuit 19 shown in FIG. 3, a trimming decoder circuit 20 shown in FIG. 4, and a VN generation circuit 2 shown in FIG.
1 and a temperature compensating circuit 22, and a voltage dividing circuit 23 shown in FIG. Hereinafter, these circuit configurations and circuit operations will be described.

As shown in FIG. 3, the signal generation circuit 19 includes inverters IV1 to IV4, a NAND gate NAND1,
A delay DLY1 receives a start signal CXHSYSE from the controller 12, and receives signals FRENB and FREB.
This circuit generates NT and FSTUP and supplies a start signal to each part of the temperature-dependent compensation circuit 16. Controller 12
When the start signal CXHSYSCE from the
NT = VSS, FSTUP = VCC. CXHSY
When CE = VCC, FRENT = VCC, FREN
B = VSS, and FSTUP becomes a pulse (VSS) having a width of 10 ns using a delay DLY1 with a delay of 10 ns.

As shown in FIG. 4, the trimming decoder circuit 20 includes inverters IV5 to IV7 and a NOR gate N.
This circuit includes OR1 to NOR6 and performs trimming. The temperature compensating circuit 22 detects the voltage of the MOS transistor
Since the current characteristics are used, the output voltage value may be shifted due to process variations. To correct the deviation, trimming is performed by a fuse. Input signal TD4
<0>, <1>, and <2> are decoded and set in eight ways by combinations, and one of the output signals TM0 to TM7 is set.
One goes to VCC and the other goes to VSS.

As shown in FIG. 5, the VN generation circuit 21
The circuit includes OS transistors TP1 to TP5, NMOS transistors TN1 to TN4, depletion PMOS transistors DTP1 to DTP3, and a depletion NMOS transistor DTN1, and determines a current flowing to the temperature compensation circuit 22. The reference voltage VREF16 = 1.6V generated by the reference voltage generation circuit 17 is applied to the gate of the NMOS transistor TN2.

In the VN generating circuit 21, when not operating, no current flows with the input signal REFENT = VSS, but when REFENT = VCC, a current determined by the constant W / L of the NMOS transistor TN2 flows. PMOS
The current is mirrored by the transistors TP3 to TP5, and a current twice as large as that of the NMOS transistor TN2 flows through the NMOS transistor TN4. In addition, NM
A current mirror is performed between the OS transistor TN4 and the temperature compensating circuit 22, and the temperature compensating circuit 22 passes a current six times as large as that of the NMOS transistor TN2. This current value has no meaning and only determines the operation speed of the circuit.

The temperature compensation circuit 22, as shown in FIG.
The circuit includes OS transistors TP6 and TP7, NMOS transistors TN5 to TN25, depletion PMOS transistors DTP4 and DTP5, and depletion NMOS transistors DTN2 and DTN3. This circuit configuration is a normal NMOS buffer. However, the NMO on the right
The constant Wr * of each of the S transistors TN8, TN10,..., TN22 is different from the constant Wleft of the left NMOS transistor TN6. Because of such a buffer structure,
The same current flows through the left and right NMOS transistors,
Since the constant W is different, the gate voltages of the NMOS transistors are different on the left and right. By changing this constant, the NMOS
The operating voltage Vgs of the transistor is changed to add temperature dependency. The output signal SREF13B is about 1.3V.

In the temperature compensation circuit 22, the constant W
When the constant Wr is large, the temperature dependence is negative with respect to the left, and when the constant Wr is small, the temperature dependence is positive. Further, when Wleft = Wr, there is no temperature dependency. If Wleft ≠ Wr, VREFxx
Since it becomes ≠ SREF13B, the voltage value of VREFxx is also trimmed in accordance with the trimming of Wr. In the present embodiment, a combination in which a negative temperature dependency is obtained is trimmed corresponding to the negative temperature dependency of the memory cell threshold voltage.

As shown in FIG. 6, the voltage dividing circuit 23 includes a PMOS
It comprises transistors TP8 to TP33, NMOS transistors TN26 to TN39, depletion PMOS transistors DTP6 to DTP11, and capacitors C1 to C8.
Based on the output SREF13B of the temperature compensation circuit 22,
F01 to SREF16 = 0.1 to 1.6V in steps of 0.1V.

In the voltage dividing circuit 23, when not operating,
PM because FRENT = VSS and FRENB = VCC
OS transistors TP14, TP16, TP18, TP
20, TP22, TP24 and TP26 gates are VC
C, NMOS transistors TN33, TN35, TN3
7, the gate of TN39 becomes VSS, and the circuit does not operate. When the start signal is input, the switching between the Frent and the Frenn switches, and the PMOS transistors TP14, TP16, T
P18, TP20, TP22, TP24, TP26, N
MOS transistors TN33, TN35, TN37, T
The gate of N39 is no longer fixed to VCC and VSS.
Then, the signal FSTUP is output from the PMOS transistor TP3.
When it goes to 0, it turns on for 10 ns and charges node A to VCC. When the node A is charged, a current flows through the PMOS transistor TP33. The NMOS transistors TN28, TN30, TN33,.
Since the current mirrors are MOS transistors, the same current flows through these NMOS transistors. Also,
The current of the NMOS transistor TN37 is current mirrored to the NMOS transistor TN33, passes through the PMOS transistor TP14, and passes through the PMOS transistors TP9 and TP9.
The same current is applied to TP11, TP14,..., TP26 by the current mirror.

At this time, the circuit to which the signal SREF13B is input is a PMOS buffer, and transmits the SREF13B to the node B. PMOS transistor TP32 and PMO
The S transistor TP33 has the gate voltages of the nodes B and C, respectively, but the NMOS transistors TN35 and TN3
7, the same current flows through the PMOS transistor TP3
2 and the PMOS transistor TP33 have the same current. However, if the potentials of the nodes B and C are different, the current balance is lost, and the PMOS transistors TP9 and T
By changing the gate voltages of P11, TP14,..., TP26, a balance is achieved and the state shifts to a stable state.

For example, the node C at the time of startup is set to VSS by the depletion PMOS transistors DTP6 to DTP11. When node B reaches 1.3V, P
Since the current flows through the MOS transistor TP33 from the PMOS transistor TP32, the gate voltage of the NMOS transistor TN37 increases. Then, node C
Potential rises. It is stabilized when the potential of the node C becomes equal to that of the node B. Conversely, the potential at node C is
Even in the case where the voltage becomes higher, the gate potentials of the PMOS transistors TP32 and TP33 are similarly changed to change the current flowing through the depletion PMOS transistors DTP6 to DTP11, thereby enabling a transition to a stable state.

Next, an example of a buffer circuit having a negative temperature dependency in the temperature compensation circuit 22 will be described with reference to the circuit diagram of FIG. 7 and the characteristic diagram of FIG. This buffer circuit corresponds to, for example, a portion including the NMOS transistor TN6 and the NMOS transistor TN8 shown in FIG. As shown in FIG. 7, the constants of the left NMOS transistor and the right NMOS transistor are different, and the gate width Wl of the left NMOS transistor for the same gate length.
Is 15 μm, the gate width W of the right NMOS transistor
r is formed in a size of 150 μm.

In this buffer configuration, the input voltage Vi
When n = 1.6V and output voltage Vout = 1.3V, Vg
FIG. 8 shows the temperature characteristics based on the relationship between s and Ids.
That is, at the temperature Ta = -5 ° C., Vin = 1.6 V / V
out = 1.3 V (points A and B). Ta = 8
When the temperature reaches 0 ° C., it is fixed at Vin = 1.6 V.
The current flowing through the MOS transistor decreases (point C).
Accordingly, the same current flows in the left and right NMOS transistors, so that the current in the right NMOS transistor also decreases. FIG. 8 shows the current value per unit W, so that the current on the right side decreases at the same rate as that on the left side (because it is a log scale, it moves downward by the same length). Left NMOS
To reduce the current by the same amount as the transistor, the NM on the right
Vgs of the OS transistor decreases (point D). Therefore,
At a high temperature, a characteristic of decreasing by ΔV, that is, a negative temperature dependency is obtained. This is because the memory cell current at the time of reading is 1 μm.
This is because the temperature dependence of the Ids characteristics of the NMOS transistor is shifted by Vgs when the region is close to the tailing region of about A or less.

As described above, a pair of N with different constants
By configuring the temperature compensation circuit 22 having a buffer circuit using MOS transistors, the read voltage can have a negative temperature dependency. Here, a comparison between the technology of the present embodiment having the temperature-dependent compensation circuit 16 and the technology without the temperature-dependent compensation circuit will be described based on the explanatory diagram of the temperature-dependent characteristics of the memory cell threshold voltage in FIG. I do.

As shown in FIG. 9, in the comparative technique, the memory cell threshold voltage Vth
Has a negative characteristic of downward sloping and a positive characteristic of read voltage of upward sloping, and has opposite characteristics. For this reason, at room temperature of Ta = RT, even if there is a voltage margin due to a sufficient interval between the read voltage and each memory cell threshold voltage Vth, at a low temperature of Ta = −5 ° C., the memory cell threshold on the lower voltage side. The interval from the voltage Vth becomes narrow, and T
Conversely, at a high temperature of a = 80 ° C., the interval between the memory cell threshold voltage Vth on the high voltage side becomes narrow, and the voltage margin decreases at low and high temperatures.

On the other hand, in the present embodiment,
Since both the memory cell threshold voltage Vth and the read voltage have negative characteristics of falling to the right, a sufficient voltage margin between the read voltage at room temperature and each memory cell threshold voltage Vth is reduced even at low and high temperatures. The same voltage margin can be secured without performing. this is,
This is because the temperature dependency of the read voltage is made to have the same tendency as the memory cell threshold voltage Vth by the temperature dependency compensation circuit 16 as described above.

Further, in the present embodiment, since the memory matrix 1 is composed of four-valued multi-valued memory cells, there is an advantage at the time of multi-valued application, and the state of the multi-valued memory cell threshold voltage Vth 10 and FIG. 11 showing the variation of the threshold voltage Vth with respect to the leaving time. FIG. 10A shows a 1-bit binary example, and FIG. 10B shows a 2-bit quaternary example. In the multi-valued memory cell, in order to write two or more bits of information into one memory cell, the memory cell threshold voltage Vth is changed from two values of “0” and “1” (FIG. 10A) to FIG. 4 or more (2) as shown in (b)
Since 56M has four values, “10”, “00”, “01”,
(4 of "11")

In order to separate the state of each memory cell, an interval of each memory cell threshold voltage Vth is provided. In this case, in the method of making the interval of the memory cell threshold voltage Vth large, the memory cell threshold voltage Vth is changed to the original threshold voltage (Vthi: Vth initi) of the memory cell.
The characteristic returning to al) cannot be adopted because the power difference increases as the voltage difference increases as shown in FIG.

In FIG. 11, although the memory cell threshold voltage Vth drops by 0.6 V from 4 V to 3.4 V, 90
It takes 0hr, but 0.6V from 3.4V to 2.8V
The decrease takes as much as 9000 hours. Therefore, for example, when it is desired to maintain the memory cell threshold voltage Vth at 2.8 V or more, even if the threshold voltage Vth is increased from 3.4 V to 4 V, it only increases from 9000 hr to 9900 hr,
Time margins can only be saved.

Therefore, since the voltage value of the uppermost and lowermost memory cell threshold voltages Vth is determined by the characteristic of returning to the original threshold voltage of the memory cells, the voltage value of each memory cell threshold voltage Vth Of the internal power supply applied to the word line at the time of reading, which separates the state of each memory cell, and the variation due to the VCC dependency are adopted. The present embodiment is a technique for reducing the variation of the internal power supply applied to the word line at the time of reading, and is effective in the case where the number of values further increases and the number of values increases from four to eight or more in the future.

Therefore, according to the semiconductor memory device of the present embodiment, the signal generation circuit 19 and the trimming decoder circuit 2
0, a VN generating circuit 21, a temperature compensating circuit 22 and a temperature-dependent compensating circuit 23 are connected between a reference voltage generating circuit 17 and a read voltage generating circuit 18. By adjusting the temperature dependency to the temperature dependency of the memory cell threshold voltage, a read voltage margin can be secured. The temperature dependency of the internal voltage can be arbitrarily varied by the trimming decoder circuit 20. In particular, in a multi-level memory cell, a sufficient voltage margin can be ensured, so that the reliability in the multi-level memory cell is increased, and the trimming decoder circuit 20 can cope with process variations.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above embodiment, the case where the temperature-dependent compensation circuit is constituted by the NMOS buffer has been described. However, the present invention is not limited to this.
2, it is also possible to use a PMOS buffer. In this case, there is an advantage that the input and output can be set lower than those of the NMOS transistor type.

Further, the capacity is not limited to 256 Mbits and the number of memory cells is not limited to four values.
The present invention can be widely applied to a flash memory of 2 M bits or more, a multi-level memory cell of 8 levels or more, and the effect of the present invention is more effective as the capacity and the number of levels are increased.

In addition to the flash memory, EEPR
The present invention can be widely applied to other semiconductor memory devices that need to secure a voltage margin such as OM.

[0060]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) The internal power supply circuit is provided with a temperature-dependent compensation circuit having a negative temperature dependency by compensating the internal voltage at the time of reading, so that the temperature dependency of the internal voltage at the time of reading is stored in a memory cell. Since the threshold voltage can be adjusted to the temperature dependency, a read voltage margin can be secured.

(2) The temperature-dependent compensation circuit includes a buffer circuit in which the MOS transistor constants are unbalanced, and a trimming circuit that can arbitrarily vary the temperature dependency of the internal voltage. By selecting a buffer circuit, the temperature dependency of the internal voltage can be easily varied.

(3) In a multi-level memory cell, a sufficient voltage margin can be secured, so that the reliability of the multi-level memory cell can be improved.

(4) Since the temperature dependency can be arbitrarily varied by the trimming circuit, it is possible to cope with process variations.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a semiconductor memory device according to an embodiment of the present invention;

FIG. 2 is a configuration diagram showing a read voltage generation circuit portion in the semiconductor memory device according to one embodiment of the present invention;

FIG. 3 is a circuit diagram showing a signal generation circuit of a temperature-dependent compensation circuit in one embodiment of the present invention.

FIG. 4 is a circuit diagram showing a trimming decoder circuit of a temperature-dependent compensation circuit in one embodiment of the present invention.

FIG. 5 is a circuit diagram showing a VN generating circuit and a temperature compensating circuit of the temperature-dependent compensating circuit in one embodiment of the present invention.

FIG. 6 is a circuit diagram showing a voltage dividing circuit of a temperature-dependent compensation circuit in one embodiment of the present invention.

FIG. 7 is a circuit diagram showing a buffer circuit in one embodiment of the present invention.

FIG. 8 is a characteristic diagram showing temperature dependency in one embodiment of the present invention.

FIG. 9 is an explanatory diagram showing a comparison result of temperature dependency between the embodiment and the comparative technique.

FIGS. 10 (a) and (b) show one embodiment of the present invention.
FIG. 4 is an explanatory diagram showing the states of threshold voltages of binary and quaternary memory cells.

FIG. 11 is a characteristic diagram showing a change in a threshold voltage of a multi-level memory cell in one embodiment of the present invention.

FIG. 12 is a circuit diagram showing a modified example of the buffer circuit in one embodiment of the present invention.

[Explanation of symbols]

1 Memory Matrix 2 X Address Buffer 3 X Predecoder 4 X Decoder 5 Y Address Counter 6 Y Decoder 7 Input / Output Buffer 8 Main Amplifier 9 Y Gate 10 Data Register 11 Control Signal Input Buffer 12 Controller 13 System Clock Circuit 14 Internal Power Supply Circuit 15 Voltage conversion circuit 16 Temperature dependent compensation circuit 17 Reference voltage generation circuit 18 Readout voltage generation circuit 19 Signal generation circuit 20 Trimming decoder circuit 21 VN generation circuit 22 Temperature compensation circuit 23 Voltage divider circuit C1 to C8 Capacitor DLY1 Delay DTN1 to DTN3 Depletion NMOS transistor DTP1 to DTP11 Depletion PMOS transistors IV1 to IV7 Inverter NAND1 NAND gate NOR1 to NOR6 NOR gate TN ~TN39 NMOS transistor TP1~TP33 PMOS transistor

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Shoji Kubono 5-22-1, Josuihonmachi, Kodaira-shi, Tokyo F-term in Hitachi Super LSI Systems Co., Ltd. 5B025 AD03 AE08

Claims (5)

[Claims] 1. A semiconductor memory device including an internal power supply circuit for generating a predetermined internal voltage, wherein the internal power supply circuit comprises:
A temperature-dependent compensation circuit having a negative temperature dependency corresponding to a negative characteristic of the temperature dependency of the memory cell threshold voltage, wherein the temperature dependency of the internal voltage at the time of reading is compensated. And a temperature dependency of the memory cell threshold voltage to secure a read voltage margin. 2. The semiconductor memory device according to claim 1, wherein said temperature-dependent compensation circuit includes a buffer circuit in which the constants of a pair of NMOS transistors or PMOS transistors are unbalanced. . 3. The semiconductor memory device according to claim 2, wherein said temperature-dependent compensation circuit includes a trimming circuit capable of arbitrarily changing the temperature dependence of an internal voltage. 4. The semiconductor memory device according to claim 1, wherein said memory cell is a multi-valued memory cell. 5. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a flash EEPROM, and a memory cell current at the time of reading is one.
A semiconductor memory device having a current of about μA or less.