JP2000011400A - Signal detection circuit of optical disk drive - Google Patents

Abstract

(57) [Problem] To appropriately cancel a circuit offset and an optical offset generated in a servo signal. SOLUTION: A focus signal operation amplifier 21 calculates and outputs a focus signal based on a plurality of output signals from divided light receiving elements of an optical pickup, and a differential amplifier 24 outputs a focus signal output from the focus signal operation amplifier 21. 1st system offset cancel voltage: FEOF
The VCA 25 normalizes the focus signal after the application of the first system offset cancel voltage: FEOFS-E with the sum signal by the AGC control circuit 45, and outputs the result. Applies the second system offset cancel voltage: FEOFS-O to the normalized servo signal and outputs it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a signal detection circuit in an optical disk drive.

[0002]

2. Description of the Related Art FIG. 16 is a circuit diagram showing a servo signal calculation section of a signal detection circuit in a conventional optical disk drive. The focus signal operation amplifier 61 of the servo signal operation unit receives four output signals VA to VD from the detector having the divided light receiving elements of the optical pickup, and performs an operation based on the operation expression (VA + VC)-(VB + VD). The output signal obtained by the above is output. Such a focus signal detection method is called an astigmatism method.

[0003] A DA converter (DAC) 62
A predetermined offset cancel signal is output to the amplifier 63. The offset cancel data “FEOFS” of the offset cancel signal output from the DAC 62 is set from the CPU or the like of the optical disk drive. Then, the amplifier 63 removes an offset from the focus signal obtained by the calculation by the focus signal calculation amplifier 61, and outputs the focus signal from the signal terminal FE.

On the other hand, a tracking signal operation amplifier 71
Inputs four output signals VA to VD from a detector having a divided light receiving element of an optical pickup, and calculates an arithmetic expression (VA +
An output signal obtained by performing an operation based on (VD)-(VB + VC) is output. Such a tracking signal calculation method is called a push-pull method.

[0005] A DA converter (DAC) 72 is
A predetermined offset cancel signal is output to the amplifier 73. The offset cancel data “TEOFS” of the offset cancel signal output from the DAC 72 is set by the CPU or the like of the optical disk drive. Then, the amplifier 73 removes an offset from the tracking signal obtained by the calculation by the tracking signal calculation amplifier 71, and outputs the tracking signal from the signal terminal TE.

[0006] As described above, the focus signal and the tracking signal calculated by the focus signal calculation amplifier 61 and the tracking signal calculation amplifier 71, respectively, generally include offset signals roughly classified into two types.

One of them is called a circuit offset, which is caused by a circuit offset of an IV amplifier, a focus signal operation amplifier 61, a tracking signal operation amplifier 71, etc. of a detector of an optical pickup. The circuit offset is constant irrespective of the signal level input to the photodetector, and constantly occurs even when the laser power is turned off.

The circuit offset generally increases as the amplifier gain increases. That is, normally, the gain of the amplifier in the preceding stage is increased to improve the S / N ratio, so that the circuit offset is mainly generated by the IV amplifier, the focus signal operation amplifier 61, and the tracking signal operation amplifier 71. It is.

The other is called an optical offset, which is caused by an assembly error of an optical pickup or the like. This optical offset changes depending on the signal level input to the photodetector. Therefore, the optical offset changes depending on the disk reflectivity and the laser power.

[0010]

However, in the signal detection circuit of the conventional optical disk drive, a certain amount of offset signal can be canceled by the DACs 62 and 72. However, as described above, the offset generated in the servo signal is
An almost constant amount of circuit offset and an optical offset that fluctuates depending on the reflectivity of the laser power disk are mixed, and there has been a problem that complete offset cancellation cannot be performed.

The offset generated in the servo signal is
A focus shift and a tracking shift of a laser beam caused by an optical pickup are caused, so that there are problems such as that data on an optical disc cannot be reproduced correctly and data cannot be recorded on an optical disc correctly.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object to appropriately cancel a circuit offset and an optical offset generated in a servo signal.

[0013]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a servo signal operation circuit for calculating a servo signal of a focus signal and a tracking signal based on a plurality of output signals from divided light receiving elements of an optical pickup. When,
First system offset cancel voltage applying means for applying a first system offset cancel voltage to the servo signal output from the servo signal calculation circuit; and a first system offset cancel voltage after the first system offset cancel voltage is applied by the means. Servo signal normalizing means for normalizing a servo signal with a sum signal of the plurality of output signals, and a second system offset cancel for applying a second system offset cancel voltage to the servo signal normalized by the means Provided is a signal detection circuit of an optical disk drive including a voltage application unit.

In the above-described signal detection circuit of the optical disk drive, the gain is switched to one of two types of gains based on a predetermined switching signal, and a plurality of gains from the divided light receiving elements are determined based on the switched gain. And a current-voltage conversion circuit for converting the current signals of the output signals into voltage signals, and a level of the first system offset cancel voltage applied by the first system offset cancel voltage applying means based on the predetermined switching signal. Offset cancel voltage level switching means for switching to one of two types of levels of the small system is provided. Based on the predetermined switching signal, switching of the type of gain in the current-voltage conversion circuit and the offset cancel voltage level switching means are performed. It is good to link the switching of the level type of the small system

[0015]

Embodiments of the present invention will be specifically described below with reference to the drawings. FIG. 2 is a diagram showing a configuration of an optical disk drive according to one embodiment of the present invention.

This optical disk driving device includes an optical disk 1
Is irradiated with the laser beam L emitted from the optical pickup 2. The laser drive circuit 3 drives the optical pickup 2 to irradiate the laser beam L with a predetermined reproduction power value during data reproduction, and drives the optical pickup 2 according to the modulation pattern output from the modulation circuit 4 during data recording. Then, a laser beam is irradiated at a predetermined recording power.

The optical pickup 2 has a detector provided therein with a divided light receiving element and a current / DC converter (IV converter), and the detector converts the laser beam reflected from the optical disk 1 into a voltage signal. . The signal detection circuit 5 outputs an RF signal and a servo signal corresponding to the reproduced data from the output signal of the optical pickup 2. The servo signal includes a focus signal for focus control, a track signal for tracking control, and the like.

The servo circuit 7 drives the actuator of the optical pickup 2 based on the servo signal, and causes the laser beam L to follow a track on the optical disk 1. C
The PU 8 is a microcomputer, and controls the entire optical disk drive. Spindle motor 9
Drives the optical disk 1 to rotate at a predetermined number of rotations.

FIG. 3 is a diagram showing a configuration of a detector in the optical pickup 2 of FIG. This detector is a photodetector 10 composed of four divided light receiving elements 10a to 10d.
And four IV amplifiers (IV conversion circuits) 11a to 11d
Consists of

When each of the divided light receiving elements 10a to 10d of the photodetector 10 converts an optical signal based on the light reflected from the optical disk 1 into a current signal, the IV amplifier 11a
To each of the IV amplifiers 11a to 11d.
d converts each input current signal into a voltage signal and outputs it.

Generally, there is a difference of about 10 times between the reproduction power value of the laser beam L and the recording power value, so that the optical signal input to the photodetector 10 has the same ratio difference between the reproduction time and the recording time.

Each of the IV amplifiers 11a to 11d is switchable between two kinds of gains, high and low. The gains are switched to a high gain when reproducing data, and a low gain when recording data. Thus, a voltage signal having a sufficient amplitude can be obtained, and the data signal is prevented from being saturated during data recording with a high laser power.

FIG. 1 is a diagram showing a detailed internal configuration of the signal detection circuit 5 shown in FIG. This signal detection circuit 5
Is a voltage “FEOF” for the DA converter (DAC) 23 to cancel the circuit offset of the focus signal.
The selector (SEL) 22 inputs two types of offset cancel data “FEOFS1” and “FEOFS2”, selects one of them, and inputs it to the DAC 23.

That is, W which becomes "H" during data recording
The GATE signal is input, and “FEOFS1” is output to the DAC 23 when the WGATE signal is “high (H)”, and “FEOFS2” is output when the WGATE signal is “low (L)”.

The WGATE signal is also used for switching the gain of each of the IV amplifiers 11a to 11d in the optical pickup 2 shown in FIG. The differential amplifier 24 subtracts the circuit offset cancel voltage “FEOFS-E” from the output value of the focus signal operation amplifier 21 and outputs the result.

As described above, as described above, the circuit offset is predominantly generated by each of the IV amplifiers 11a to 11d and the focus signal operation amplifier 21, and by subtracting the circuit offset by the differential amplifier 24, the circuit offset is obtained. Can be almost canceled.

Further, each I of the detector in the optical pickup 2 is
V amplifiers 11a to 11d perform gain switching based on the WGATE signal. However, different circuit offsets occur at the time of high gain and at the time of low gain.

Therefore, when data is reproduced by the DAC 23 (WG
ATE signal = “L”) high gain offset cancel data “FEOFS1” and data recording (WGAT
By selectively inputting the low gain offset cancel data “FEOFS2” for the E signal = “H”), both the circuit offset at the time of the high gain and the circuit offset at the time of the low gain can be canceled.

Similarly, this signal detection circuit 5
A voltage “TEOFS” for the DA converter (DAC) 33 to cancel the circuit offset of the tracking signal.
The selector (SEL) 32 receives two types of offset cancel data “TEOFS1” and “TEOFS2”, selects one of them, and selects D
Input to AC33.

That is, W which becomes "H" during data recording
The GATE signal is input, and “TEOFS1” is output to the DAC 33 when the WGATE signal is “high (H)”, and “TEOFS2” is output when the WGATE signal is “low (L)”.

The differential amplifier 34 subtracts the circuit offset cancel voltage “TEOFS-E” from the output value of the tracking signal operation amplifier 31 and outputs the result. In this manner, as described above, the circuit offset is set at each IV amplifier 1
1a to 11d, the signal generated by the tracking signal operation amplifier 31 is dominant, and the circuit offset can be almost canceled by subtracting the circuit offset by the differential amplifier 34.

Each I of the detector in the optical pickup 2
V amplifiers 11a to 11d perform gain switching based on the WGATE signal. However, different circuit offsets occur at the time of high gain and at the time of low gain.

Therefore, when data is reproduced in the DAC 33 (WG
High gain offset cancel data “TEOFS1” for ATE signal = “L”) and data recording (WGAT
By selectively inputting the low-gain offset cancel data “TEOFS2” for the E signal = “H”), the circuit offset of the tracking signal can be canceled at both the high gain and the low gain.

Further, the sum signal operation amplifier 41 outputs a sum signal of the output values VA to VD from the detector. The sum signal is used to normalize the focus signal and the tracking signal based on this signal, thereby suppressing a signal level fluctuation due to a change in a disk reflectance or a laser power value of the optical disk. Generally, this normalization operation is performed by an AGC (Automatic Gain C
control operation.

In the same manner as described above, the signal detection circuit 5 uses the voltage "SUMOFS" for the DA converter (DAC) 43 to cancel the circuit offset of the sum signal.
The selector (SEL) 42 receives two types of offset cancel data “SUMOFS1” and “SUMOFS2”, selects one of them, and inputs the selected data to the DAC 43.

That is, W which becomes "H" during data recording
When the GATE signal is input and the WGATE signal is “High (H)”, “SUMOFS1” is changed to “Low (L)”.
In this case, "SUMOFS2" is output to the DAC 43.

The differential amplifier 44 is a sum signal operation amplifier 4
The circuit offset cancel voltage “SUM”
OFS-E "is subtracted and output.
As described above, the circuit offset is set for each of the IV amplifiers 11a to 11a.
11d, the signal generated by the sum signal operation amplifier 41 is dominant, and the circuit offset can be almost canceled by subtracting the circuit offset by the differential amplifier 44.

Further, each I of the detector in the optical pickup 2
V amplifiers 11a to 11d perform gain switching based on the WGATE signal. However, different circuit offsets occur at the time of high gain and at the time of low gain.

Therefore, when data is reproduced by the DAC 43 (WG
ATE signal = “L”) high gain offset cancel data “SUMOFS1” and data recording (WGA
By selectively inputting the low gain offset cancel data “SUMOFS2” for the TE signal = “H”),
As for the sum signal, both the circuit offset at the time of high gain and the circuit offset at the time of low gain can be canceled.

Next, the sum signals (ie, the focus signal and the track signal) whose circuit offsets have been canceled by the differential amplifiers 24 and 34 are respectively VCA (Vo).
ltage Controlled Ampe) 25 and 35.

The sum signal whose circuit offset has been canceled by the differential amplifier 44 is sent to the AGC control circuit (A
GCCNT) 45. The AGCCNT 45 decreases the gains of the VCAs 25 and 35 when the sum signal is large, and increases the gains of the VCAs 25 and 35 when the sum signal is small.

With the above operation, the above-mentioned AGC is performed, so that the signal level fluctuation due to the change in the disk reflectivity or the laser power value of the level of the focus signal and the tracking signal can be suppressed.

Further, a DA converter (DAC) 26
Outputs a voltage “FEOFS-O” for canceling the optical offset of the normalized focus signal.
Then, the differential amplifier 27 calculates the optical offset cancel voltage “FEOFS-O” from the normalized focus signal.
Is subtracted and output.

Similarly, a DA converter (DA
C) 36 outputs a voltage “TEOFS-O” for canceling the optical offset of the normalized tracking signal. Then, the differential amplifier 37 calculates the optical offset cancel voltage “TE” from the normalized tracking signal.
OFS-O "is subtracted and output.

As described above, as described above, the optical offset generated in the focus signal and the tracking signal changes in proportion to the signal level input to the photodetector 10, that is, the total signal level. The optical offset of the focus signal and the tracking signal normalized by the sum signal have a constant level.

More specifically, when the disc reflectivity or the laser power value of the optical disc 1 increases, the focus signal level, the tracking signal level, and the optical offset generated in the focus signal and the tracking signal both increase in proportion.

Similarly, since the total signal level also increases, the gain of the VCAs 25 and 35 decreases due to the AGC operation described above. As a result, the normalized focus signal and tracking signal levels can be suppressed to levels before the disc reflectivity of the optical disc 1 and the laser power value are increased. Also, the disk reflectance of the optical disk 1,
The same applies when the laser power value decreases.

As described above, the normalized focus signal from which the optical offset has been canceled is output from the differential amplifier 27, and the normalized tracking signal from which the optical offset has been canceled is output from the differential amplifier 37. You.

That is, the focus signal calculation amplifier 21 and the tracking signal calculation amplifier 31 calculate the servo signal of the focus signal and the tracking signal based on a plurality of output signals from the divided light receiving elements of the optical pickup. Performs the function of the circuit.

The differential amplifiers 24 and 34 function as a first-system offset cancel voltage applying means for applying a first-system offset cancel voltage to the servo signal output from the servo signal operation circuit.

Further, the VCAs 25 and 35, the sum signal operation amplifier 41, the differential amplifier 44, and the AGC control circuit 45
Function as a servo signal normalizing means for normalizing the servo signal after the first system offset canceling voltage applying means has applied the first system offset canceling voltage with the sum signal of the plurality of output signals. .

Furthermore, the differential amplifiers 27 and 37 and the like apply a second system offset cancel voltage applying means to the second system offset cancel voltage to the servo signal normalized by the servo signal normalizing means. Perform the function of

The IV conversion circuits 11a to 11d
Switches between one of two types of gains based on a predetermined switching signal, and converts current signals of a plurality of output signals from the divided light receiving elements into voltage signals based on the switched gains. Performs the function of a voltage conversion circuit.

Further, the selectors 22 and 32, DAC
23 and 33 switch the level of the first system offset cancel voltage applied by the first system offset cancel voltage applying means to one of two types of small system levels based on the predetermined switching signal. The function of the offset cancel voltage level switching means is achieved.

The switching of the type of gain in the current / voltage conversion circuit and the switching of the level type of the small system in the offset cancel voltage level switching means are linked in accordance with the WGATE signal based on the predetermined switching signal. To

Next, an offset cancel sequence in the optical disk drive will be described. This offset cancel sequence is performed by the CPU 8 reading some signal levels in the signal detection circuit 5 under predetermined conditions via the AD converter (ADC) 52 and setting offset cancel data based on the read data. .

The selector 51 outputs a focus signal (FE) and a tracking signal (T
E), one of the focus signal (FEMON), the tracking signal (TEMON), and the sum signal (SUMMON) after the circuit offset cancellation is selected and the ADC is selected.
Input to 52. The data “OFSDAT” after AD conversion by the ADC 52 is input to the CPU 8.

Next, a circuit offset cancel sequence will be described. As described above, the circuit offset occurs constantly even when the laser power is turned off (OFF). Therefore, the circuit offset can be canceled by turning off the laser power, detecting the signal level in the signal detection circuit 5, and setting the offset cancel data.

Next, a circuit offset cancel sequence for the focus signal system will be described. FIG.
7 is a flowchart showing a circuit offset cancel sequence process of a focus signal system in PU8.

The CPU 8 stops the laser drive circuit in step (indicated by "S" in the figure) 1, and turns off the laser power by LD / OFF. Proceeding to step 2, switching is performed so that the selector 51 of the signal detection circuit 5 selects FEMON. As a result, the FEM is output from the ADC 52.
ON AD conversion data is output.

Further, the process proceeds to step 3, where the WGATE signal is set to "L". Thereby, the IV amplifier 1 of the detection circuit
The IV conversion gain by 1a to 11d becomes high,
The offset cancel data “FEOFS1” is input to the DAC 23 of the signal detection circuit 5. And
Proceeding to step 4, the value of "FEOFS1" is changed and adjusted to cancel the circuit offset.

Further, the CPU 8 proceeds to step 5 and sets the WGATE signal to "H". As a result, the IV conversion gain by the IV amplifiers 11 a to 11 d of the detection circuit becomes low, and the offset cancel data “FEOFS2” is input to the DAC 23 of the signal detection circuit 5. Then, the process proceeds to step 6 to change and adjust the value of “FEOFS2” to cancel the circuit offset.

As described above, after the processing of steps 1 to 6 in FIG. 4 is completed, "FEOFS1" is used when the IV amplifiers 11a to 11b of the detection circuit have a high gain and when "FEOFS1"
In FS2 ", offset cancel data when the IV amplifiers 11a to 11b of the detection circuit have a low gain is obtained.

FIG. 5 is a flowchart showing the detailed processing of step 4 in FIG. The CPU 8 determines in step 11
To set an initial value to “FEOFS1.” For example, A
The center value of the data range that can be input to the DC 52 is set.

Proceeding to step 12, the AD conversion data "O
FSDAT ”is read, and it is determined whether or not the absolute value is equal to or smaller than a predetermined value. Since the processing has been completed, the processing ends.

If the absolute value of "OFSDAT" exceeds the predetermined value in the determination in step 12, the process proceeds to step 13 to determine whether "OFSDAT" is positive or negative. Proceed to step 14.

When the process proceeds to step 15, "FEMO"
The level of “N” is a positive level, and “1” is incremented (added) to “FEOFS1.” As a result, the offset cancel voltage “FEOFS-E” increases, and the output value “FEMON” of the differential amplifier 24 increases. And the circuit offset decreases.

When the process proceeds to step 14, "FEMO
The level of “N” is a negative level, and “1” is decremented (subtracted) from “FEOFS1.” As a result, the offset cancel voltage “FEOFS-E” decreases, and the output value “FEMON” of the differential amplifier 24 is reduced. And the circuit offset increases.

After the processing in step S14 or S15, the flow returns to step S12, and while the loop processing in steps S12 to S15 is repeated, "FEFOFS1" such that the level of "FEMON" becomes a predetermined level near "0".
When is set, the process ends.

FIG. 6 is a flowchart showing the detailed processing of step 6 in FIG. The CPU 8 determines in step 21
To set an initial value to "FEOFS2". For example, AD
The center value of the data range that can be input is set in C52.

Proceeding to step 22, the AD conversion data "O
FSDAT ”is read, and it is determined whether or not the absolute value is equal to or smaller than a predetermined value. If the absolute value is equal to or smaller than the predetermined value, the output value“ FEMON ”of the differential amplifier 24 is almost at the“ 0 ”level, and the circuit offset cancellation is performed. Since the processing has been completed, the processing ends.

If the absolute value of "OFSDAT" exceeds the predetermined value in step 22, the process proceeds to step 23 to determine whether "OFSDAT" is positive or negative. Proceed to step 24.

When the process proceeds to step 25, "FEMO
The level of “N” is a positive level, and “1” is incremented (added) to “FEOFS2.” As a result, the offset cancel voltage “FEOFS-E” increases, and the output value “FEMON” of the differential amplifier 34 increases. And the circuit offset decreases.

When the process proceeds to step 24, "FEMO
The level of “N” is a negative level, and “1” is decremented (subtracted) from “FEOFS2.” As a result, the offset cancel voltage “FEOFS-E” decreases, and the output value “FEMON” of the differential amplifier 24 is reduced. And the circuit offset increases.

After the processing of step 24 or step 25, the flow returns to step 22, and while repeating the loop processing of steps 22 to 25, "FEOFS2" such that the level of "FEMON" becomes a predetermined level near "0".
When is set, the process ends.

Next, a circuit offset cancel sequence for the tracking signal system will be described. FIG.
4 is a flowchart showing a circuit offset cancel sequence process of a tracking signal system in the CPU 8;

The CPU executes a step (indicated by “S” in the figure)
At 31, the laser drive circuit is stopped, and the laser power is turned off by LD / OFF. Proceeding to step 32, switching is performed so that the selector 51 of the signal detection circuit 5 selects TEMON. As a result, the TEM is output from the ADC 52.
ON AD conversion data is output.

Further, the routine proceeds to step 33, where the WGATE signal is set to "L". As a result, the IV conversion gain by the IV amplifiers 11a to 11d of the detection circuit becomes high, and the offset cancellation data “TEOFS1” is input to the DAC 33 of the signal detection circuit 5. Then, the process proceeds to step 34 to change and adjust the value of “TEOFS1” to cancel the circuit offset.

Further, the CPU 8 proceeds to step 35 and sets the WGATE signal to "H". As a result, the IV conversion gain by the IV amplifiers 11a to 11d of the detection circuit becomes low, and the offset cancellation data “TEOFS1” is input to the DAC 33 of the signal detection circuit 5. Then, the process proceeds to step 36, where “TEOFS
Adjustment is made by changing the value of 2 "to cancel the circuit offset.

Thus, steps 31 to 3 in FIG.
After the processing of step 6, the “TEOFS1” contains the IV of the detection circuit.
When the amplifiers 11a and 11b have a high gain,
EOFS1 ″ has IV amplifiers 11a to 11b of a detection circuit.
Is low gain, offset cancel data is obtained.

FIG. 8 is a flowchart showing a detailed process of step 34 in FIG. The CPU 8 determines in step 4
In step 1, an initial value is set in “TEOFS1”. For example, A
The center value of the data range that can be input to the DC 52 is set.

Proceeding to step 42, the AD conversion data "O
FSDAT ”is read, and it is determined whether the absolute value is equal to or smaller than a predetermined value. If the absolute value is equal to or smaller than the predetermined value, the output value“ TEMON ”of the differential amplifier 34 is substantially at the“ 0 ”level, and the circuit offset cancellation is performed. Since the processing has been completed, the processing ends.

If the absolute value of "OFSDAT" exceeds the predetermined value in step 42, the flow advances to step 43 to determine whether "OFSDAT" is positive or negative. Proceed to step 44.

When the process proceeds to step 45, "TEMO
The level of “N” is a positive level, and “1” is incremented (added) to “TEOFS1.” As a result, the offset cancel voltage “TEOFS-E” increases, and the output value of the differential amplifier 34 “TEMON” And the circuit offset decreases.

When the process proceeds to step 44, "TEMO
The level of “N” is a negative level, and “1” is decremented (subtracted) from “TEMON.” As a result, the offset cancel voltage “TEOFS-E” decreases, and the output value “TEMON” of the differential amplifier 34 is reduced. Levels increase,
Circuit offset increases.

After the processing of step 44 or step 45, the flow returns to step 42, and while repeating the loop processing of steps 42 to 45, "TEOFS1" such that the level of "TEMON" becomes a predetermined level near "0".
When is set, the process ends.

FIG. 9 is a flowchart showing a detailed process of step 36 in FIG. The CPU 8 determines in step 5
In step 1, an initial value is set in “TEOFS2”. For example, A
The center value of the data range that can be input to the DC 52 is set.

Proceeding to step 52, the AD conversion data "O
FSDAT ”is read, and it is determined whether the absolute value is equal to or smaller than a predetermined value. If the absolute value is equal to or smaller than the predetermined value, the output value“ TEMON ”of the differential amplifier 34 is substantially at the“ 0 ”level, and the circuit offset cancellation is performed. Since the processing has been completed, the processing ends.

If the absolute value of "OFSDAT" exceeds the predetermined value in step 52, the flow advances to step 53 to determine whether "OFSDAT" is positive or negative. Proceed to step 54.

If the process proceeds to step 55, the "TEMO
The level of “N” is a positive level, and “1” is incremented (added) to “TEOFS2.” As a result, the offset cancel voltage “TEOFS-E” increases, and the output value “TEMON” of the differential amplifier 34 is increased. And the circuit offset decreases.

When the process proceeds to step 54, the "TEMO
The level of “N” is a negative level, and “1” is decremented (subtracted) from “TEMON.” As a result, the offset cancel voltage “TEOFS-E” decreases, and the output value “TEMON” of the differential amplifier 34 is reduced. Levels increase,
Circuit offset increases.

After the processing of step 54 or 55, the flow returns to step 52, and while repeating the loop processing of steps 52 to 55, "TEOFS2" such that the level of "TEMON" becomes a predetermined level near "0".
When is set, the process ends.

Next, a circuit offset cancel sequence for the sum signal system in the optical disk drive will be described. FIG. 10 is a flowchart showing the circuit offset cancel sequence processing of the sum signal system in the CPU 8.

In step (indicated by "S" in the figure) 61, the CPU 8 stops the laser drive circuit, and
Turn off the laser power with. Proceeding to step 62, switching is performed so that the selector 51 of the signal detection circuit 5 selects SUMMON. As a result, AD conversion data of SUMMON is output from the ADC 52.

Further, the routine proceeds to step 63, where the WGATE signal is set to "L". As a result, the IV conversion gain by the IV amplifiers 11a to 11d of the detection circuit becomes high, and the offset cancellation data “SUMOFS1” is input to the DAC 43 of the signal detection circuit 5. Then, the process proceeds to step 64 to change and adjust the value of "SUMOFS1" to cancel the circuit offset.

Further, the CPU 8 proceeds to step 65 and sets the WGATE signal to "H". As a result, the IV conversion gain by the IV amplifiers 11a to 11d of the detection circuit becomes low, and the offset cancellation data “SUMOFS2” is input to the DAC 43 of the signal detection circuit 5. Then, the process proceeds to step 66, where "SUMOF"
The value of S2 "is changed and adjusted to cancel the circuit offset.

Thus, steps 61 to 61 in FIG.
After the end of the process at 66, “SUMOFS1” contains the case where the IV amplifiers 11a to 11b of the detection circuit have a high gain, and
"SUMOFS2" includes the IV amplifiers 11a to 11a of the detection circuit.
Offset cancellation data when 11b is a low gain is obtained.

FIG. 11 is a flowchart showing the detailed processing of step 64 in FIG. The CPU 8 sets an initial value to “SUMOFS1” in a step 71. For example, a center value of a data range that can be input to the ADC 52 is set.

Proceeding to a step 72, the AD conversion data "O"
FSDAT ”is read, and it is determined whether or not the absolute value is equal to or smaller than a predetermined value. If the absolute value is equal to or smaller than the predetermined value, the output value“ SUMMON ”of the differential amplifier 44 is almost at“ 0 ”level, and the circuit offset cancellation is performed. Since the processing has been completed, the processing ends.

If the absolute value of "OFSDAT" exceeds the predetermined value in step 72, the flow advances to step 73 to determine whether "OFSDAT" is positive or negative. Proceed to step 74.

When the process proceeds to step 75, the "SUMMO
The level of “N” is a positive level and “SUMOFS1”
Is incremented (added). As a result, the offset cancel voltage “SUMOFS-E” increases, the level of the output value “SUMMON” of the differential amplifier 44 decreases, and the circuit offset decreases.

When the process proceeds to step 74, the "SUMMO
The level of “N” is a negative level and “SUMOFS1”
Is decremented (subtracted) by "1". As a result, the offset cancel voltage “SUMOFS-E” decreases, the level of the output value “SUMMON” of the differential amplifier 44 increases, and the circuit offset increases.

After the processing of step 74 or step 75, the flow returns to step 72, and while repeating the loop processing of steps 72 to 75, "SUMOFS" such that the level of "SUMMON" becomes a predetermined level near "0".
When "1" is set, the processing is terminated.

FIG. 12 is a flowchart showing the detailed processing of step 66 in FIG. The CPU 8 sets an initial value to “SUMOFS2” in step 81. For example, a center value of a data range that can be input to the ADC 52 is set.

Proceeding to a step 82, the AD conversion data "O"
FSDAT ”is read, and it is determined whether or not the absolute value is equal to or smaller than a predetermined value. If the absolute value is equal to or smaller than the predetermined value, the output value“ SUMMON ”of the differential amplifier 44 is almost at“ 0 ”level, and the circuit offset cancellation is performed. Since the processing has been completed, the processing ends.

If the absolute value of "OFSDAT" exceeds the predetermined value in step 82, the flow advances to step 83 to determine whether "OFSDAT" is positive or negative. Proceed to step 84.

When the process proceeds to step 85, the "SUMMO
The level of “N” is a positive level, and “SUMOFS2”
Is incremented (added). As a result, the offset cancel voltage “SUMOFS-E” increases, the level of the output value “SUMMON” of the differential amplifier 44 decreases, and the circuit offset decreases.

If the process proceeds to step 84, the "SUMMO
The level of “N” is a negative level and “SUMOFS2”
Is decremented (subtracted) by "1". As a result, the offset cancel voltage “SUMOFS-E” decreases, the level of the output value “SUMMON” of the differential amplifier 44 increases, and the circuit offset increases.

After the processing in step 84 or step 85, the flow returns to step 82, and while repeating the loop processing in steps 82 to 85, the "SUMMONS" level such that the level of "SUMMON" becomes a predetermined level near "0".
When "2" is set, the processing is terminated.

Next, an optical offset cancel sequence in the optical disk drive will be described.

First, an offset is applied to a focus signal while the focus servo in the optical disk drive is turned on, and an offset cancel process of the focus signal for obtaining an offset value that maximizes the amplitude of the tracking signal is performed. explain.

FIG. 13 is a diagram showing an example of the relationship between the offset amount applied to the focus signal and the amplitude value of the tracking signal. In the case of this example, the focus offset application amount at which the amplitude value of the tracking signal becomes the maximum is F, and this value is used as the optical offset cancel voltage.

FIG. 14 shows the CP of this optical disk drive.
It is a flowchart which shows the circuit offset cancellation sequence process of the sum signal system in U8. CPU8
Turns on the focus servo (FO servo) in step 91. Proceeding to step 92, the selector 51 sets "T
Switching is performed so as to select E ".

In steps 93 to 95, the process is repeated while incrementing N from I = -N to N.
First, in step 93, the value of I is set to "FEOFS3" of the offset cancel data.

At step 94, "OFSDAT" is monitored to detect AD conversion data corresponding to the peak value and the bottom value of the tracking signal. Step 9
5 (peak value−bottom value), that is, the data TE (I) corresponding to the amplitude value of the tracking signal
And memorize them. Then, after repeating steps 93 to 95, the process proceeds to step 96.

In step 96, the maximum value of the stored "2N + 1" pieces of data: TE (I) is detected. Step 9
The process proceeds to step S7, and the value of I at which TE (I) is maximized is set as offset cancel data “FEOFS3”. Then, after the above processing is completed, data for canceling the optical offset of the focus signal is obtained in “FEOFS3”.

Next, an offset is applied to the tracking signal while the focus servo in the optical disk drive is turned on, and the offset of the tracking signal for obtaining the offset whose center value of the amplitude of the tracking signal is closest to “0” is obtained. The cancellation process will be described.

FIG. 15 shows the CP of the optical disk drive.
It is a flowchart which shows the other circuit offset cancellation sequence processing of the sum signal system in U8. CPU
8 turns on the focus servo (FO servo) in step 101. Proceeding to step 102, selector 5
1 so as to select “TE”.

In steps 103 to 105, the process is repeated while incrementing N from I = -N to N. First, in step 103, the value of I is set to "TEOFS3" of the offset cancel data.

Proceeding to step 104, "OFSDAT"
Is monitored, and AD conversion data corresponding to the peak value and the bottom value of the tracking signal is detected. Further, the process proceeds to step 105, where (peak value + bottom value) / 2, that is, data TE (I) corresponding to the center value of the amplitude of the tracking signal is stored in association with I. After repeating steps 103 to 105, the process proceeds to step 106.

In step 106, the stored "2N + 1"
Pieces of data: the minimum value of the absolute value of TE (I), that is,
A value closest to "0" is detected. Proceeding to step 107, the value of I at which | TE (I) | is minimized is set as offset cancel data “TEOFS3”. Then, after the above processing is completed, data for canceling the optical offset of the tracking signal is obtained in “TEOFS3”.

In the signal detection circuit of this optical disk drive, since the circuit offset is subtracted in the subsequent stage of the IV amplifier and the servo signal operation amplifier, the circuit offset which is mainly generated in the IV amplifier and the servo signal operation amplifier is sufficiently canceled. can do.

Further, since the optical offset is subtracted at the subsequent stage of the normalized servo signal, it is necessary to sufficiently cancel the optical offset by a constant offset cancel voltage even if there is a change in the reflectivity of the optical disk or the laser power. Can be.

Further, the IV amplifier has a gain switching function, has offset cancellation data for each gain, and switches the offset cancellation data in conjunction with the gain switching. The offset can be sufficiently canceled.

[0125]

As described above, according to the signal detection circuit of the optical disk drive of the present invention, the circuit offset and the optical offset generated in the servo signal can be appropriately canceled.

[Brief description of the drawings]

FIG. 1 is a diagram showing a detailed internal configuration of a signal detection circuit 5 shown in FIG.

FIG. 2 is a diagram showing a configuration of an optical disk drive according to an embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a detector in the optical pickup 2 shown in FIG.

FIG. 4 is a flowchart showing a circuit offset cancel sequence processing of a focus signal system in a CPU 8 shown in FIG. 1;

FIG. 5 is a flowchart showing a detailed process of step 4 shown in FIG. 4;

6 is a flowchart showing a detailed process of step 6 shown in FIG.

FIG. 7 is a flowchart showing a circuit offset cancel sequence processing of a tracking signal system in the CPU 8 shown in FIG. 1;

FIG. 8 is a flowchart showing a detailed process of step 34 shown in FIG. 7;

FIG. 9 is a flowchart showing a detailed process of step 36 shown in FIG. 7;

FIG. 10 is a flowchart showing a circuit offset cancel sequence process of a sum signal system in the CPU 8 shown in FIG. 1;

FIG. 11 is a flowchart showing a detailed process of step 64 shown in FIG. 10;

12 is a flowchart showing a detailed process of step 66 shown in FIG.

FIG. 13 is a diagram illustrating an example of a relationship between an offset amount applied to a focus signal and an amplitude value of a tracking signal.

FIG. 14 is a flowchart showing a circuit offset cancel sequence processing of a sum signal system in the CPU 8 shown in FIG. 1;

FIG. 15 is a flowchart showing another circuit offset cancel sequence processing of the sum signal system in the CPU 8 shown in FIG. 1;

FIG. 16 is a circuit diagram showing a servo signal calculation unit of a signal detection circuit in a conventional optical disk drive.

[Explanation of symbols]

1: optical disk 2: optical pickup 3: laser drive circuit 4: modulation circuit 5: signal detection circuit 6: demodulation circuit 7: servo circuit 8: CPU 9: spindle motor 10a to 10d: split light receiving element 10: photodetector 11a to 11d: IV amplifiers 21, 61: focus signal operation amplifiers 22, 32, 42, 51: selectors (SEL) 23, 26, 33, 36, 43, 62, 72: DACs 24, 27, 34, 37, 44, 63, 73 : Differential amplifier 25, 35: VCA 31, 71: Tracking signal operation amplifier 45: AGC control circuit (AGCCNT) 52: AD converter (ADC)

Claims (2)

[Claims] A servo signal calculating circuit for calculating a servo signal of a focus signal and a tracking signal based on a plurality of output signals from the divided light receiving elements of the optical pickup; and a servo signal output from the servo signal calculating circuit. 1
First system offset cancel voltage applying means for applying the offset cancel voltage of the first system, and normalizing the servo signal after the first system offset cancel voltage is applied by the means with the sum signal of the plurality of output signals An optical disc drive, comprising: a servo signal normalizing means for performing the operation; and a second system offset canceling voltage applying means for applying a second system offset canceling voltage to the servo signal normalized by the means. The signal detection circuit of the device. 2. The signal detecting circuit according to claim 1, wherein the divided light receiving element is switched to one of two kinds of gains based on a predetermined switching signal, and the divided light receiving element is switched based on the switched gain. And a current-to-voltage conversion circuit for converting current signals of a plurality of output signals from each of the plurality of output signals into a voltage signal; And an offset canceling voltage level switching means for switching to one of two types of levels of the small system based on the predetermined switching signal. The switching of the level type of the small system by the level switching means is linked. A signal detection circuit for an optical disk drive, characterized by: