JP2000009861A - Time-division multiple timer and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely monitor the time lapse without increasing the scale of a device even if the number of time monitoring to be processed simultaneously increases by providing a second storage means for storing a calculation value when the output of an addition means overflows. SOLUTION: The data port of a memory 40 is connected to the data port of an adder 50 and a data register 60. The adder 50 reads a memory data signal DMD at an address indicated by a memory address signal DMA from the memory 40 and adds '2' to it for holding. Input and output data controlled by a processor 70 are held by the data register 60. A detection machine 80 inputs an overflow signal outputted by the adder 50 as a timer end signal STE and outputs a read timing signal SRd. An FIFO 90 internally holds a counter address signal DCA when the read timing signal Srd is inputted by fast-in/fast-out operation and outputs a flag signal Frg.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a time division multiplex timer for executing a plurality of time lapse monitoring processes in one apparatus and a method of controlling the time division multiplex timer.

[0002]

2. Description of the Related Art Japanese Patent Laid-Open Publication No. Sho 63-214803 discloses a method for monitoring the lapse of time of changes for a plurality of signals. In this publication, the processor controls a plurality of independent timers by multiplexing the reading and writing of data by the processor and the counting of the timer.

[0003]

The processor sets a timer value at a data write timing, and the set timer value is added at a timer count timing, and is cleared when an overflow occurs.

[0004] Therefore, in order to detect the expiration of the timer, the processor must keep monitoring whether the timer values set for all the operating timers have been cleared. For this reason, in the related art, there has been a problem that the number of timers that can be operated simultaneously is limited according to the processing capability of the processor.

[0005] The present invention has been made under such a background, and even if the number of time monitors to be simultaneously processed increases, time division can be reliably monitored without increasing the scale of the apparatus. It is an object of the present invention to provide a control method for a multiplex timer and a time division multiplex timer.

[0006]

In order to solve the above-mentioned problems, according to the first aspect of the present invention, there is provided a counting means for counting a clock serving as a reference for time measurement, and a counting value by the counting means. Any one of a plurality of timing values based on
Selection signal generating means for outputting a selection signal for selecting one;
Control means for monitoring the plurality of time values; first storage means for storing the plurality of time values; and a first address based on the control address, the count value, and the selection signal output by the control means. Selecting means for selecting an address corresponding to any one of the plurality of clock values in the storage means, and adding means for adding a predetermined number to each of the plurality of clock values;
Holding means for holding the control data output by the control means and the addition result by the adding means; and a second means for storing the count value when the output of the adding means overflows.
Storage means. According to a second aspect of the present invention, in the time division multiplex timer of the first aspect, the second storage means inputs and outputs data in a first-in first-out operation. In the invention according to claim 3, the time division multiplexing timer according to claim 1 or 2 detects an overflow of the adding means and stores the overflow in the second storage means. It is characterized by comprising detecting means for reading the count value. According to a fourth aspect of the present invention, in the time division multiplex timer according to any one of the first to third aspects, the adding means is selected by the selecting means in the first storage means. The time value corresponding to any one of the plurality of time values thus read is read out, added with 2, and written to the address. In the invention according to claim 5,
In the time division multiplex timer according to any one of claims 1 to 4, the control unit determines which of the plurality of time count values is based on the count value stored in the second storage unit. It is characterized in that it is determined whether or not a predetermined time has passed.
In the invention according to claim 6, a clock serving as a reference for time measurement is counted by the counting means, and one of a plurality of time values is selected based on the count value by the counting means. The selection signal to be output is output by the selection signal generation means, the plurality of time values are stored by the first storage means, and the first time is calculated based on the control address, the count value, and the selection signal output by the control means. A method of controlling a time division multiplexing timer, wherein an address corresponding to any one of the plurality of clock values in a storage unit is selected by a selection unit, and a predetermined number is added to each of the plurality of clock values by an addition unit. Storing the count value when the output of the adding means overflows in a second storage means for inputting / outputting data in a first-in first-out operation; and storing the count value stored in the second storage means Any of the plurality of timing values based is characterized in that to determine exceeds a predetermined time.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 shows a counter 10 in FIG. 1, which divides an input clock pulse _PCK and outputs it. Reference numeral 20 denotes a selection signal generation circuit, which is a counter 1
And outputs a selection signal S _EL based on 0 is divided outputs of the counter address signal D _CA.

Reference numeral 30 denotes a selector, which is a processor address signal D which is a control address output from the processor 70.
_PA and the counter address signal D _CA described above is input, by selecting the time division by the selection signal S _EL these signals and outputs the memory address signal D _MA.

Reference numeral 40 denotes a memory, which is provided with output data (processor data signal D _PD ) temporarily stored in a data register 60 described later by the processor 70 and an adder 50 described later.
And the memory data signal _DMD , which is the calculation result of

The adder 50 adds "2" to the operation result stored in the memory 40, erases the timer value when an overflow occurs, and supplies the operation result to the memory 40.

The data register 60 holds input data and output data (processor data signal D _PD ) controlled by the processor 70. 80 is a detector receives the overflow signal from the adder 50 is output as a timer end signal S _TE, and outputs a read timing signal S _Rd.

Reference numeral 90 denotes a FIFO (First-In First-Out).
a memory), a counter address signal D _CA when the read timing signal S _Rd is inputted, held inside a first-in, first-out operation, and outputs a flag signal F _rg.

The operation of this embodiment will be described below. Here, the counter address signal _DCA and the processor address signal _DPA are described as two bits, but the present invention may be applied to other bits.

[0014] counter 10 is supplied with the clock pulse P _CK, generates the counter address signal D _CA that changes at this time. This counter address signal D _CA
Is input to the selection signal generation circuit 20, and the selection signal generation circuit 20 outputs the selection signal _SEL based on the value of the counter address signal _DCA .

[0015] In this embodiment, as shown in FIG. 2, the value of the counter address signal D _CA is (for each input of the clock pulse P _CK) 0,1,2,3,0 in the order of ... This is repeated (see FIG. 2A).

[0016] On the other hand the selection signal S _EL is repeatedly output one of the values of the counter address signal D _CA as one cycle (see FIG. 2 (b)), counter address signal D _CA and multiplexes the processor address signal D _PD It is used when converting.

The selector 30 has a counter address signal D
Multiplexes based the _CA and the processor address signal D _PA to the selection signal S _EL, and outputs a memory address signal D _MA (see FIG. 2 (c)).

As shown in FIG. 1, the data port of the memory 40 is connected to the adder 50 and the data port of the data register 60. The adder 50 reads the memory data signal _DMD at the address indicated by the memory address signal _DMA from the memory 40 during the period A shown in FIG.

On the other hand, the adder 50 writes the calculated memory data signal _DMD to an address of the memory 40 indicated by the memory address signal _DMA in a period B shown in FIG.

The above operation is performed by the counter address signal _DCA.
Is repeated for every change. If the operation result overflows during this repetition, the adder 50 outputs a timer end signal _STE .

The detector 80 monitors the timer end signal S _TE, and the timer end signal S _TE is detected, supplies the read timing signal S _Rd to FIFO 90 (see FIG. 2 (e)).

The read timing signal S _Rd is inputted FIFO90 holds reads the counter address signal D _CA at the leading edge of the timing signal S _Rd, and outputs a flag signal F _rg to the processor 70 (FIG. 2
(F)).

When the flag signal F _rg is inputted as an interrupt signal, the processor 70 receives the flag signal C _rg during a period C shown in FIG.
In, it reads the counter address D _CA of the head which is held in FIFO90 as processor data signal D _PD.

[0024] While repeating such operation, for example be counter address signal D _CA is completed is continuously all timers 0,1,2 and 3, FIFO 90 holds the total counter address in a first-in first-out operation.

[0025]

As described above, according to the present invention, a clock serving as a reference for time measurement is counted by the counting means, and any one of the plurality of time values is counted based on the count value by the counting means. Is output by the selection signal generation means, a plurality of time values are stored by the first storage means, and the first storage means is provided based on the control address, the count value, and the selection signal output by the control means. A time-division multiplexing timer control method in which an address corresponding to any one of the plurality of clock values is selected by the selection means, and a predetermined number is added to each of the plurality of clock values by the addition means.
The count value when the output of the adding means overflows is stored in the second storage means for inputting / outputting data in a first-in first-out operation, and based on the count value stored in the second storage means, a plurality of time count values are stored. A time-division multiplexing timer and a time-division multiplexing timer that can reliably monitor the elapse of time without increasing the scale of the device even if the number of time monitors to be processed simultaneously increases because it is determined which has exceeded the predetermined time. The control method described above can be realized.

That is, according to the present invention, the load on the processor is reduced by monitoring all the operating timers, which has been performed by the conventional processor, by the detector and the FIFO. Therefore, the number of simultaneously operable timers is not limited by the processing capability of the processor.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a time division multiplex timer according to an embodiment of the present invention.

FIG. 2 is a timing chart showing a state of a signal in each section of the embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Counter (counting means) 20 Selection signal generation circuit (selection signal generation means) 30 Selector (selection means) 40 Memory (first storage means) 50 Adder (addition means) 60 Data register (holding means) 70 Processor (control) Means) 80 detector (detection means) 90 FIFO (second storage means) _DCA counter address signal (count value) _DMA memory address signal (address) _DMD memory data signal (addition result) _DPA processor address signal ( Control address) _DPD processor data signal (control data) F _rg flag signal P _CK clock pulse (clock) S _EL select signal (select signal) S _TE timer end signal

Claims (6)

[Claims] 1. A clock (P _CK ) serving as a reference for time measurement
Counting means (10) for counting the count, and selection signal generating means for outputting a selection signal (S _EL ) for selecting any one of a plurality of time values based on the count value (D _CA ) by the counting means. (20), control means (70) for monitoring the plurality of time values, and first storage means (40) for storing the plurality of time values.
And an address (D _MA) corresponding to any one of the plurality of clock values in the first storage means based on the control address (D _PA ) output from the control means, the count value, and the selection signal. ), Adding means (50) for adding a predetermined number to each of the plurality of time values, control data (D _PD ) output by the control means, and an addition result by the adding means (D _MD ) and holding means (6
0), and a second storage means (90) for storing the count value when the output of the adding means overflows. 2. The time division multiplex timer according to claim 1, wherein said second storage means inputs and outputs data in a first-in first-out operation. 3. The apparatus according to claim 1, further comprising a detecting means for detecting an overflow of said adding means and reading said count value into said second storage means. 2. The time-division multiplex timer according to 1. 4. The adding means reads a time value corresponding to any one of the plurality of time values selected by the selecting means in the first storage means and adds 2 to the time value. 4. The time-division multiplex timer according to claim 1, wherein the address is written to the address. 5. The control device according to claim 1, wherein the control unit determines which of the plurality of time values has exceeded a predetermined time based on the count value stored in the second storage unit. The time division multiplex timer according to any one of claims 1 to 4. 6. A clock as a reference for time measurement is counted by a counting means, and a selection signal for selecting any one of a plurality of time values based on the count value by the counting means is selected by a selection signal generating means. Outputting the plurality of timekeeping values by a first storage means, and calculating the plurality of timekeeping values in the first storage means based on the control address, the count value, and the selection signal output by the control means. Any one
A time division multiplex timer for selecting an address corresponding to one of the plurality of clock values and adding a predetermined number to each of the plurality of clock values by an adding means, wherein the output of the adding means overflows. A count value is stored in a second storage unit that inputs and outputs data in a first-in first-out operation, and which of the plurality of time count values exceeds a predetermined time based on the count value stored in the second storage unit A method for controlling a time division multiplex timer.