JP2000005151A - Reader - Google Patents

Abstract

(57) [Problem] To provide a pattern reading device which can be easily miniaturized, and has high reproducibility and reliability. A detection electrode panel includes a plurality of selection lines.
b and the data line 21c are wired so as to cross each other, and the detection electrodes 21a are arranged in a two-dimensional array near each crossing point. When a fingerprint is placed on the panel 21, the potential of the detection electrode differs between when the convex portion touches the detection electrode 21a and when the concave portion faces the detection electrode 21a. When a selection signal is sequentially applied to the selection line 21b, the above potential is detected by the detection circuit 21d and can be read out via the data line 21c. In this device, the circuits of the main part can be integrated into an LSI on the same substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a reading device for reading a surface pattern of an object to be read having a surface pattern including a plurality of conductive portions such as fingerprints and a non-conductive portion.

[0002]

2. Description of the Related Art Conventionally, the above-mentioned reading apparatus is roughly classified into an optical system and a capacitance system by physical contact. The optical reading device is designed to optically capture a reflection image of a pattern such as a fingerprint by an imaging device, for example, a CCD digital camera. Further, the capacitance type reading device reads a difference between a sensor and a distance due to, for example, unevenness of a fingerprint as capacitance.

[0003]

However, in order to obtain a reflected image, an optical system for illuminating a fingerprint and an optical system for forming the reflected image on an image pickup device are indispensable for the optical reading device. Therefore, it is difficult to reduce the size of the device, and the overall structure is complicated and expensive.

On the other hand, the reading device of the capacitance type has a problem that it is susceptible to noise and lacks reproducibility and reliability because the sensor system has a high impedance in principle.

An object of the present invention is to provide a reading apparatus which can be easily reduced in size, has a simple structure, is inexpensive, and has high reproducibility and reliability by adopting a method different from the above-mentioned conventional method. .

[0006]

In order to achieve the above object, the present invention is a reading apparatus for reading a pattern of an object to be read having a conductive region and a non-conductive region, wherein the reading device is arranged in a two-dimensional array. A plurality of detection electrodes; a plurality of detection circuits connected to each of the detection electrodes; a plurality of selection lines connected to respective inputs of the detection circuits; and a plurality of selection lines connected to respective outputs of the detection circuits. Driving means for applying a predetermined selection signal to each of the detection circuits through each of the data lines, and a detection signal output from each of the detection circuits in response to the selection signal. And an output unit that takes out the data via the.

In the device of the present invention, the detection circuit includes:
It can be composed of a pull-up resistor connected to the detection electrode and a selection transistor connected between the detection electrode, the selection line and the data line.

In the detection circuit having the above configuration, a resistance load type inverter may be connected between the detection electrode and the selection transistor.

Alternatively, an E / D configuration type inverter connected between the detection electrode and the selection transistor may be provided.

Alternatively, an E / E configuration type inverter connected between the detection electrode and the selection transistor may be provided.

Alternatively, a CMOS inverter connected between the detection electrode and the selection transistor may be provided.

Alternatively, the selection line has two phases, a normal phase and a negative phase.
The book comprises a pair of select lines, between which a positive-phase select transistor and a negative-phase select transistor are connected, and a CMOS inverter is connected between the select transistors and the pull-up resistor. May be performed.

Further, in the fingerprint reader to which the present invention is applied, the detection electrodes are arranged at a pitch corresponding to the pitch of the fingerprint.

[0014]

FIG. 1 shows an embodiment of a reading apparatus according to the present invention. In the figure, 20 is a detection electrode panel, 22 is a scanning unit, 23 is an output unit, 24 is a standard pattern memory unit, 25 is a collating unit, and 26 is a determining unit. In the detection electrode panel 20, detection units 21 having detection electrodes 21a and detection circuits 21d are arranged in a matrix.

More specifically, on one surface of the detection electrode panel, a plurality of conductive detection electrodes 21a are arranged in a two-dimensional array at a predetermined pitch.
A plurality of select lines 21b mutually insulated corresponding to 1a
And the data lines 21c are wired so as to intersect in a grid pattern,
A detection circuit 21d is connected between each detection electrode 21a, the selection line 21b, and the data line 21c. This reading device reads, for example, a fingerprint pattern of a finger. The detection electrodes 21a are arranged at a pitch equal to or less than the pitch of the fingerprint, for example, at a pitch of 50 to 200 μm, in a row direction and a column direction. Are arranged.

As shown in FIG. 2, for example, when the finger 27 of the subject is placed on the detection electrode panel 21, the pattern of the concave and convex portions of the fingerprint covers the array of the detection electrodes 21a, Is in contact with the detection electrode 21a.
That is, the detection electrode 21a whose concave portion faces the ground potential has a potential which is pulled up from the ground potential.

Therefore, if the scanning unit 2 sequentially scans the selection lines 21b by sequentially applying the selection signal to each of the selection lines 21b, in response to the selection signal,
A high or low level (1 or 0) data signal is output from the detection circuit 21d depending on whether the convex portion is in contact with the detection electrode 21a or the concave portion is facing the detection electrode 21a, and is output via the data line 21c. Can be taken out.

By scanning the selection line 21b in this manner, a data signal corresponding to the concavo-convex pattern of the fingerprint is obtained from the output unit 23. The standard pattern memory 24 stores fingerprint image signals corresponding to fingerprints of a plurality of specific persons in advance as standard pattern signals. The collation unit 25 collates the data signal with standard pattern signals sequentially called from the standard pattern memory 24, and outputs each collation signal obtained as a result to the determination unit 26. Based on each collation signal from the collation unit 25, the determination unit 26 determines whether or not the fingerprint image signal corresponding to the output signal from the output unit 23 at that time is a specific person stored in the standard pattern memory 24 in advance. Judge,
Outputs a judgment signal.

FIGS. 3 to 25 show one detection electrode 21a.
And each detection unit 21 comprising a detection circuit 21d corresponding thereto
Is shown below. In these figures, 1 is a data line, 2 is a power supply line V _DD , and 3 is a ground line (FIGS.
3), 4 is a selection line (high-level H selection), 5 is a selection line (low-level L selection) (FIGS. 21 to 25), 6 is an N-channel (ch) selection transistor, and 7 is a P-channel selection transistor (FIG. 21 to 25), 8 is a P-channel load transistor (FIGS. 17 to 25), 9 is an N-channel drive transistor (FIGS. 5 to 25), 10 is a pull-up resistor, 11 is a detection electrode, 12 is a substrate, 13 is a load resistance (FIGS. 5 to 8), 14 is an N-channel depletion type load transistor (FIGS. 9 to 12), and 15 is an N-channel enhancement type load transistor (FIGS. 13 to 1).
6) and 16 are gate drivers, and 17 is a sense amplifier unit. The gate driver 16 is connected between each select line 4 and the scanning unit 22, and the sense amplifier unit 17 is connected to the data line 1.
And the output unit 23.

First, the reading operation common to the above-described detection circuits will be described. If the human body is discharged to the ground potential in advance, and the detection electrode is pulled up to a predetermined potential by a pull-up resistor, the protrusion of the fingerprint comes into contact with the detection electrode, thereby causing the detection electrode to be pulled up. The potential drops to the ground potential. However, since the contact does not occur when the concave portion of the fingerprint faces the detection electrode, the detection electrode remains at the predetermined potential. Therefore, as described above, if these detection electrodes arranged in a two-dimensional array are connected to a selection transistor and a selection signal is applied to a selection line and scanning is performed, the potential (H or L) of the detection electrode is obtained. , A pattern signal corresponding to the fingerprint can be obtained.

FIG. 3 shows a detection circuit having the simplest structure. A pull-up resistor 10 is connected between the detection electrode 11 and the power supply line V _DD2, and the gate of the N-channel selection transistor 6 is connected to the selection line, and its drain and source are connected. Are connected to the detection electrode 11 and the data line 1, respectively.

When the convex portion of the fingerprint contacts the detection electrode 11,
The detection electrode 11 is at a human body potential, that is, a ground potential. On the other hand, when the concave portion of the fingerprint faces the detection electrode 11, the detection electrode 11 keeps being pulled up by the resistor 10 and remains at the power supply potential. At this time, when a selection signal is applied from the gate driver 16 to the N-channel selection transistor 6 via the selection line 4 to select the N-channel selection transistor 6, that is, when the selection line 4 is set to a high level, the transistor 6 operates and the detection electrode 11 The potential is transmitted to the data line 1, detected and amplified by the sense amplifier unit 17, and taken out. Therefore, by scanning each selection line, data of a pattern corresponding to a fingerprint can be obtained from each data line.

FIG. 4 shows that the power supply line 2 is provided by disposing the pull-up resistor 10 of FIG.
Is unnecessary, and the detection circuit is further simplified.

FIGS. 5 to 8 show modifications of the detection circuit of FIG. In FIG. 5, a resistance load type inverter composed of an N channel drive transistor 9 and a load resistor 13 is connected between the detection electrode 11 and the N channel selection transistor 6, and the potential of the detection electrode 11 is set to the resistance load type inverter. Is subjected to amplification impedance conversion. That is,
When the concave portion of the fingerprint faces the detection electrode 11, the N-channel drive transistor 9 operates, and the N-channel drive transistor 9 has a low impedance.
3, a low-level potential is output via the N-channel selection transistor 6. Further, when the convex portion of the fingerprint faces the detection electrode 11, the N-channel drive transistor 9 does not operate and the impedance is high, so that a high-level potential is output, and fingerprint data can be obtained in the same manner as described above. it can.

FIG. 6 is different from FIG. 5 only in that the pull-up resistor 10 is connected to the selection line 4, and the other configuration and operation are the same as those in FIG.

FIG. 7 is different from FIG. 5 only in that the load resistor 13 is connected to the selection line 4.

FIG. 8 shows a pull-up resistor 10 and a load resistor 1
5 is connected to the selection line, and the power line 2 is unnecessary.
The only difference is.

The load resistor 13 in FIGS. 5 to 8 can be replaced by a transistor. FIGS. 9 to 12 show an example in which the load resistor 13 of FIGS. 5 to 8 is replaced with an N-channel depletion type load transistor 14. In this case, the N-channel drive transistor 9 is an enhancement type to constitute an E / D inverter. The operation of the detection unit in FIGS. 9 and 10 is the same as in FIGS.

FIG. 10 is different from FIG. 9 only in that the pull-up resistor 10 is connected to the selection line 4.
Is an N-channel depletion type load transistor 14
9 is different from FIG. 9 only in that the drain of the pull-up resistor 10 and the drain of the N-channel depletion type load transistor 14 are connected to the selection line 4. Just do it.

Each of the N-channel depletion type load transistors 14 in FIGS.
This constitutes a type inverter. The operation of the detection unit in FIGS. 13 to 16 is the same as that in FIGS.

FIG. 14 is different from FIG. 13 only in that the pull-up resistor 10 is connected to the selection line 4.
5 is that the gate and the drain of the N-channel enhancement type load transistor 15 are connected to the selection line 4 in FIG.
3 is different from the pull-up resistor 10 shown in FIG.
The point that the gate and the drain of the N-channel enhancement type load transistor 15 are connected to the selection line 4 is shown in FIG.
3 only.

FIGS. 17 to 20 show the N-channel depletion type load transistor 14 or 15 in FIGS. 9 to 12 or 13 to 16 as the P-channel type load transistor 8, the N-channel driving transistor 9 and the P-channel load transistor. 8, a CMOS inverter is constructed. The operation of the detection unit in FIGS. 17 to 20 is the same as that in FIGS. 9 to 12 or FIGS. 13 to 16, respectively.

FIG. 18 differs from FIG. 17 only in that the pull-up resistor 10 is connected to the selection line 4.
FIG. 19 is different from FIG. 17 only in that the drain of the P-channel load transistor 8 is connected to the selection line 4. FIG. 20 is a diagram in which the pull-up resistor 10 and the drain of the P-channel load transistor 8 are connected to the selection line 4. The only difference from FIG. 17 is that the power supply line 2 is not required.

FIGS. 21 to 24 show still another modification of the detection circuit of FIG. In FIG. 21, in addition to the positive-phase selection line 4, a negative-phase selection line 5 is provided, and the selection line 5 is connected to the gate of a P-channel selection transistor 7 that operates in reverse phase. Further, a CMOS inverter composed of an N-channel drive transistor 9 and a P-channel load transistor 8 is connected between these transistors and the detection electrode 11. The potential of the detection electrode 11 is amplified and impedance-converted by the CMOS inverter. At this time, a positive state selection signal is applied to the N-channel selection transistor 6 for selection, that is, the selection line 4 is set to a high level, and a negative-phase selection signal is applied to the P-channel selection transistor 7 for selection. When the selection line 5 is set to a low level, the potential of the detection electrode is transmitted to the data line 1 by operating the transistors 6 and 7. In other words, if the concave portion of the fingerprint corresponds to the detection electrode 11, the N-channel drive transistor 9 operates and the P-channel load transistor does not operate, so that the low-level potential changes to the N-channel selection transistor 6 and the P-channel selection transistor 7 Is output to the data line 1 via the. Also, if the convex portion of the fingerprint corresponds to the detection electrode 11, the P-channel load transistor operates and the N-channel drive transistor does not operate, so that the high-level potential changes to the N-channel selection transistor 6 and the P-channel selection transistor 7 Is output to the data line 1 via the.

FIG. 22 is different from FIG. 21 only in that the pull-up resistor 10 is connected to the selection line 4.

FIG. 23 shows a P-channel load transistor 8
21 is different from FIG. 21 only in that the source of FIG.

FIG. 24 differs from FIGS. 21 to 23 in that the power supply line V _DD 2 and the ground line 3 are not required by connecting the pull-up resistor 10 and the source of the P-channel load transistor 8 to the selection line 4. There is a feature that the operation reliability is ensured and the configuration is extremely simple.

In the above-described embodiment, the gate driver 16 and the sense amplifier section 17 are formed by an LSI external to the substrate 12 on which the detection electrode panel is formed. As shown in FIG. The IC, the control logic 18 and the like may be formed on the same substrate 12 as an integrated electronic device. This integrated electronic device is made up of LSI technology represented by so-called single-crystal silicon, high-temperature polysilicon TFT, low-temperature polysilicon TFT.
It can be easily realized by technology.

Further, the reading apparatus of the present invention can be used for reading not only an uneven pattern such as a fingerprint but also a pattern composed of a wide range of conductive portions and non-conductive portions.

[0040]

As described above, according to the present invention, the conductive pattern on the surface of the object to be read can be electrically read by an electronic circuit when the object to be read contacts the detection electrode.
The entire structure can be easily configured to be small and inexpensive, and the reliability and reproducibility are significantly improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a reading device of the present invention.

FIG. 2 is a plan view of a main part of the embodiment.

FIG. 3 is a schematic diagram illustrating a configuration example of a detection circuit of the embodiment.

FIG. 4 is a schematic diagram showing another configuration example of the detection circuit.

FIG. 5 is a schematic diagram illustrating another configuration example of the detection circuit.

FIG. 6 is a schematic diagram illustrating another configuration example of the detection circuit.

FIG. 7 is a schematic diagram showing another configuration example of the detection circuit.

FIG. 8 is a schematic diagram illustrating another configuration example of the detection circuit.

FIG. 9 is a schematic diagram illustrating another configuration example of the detection circuit.

FIG. 10 is a schematic diagram showing another configuration example of the detection circuit.

FIG. 11 is a schematic diagram showing another configuration example of the detection circuit.

FIG. 12 is a schematic diagram showing another configuration example of the detection circuit.

FIG. 13 is a schematic diagram illustrating another configuration example of the detection circuit.

FIG. 14 is a schematic diagram showing another configuration example of the detection circuit.

FIG. 15 is a schematic diagram showing another configuration example of the detection circuit.

FIG. 16 is a schematic diagram showing another configuration example of the detection circuit.

FIG. 17 is a schematic diagram showing another configuration example of the detection circuit.

FIG. 18 is a schematic diagram showing another configuration example of the detection circuit.

FIG. 19 is a schematic diagram showing another configuration example of the detection circuit.

FIG. 20 is a schematic diagram showing another configuration example of the detection circuit.

FIG. 21 is a schematic diagram illustrating another configuration example of the detection circuit.

FIG. 22 is a schematic diagram showing another configuration example of the detection circuit.

FIG. 23 is a schematic diagram showing another configuration example of the detection circuit.

FIG. 24 is a schematic diagram showing another configuration example of the detection circuit.

FIG. 25 is a schematic diagram showing another configuration example of the detection circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 21 Detection electrode panel 22 Scanning part 23 Output part 24 Standard pattern memory part 25 Collation part 26 Judgment part 21 Detection part 21a Detection electrode 21b Selection line 21c Data line 21d Detection circuit

Claims (8)

[Claims] 1. A reading device for reading a pattern of an object to be read having a conductive region and a non-conductive region, comprising: a plurality of detection electrodes arranged in a two-dimensional array; and a plurality of detection electrodes connected to each of the detection electrodes. A plurality of detection circuits; a plurality of selection lines connected to respective inputs of the detection circuit; a plurality of data lines connected to respective outputs of the detection circuits; Driving means for applying a predetermined selection signal to the detection circuit; output means for taking out a detection signal output from each of the detection circuits in response to the selection signal via the data line;
A reading device comprising: 2. The detection circuit according to claim 1, wherein the detection circuit includes a pull-up resistor connected to the detection electrode, and a selection transistor connected between the detection electrode, a selection line, and a data line. Reading device. 3. The reading device according to claim 2, further comprising a resistance load type inverter connected between the detection electrode and the selection transistor. 4. The reading device according to claim 2, further comprising an E / D configuration type inverter connected between the detection electrode and the selection transistor. 5. The reader according to claim 2, further comprising an E / E configuration type inverter connected between the detection electrode and the selection transistor. 6. The reading device according to claim 2, further comprising a CMOS inverter connected between the detection electrode and the selection transistor. 7. The selection line is one of two phases: a normal phase and a negative phase.
A pair of selection lines are connected between the pair of selection lines, a positive-phase operation selection transistor and a reverse-phase operation selection transistor, and a capacitor C is connected between these selection transistors and the pull-up resistor.
3. The reading device according to claim 2, wherein a MOS inverter is connected. 8. The reader according to claim 1, wherein the detection electrodes are arranged at a pitch corresponding to a pitch of a fingerprint.