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JP2000004010A - Manufacture of capacitor elements - Google Patents

Manufacture of capacitor elements

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Publication number
JP2000004010A
JP2000004010A JP11122299A JP12229999A JP2000004010A JP 2000004010 A JP2000004010 A JP 2000004010A JP 11122299 A JP11122299 A JP 11122299A JP 12229999 A JP12229999 A JP 12229999A JP 2000004010 A JP2000004010 A JP 2000004010A
Authority
JP
Japan
Prior art keywords
capacitive element
mask
capacitor
manufacturing
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11122299A
Other languages
Japanese (ja)
Inventor
Yoshihisa Nagano
能久 長野
Yasuhiro Shimada
恭博 嶋田
Eiji Fujii
英治 藤井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP11122299A priority Critical patent/JP2000004010A/en
Publication of JP2000004010A publication Critical patent/JP2000004010A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing capacitor elements, whereby an etching space without sidewall residues is realized to manufacture capacitor elements superior in reliability at high yield in dry etching of a capacitive insulation film and electrode material for forming the capacitor elements, with a capacitive insulation film using a high dielectric or ferroelectric. SOLUTION: Capacitor element electrodes or capacitive insulation film 2 and mask 3 are formed on a support substrate 1, the capacitor element electrodes or the capacitive insulation film 2 is dry-etched and are cleaned to remove reaction products deposited to the sidewalls of the mask 3 after etching without exposing to the open air, and the mask 3 is removed. The atmosphere for the cleaning is an inert gas such as H, Ar, He, etc., and the soln. for the cleaning is pref. a soln. contg. at least one selected from among water, hydrochloric acid, nitric acid, fluoric acid and org. solvents.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、高誘電率を有する
誘電体または強誘電体を容量絶縁膜とする電気的容量素
子の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an electric capacitor using a dielectric or ferroelectric having a high dielectric constant as a capacitor insulating film.

【0002】[0002]

【従来の技術】近年マイクロコンピュータ等の高速化、
低消費電力化の傾向が推進される中で民生用電子機器が
一段と高度化し、使用される半導体装置もその半導体素
子の微細化が急速に進んできている。それに伴って電子
機器から発生される電磁波雑音である不要輻射が大きな
問題になっており、この不要輻射低減対策として高誘電
率を有する誘電体(以下単に高誘電体という)を容量絶
縁膜とする大容量の容量素子を半導体集積回路装置等に
内蔵する技術が注目をあびている。また、ダイナミック
RAM(DRAM)の高集積化に伴い、従来の珪素酸化
物または窒化物の代わりに高誘電体を容量絶縁膜として
用いる技術が広く研究されている。さらに従来にない低
動作電圧かつ高速書き込み読み出し可能な不揮発性RA
Mの実用化を目指し、自発分極特性を有する強誘電体膜
に関する研究開発が盛んに行われている。
2. Description of the Related Art In recent years, the speed of microcomputers and the like has been increased,
As the trend toward lower power consumption is promoted, consumer electronic devices are becoming more sophisticated, and semiconductor devices used are also being miniaturized. As a result, unnecessary radiation, which is electromagnetic wave noise generated from electronic equipment, has become a major problem. As a measure to reduce this unnecessary radiation, a dielectric having a high dielectric constant (hereinafter simply referred to as a high dielectric) is used as a capacitive insulating film. Attention has been paid to a technology for incorporating a large-capacity capacitive element in a semiconductor integrated circuit device or the like. Also, with the high integration of dynamic RAMs (DRAMs), techniques for using a high dielectric as a capacitor insulating film instead of the conventional silicon oxide or nitride have been widely studied. Furthermore, a non-conventional low-operating voltage and non-volatile
Research and development on ferroelectric films having spontaneous polarization characteristics have been actively conducted with the aim of commercializing M.

【0003】以下従来の半導体装置の製造方法につい
て、図面を参照しながら説明する。図6(a)〜(c)
は従来の容量素子の製造方法を示す工程断面図であり、
1は半導体等の支持基板、2は容量素子用電極または高
誘電体や強誘電体で構成された容量絶縁膜、3は光硬化
性樹脂等のマスク、4はドライエッチングした結果マス
ク3の側壁に付着する反応生成物である。まず、支持基
板1上に容量素子用電極または容量絶縁膜2をスパッタ
法や有機金属堆積法で形成し、所望の形状に加工するた
めにマスク3を形成し図6(a)のような構成にする。
次に図6(b)のように容量素子用電極または容量絶縁
膜2をドライエッチングする。最後に図6(c)のよう
にマスクを除去する。
Hereinafter, a conventional method for manufacturing a semiconductor device will be described with reference to the drawings. 6 (a) to 6 (c)
Is a process cross-sectional view showing a conventional method of manufacturing a capacitive element,
1 is a supporting substrate of a semiconductor or the like, 2 is a capacitor element electrode or a capacitive insulating film made of a high dielectric or ferroelectric, 3 is a mask made of a photo-curable resin, etc., 4 is a side wall of the mask 3 as a result of dry etching. It is a reaction product attached to. First, a capacitor element electrode or a capacitor insulating film 2 is formed on a supporting substrate 1 by a sputtering method or an organic metal deposition method, and a mask 3 is formed for processing into a desired shape. To
Next, as shown in FIG. 6B, the electrode for the capacitor or the capacitor insulating film 2 is dry-etched. Finally, the mask is removed as shown in FIG.

【0004】[0004]

【発明が解決しようとする課題】しかしながら上記従来
の製造方法では、容量素子用電極または容量絶縁膜2を
ドライエッチングする際にマスク3の側壁に付着する反
応生成物4が、マスク除去後にも残るために、ドライエ
ッチング後に容量素子上に形成される薄膜のカバレッジ
不良が発生し、正常な特性が得られないという課題を有
していた。
However, in the above-mentioned conventional manufacturing method, the reaction product 4 adhered to the side wall of the mask 3 when the electrode for the capacitive element or the capacitive insulating film 2 is dry-etched remains after the mask is removed. For this reason, there has been a problem that a coverage failure of a thin film formed on the capacitor element after the dry etching occurs and normal characteristics cannot be obtained.

【0005】本発明は上記従来の課題を解決するもので
あり、マスク側壁に付着する反応生成物がないため、正
常な容量素子の特性が得られる容量素子の製造方法を提
供することを目的とする。
An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a method of manufacturing a capacitive element capable of obtaining normal characteristics of a capacitive element because there is no reaction product attached to a mask side wall. I do.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するた
め、本発明の第1番目の容量素子の製造方法は、高誘電
率を有する誘電体または強誘電体を容量絶縁膜とする容
量素子の形成において、マスク材料をパターニングする
工程と、前記容量素子を構成する電極材料または誘電体
材料をドライエッチングする工程と、前記ドライエッチ
ング後に大気に暴露することなく洗浄を行う工程と、前
記マスク材料を除去する工程とを有することを特徴とす
る。この構成により、容量素子用電極または容量絶縁膜
のドライエッチング後にも反応生成物の付着がないエッ
チング形状を実現できるため、容量素子の正常な特性を
得ることができる。
In order to achieve the above object, a first method of manufacturing a capacitor according to the present invention is directed to a method of manufacturing a capacitor using a dielectric or ferroelectric having a high dielectric constant as a capacitor insulating film. In the formation, a step of patterning a mask material, a step of dry-etching an electrode material or a dielectric material constituting the capacitive element, a step of performing cleaning without exposing to air after the dry etching, Removing step. With this configuration, an etched shape in which a reaction product does not adhere even after dry etching of the capacitor electrode or the capacitor insulating film can be realized, and thus normal characteristics of the capacitor can be obtained.

【0007】前記において、高誘電率を有する誘電体と
は、チタン酸ストロンチウム(SrTiO3),チタン
酸ストロンチウムバリウム(BaxSr1-xTiO3、た
だし、0<x<1)、酸化タンタル(Ta25)等をい
う。また、強誘電体とは、チタン酸鉛ジルコニウム(P
bZr1-xTix3、ただし、0<x<1)、タンタル
酸ビスマスストロンチウム(SrBi2Ta29)等を
いう。
In the above, the dielectric having a high dielectric constant includes strontium titanate (SrTiO 3 ), barium strontium titanate (Ba x Sr 1 -x TiO 3 , where 0 <x <1), tantalum oxide ( Ta 2 O 5 ). Ferroelectrics are lead zirconium titanate (P
bZr 1-x Ti x O 3 , where 0 <x <1), and bismuth strontium tantalate (SrBi 2 Ta 2 O 9 ).

【0008】次に本発明の第2番目の容量素子の製造方
法は、高誘電率を有する誘電体または強誘電体を容量絶
縁膜とする容量素子の形成において、マスク材料を5°
以上80゜以下のテーパー角度を持つようにパターニン
グする工程と、前記容量素子を構成する電極材料または
誘電体材料をドライエッチングする工程と、前記マスク
材料を除去する工程とを有することを特徴とする。この
構成により、容量素子用電極または容量絶縁膜のドライ
エッチング時にマスク側壁に付着する反応生成物を、ド
ライエッチング時のイオン衝突により物理的に除去で
き、反応生成物の付着がないエッチング形状を実現でき
るため、容量素子の正常な特性を得ることができる。
Next, a second method of manufacturing a capacitive element according to the present invention provides a method of forming a capacitive element using a dielectric or ferroelectric having a high dielectric constant as a capacitive insulating film by using a mask material of 5 °.
Patterning so as to have a taper angle of not less than 80 °, a step of dry-etching an electrode material or a dielectric material constituting the capacitive element, and a step of removing the mask material. . With this configuration, reaction products adhering to the mask side wall during dry etching of the capacitor element electrode or the capacitor insulating film can be physically removed by ion bombardment during dry etching, realizing an etched shape without reaction product adhesion. Therefore, normal characteristics of the capacitor can be obtained.

【0009】次に本発明の第3番目の容量素子の製造方
法は、高誘電率を有する誘電体または強誘電体を容量絶
縁膜とする容量素子の形成において、マスク材料をパタ
ーニングする工程と、前記容量素子を構成する電極材料
または誘電体材料を100℃以上400℃以下の基板温
度でドライエッチングする工程と、前記マスク材料を除
去する工程とを有することを特徴とする。この構成によ
り、容量素子用電極または容量絶縁膜のドライエッチン
グ時の反応生成物を揮発性の高い状態のまま排気でき、
反応生成物の付着がないエッチング形状を実現できるた
め、容量素子の正常な特性を得ることができる。
Next, a third method of manufacturing a capacitive element according to the present invention includes a step of patterning a mask material in forming a capacitive element using a dielectric or ferroelectric having a high dielectric constant as a capacitive insulating film; A step of dry-etching an electrode material or a dielectric material constituting the capacitor at a substrate temperature of 100 ° C. or more and 400 ° C. or less; and a step of removing the mask material. With this configuration, the reaction product at the time of dry etching of the capacitor element electrode or the capacitor insulating film can be exhausted in a highly volatile state,
Since an etched shape without the attachment of reaction products can be realized, normal characteristics of the capacitor can be obtained.

【0010】前記本発明の第1〜3番目の容量素子の製
造方法においては、容量素子を構成する電極材料が、白
金、パラジウム、ルテニウム、酸化ルテニウム、イリジ
ウム、酸化イリジウム、チタン、酸化チタン及び窒化チ
タンから選ばれる少なくとも一つを含む材料であること
が好ましい。
In the first to third capacitive element manufacturing methods of the present invention, the electrode material constituting the capacitive element is platinum, palladium, ruthenium, ruthenium oxide, iridium, iridium oxide, titanium, titanium oxide and nitride. It is preferable that the material contains at least one selected from titanium.

【0011】また前記本発明の第1〜3番目の容量素子
の製造方法においては、マスク材料が、フォトレジス
ト、酸化珪素、チタン、酸化チタン、窒化チタン、タン
タルおよびタングステンから選ばれる少なくとも一つを
含む材料であることが好ましい。
In the first to third methods of manufacturing a capacitor according to the present invention, the mask material is at least one selected from the group consisting of photoresist, silicon oxide, titanium, titanium oxide, titanium nitride, tantalum and tungsten. Preferably, it is a material containing.

【0012】また前記本発明の第1番目の容量素子の製
造方法においては、洗浄を行う雰囲気が、窒素、アルゴ
ン及びヘリウムから選ばれる少なくとも一つの不活性ガ
ス雰囲気であることが好ましい。これにより、反応生成
物の酸化により除去が困難な安定な物質になることを防
止することができる。
In the first method of manufacturing a capacitive element according to the present invention, it is preferable that the cleaning atmosphere is at least one inert gas atmosphere selected from nitrogen, argon and helium. This prevents the reaction product from becoming a stable substance that is difficult to remove due to oxidation.

【0013】また前記本発明の第1番目の容量素子の製
造方法においては、洗浄に用いる溶液が、水、塩酸、硝
酸、弗酸及び有機溶剤から選ばれる少なくとも一つを含
む溶液であることが好ましい。これにより、反応生成物
を化学的に除去することができる。
[0013] In the first method of manufacturing a capacitive element of the present invention, the solution used for cleaning may be a solution containing at least one selected from water, hydrochloric acid, nitric acid, hydrofluoric acid and an organic solvent. preferable. Thereby, the reaction product can be removed chemically.

【0014】[0014]

【発明の実施の形態】(実施の形態1)以下本発明の第
1の実施の形態について、図を参照しながら説明する。
(Embodiment 1) Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

【0015】図1(a)〜(d)は本発明の第1の実施
の形態における容量素子の製造方法の工程断面図であ
る。まず図1(a)に示すように、Si,GaAs等の
化合物半導体、ガラス基板などの支持基板1上に容量素
子用電極または容量絶縁膜2をスパッタ法や有機金属堆
積法で形成し、続いて所望の形状に加工するためのマス
ク3を形成した。次に、図1(b)に示すように、容量
素子用電極または容量絶縁膜2をドライエッチングし
た。この際、マスク3の側壁には反応生成物4が付着し
た。次に、図1(c)に示すように、エッチング後の支
持基板1を大気に曝すことなく窒素雰囲気下で洗浄し、
マスク3の側壁に付着した反応生成物4を除去した。最
後に、図1(d)に示すように、マスク3を除去した。
FIGS. 1A to 1D are process sectional views of a method of manufacturing a capacitor according to a first embodiment of the present invention. First, as shown in FIG. 1A, a capacitor element electrode or a capacitor insulating film 2 is formed on a supporting substrate 1 such as a compound semiconductor such as Si or GaAs or a glass substrate by a sputtering method or an organic metal deposition method. Thus, a mask 3 for processing into a desired shape was formed. Next, as shown in FIG. 1B, the electrode for the capacitor element or the capacitor insulating film 2 was dry-etched. At this time, the reaction product 4 adhered to the side wall of the mask 3. Next, as shown in FIG. 1C, the etched support substrate 1 is washed in a nitrogen atmosphere without being exposed to the air.
The reaction product 4 attached to the side wall of the mask 3 was removed. Finally, as shown in FIG. 1D, the mask 3 was removed.

【0016】このように上記実施の形態によれば、容量
素子用電極または容量絶縁膜2をドライエッチング後に
酸素に触れることなく洗浄を行うことにより、反応生成
物4が酸化され除去が困難な物質になることなく容易に
マスク3の側壁に付着した反応生成物4を除去すること
ができた。
As described above, according to the above-described embodiment, by cleaning the electrode for the capacitor element or the capacitor insulating film 2 without being exposed to oxygen after the dry etching, the reaction product 4 is oxidized and is difficult to remove. The reaction product 4 adhering to the side wall of the mask 3 could be easily removed without becoming.

【0017】例えば、容量素子用電極として白金を用い
た場合、ドライエッチングで用いるガスはおもに塩素を
含んでいるため、反応生成物は2塩化白金または4塩化
白金となる。2塩化白金は、塩酸に溶解する。また、4
塩化白金は、水、エタノールまたはアセトンに溶解す
る。以上から、洗浄剤として塩酸と水の混合液を用いれ
ばマスク3の側壁に付着した反応生成物4を完全に除去
できる。なお、2塩化白金または4塩化白金が酸化した
場合には、塩化酸化白金が形成される。これは化学的に
非常に安定であり、除去困難となるため、大気にさらす
ことなく洗浄することが不可欠となる。
For example, when platinum is used as the electrode for the capacitive element, the gas used in the dry etching mainly contains chlorine, so that the reaction product is platinum dichloride or platinum tetrachloride. Platinum dichloride dissolves in hydrochloric acid. Also, 4
Platinum chloride dissolves in water, ethanol or acetone. As described above, if a mixture of hydrochloric acid and water is used as the cleaning agent, the reaction product 4 attached to the side wall of the mask 3 can be completely removed. When platinum dichloride or platinum tetrachloride is oxidized, platinum chloride oxide is formed. Since it is chemically very stable and difficult to remove, it is essential to clean it without exposing it to the atmosphere.

【0018】また、例えば容量絶縁膜としてSrBi2
Ta29を用いた場合、ドライエッチングで用いるガス
はおもに塩素または弗素を含んでいるため、反応生成物
4はBiClxおよびSrClx、TaClx、またはB
iFxおよびSrFx、TaFxとなる。これらは、弗酸
と硝酸の混合液に溶解する。以上から弗酸と硝酸の混合
液を用いればマスク3の側壁に付着した反応生成物4を
完全に除去できる。
Further, for example, SrBi 2
When Ta 2 O 9 is used, the gas used in the dry etching mainly contains chlorine or fluorine, so that the reaction product 4 is BiCl x and SrCl x , TaCl x , or B
iF x, SrF x , and TaF x . These dissolve in a mixture of hydrofluoric acid and nitric acid. As described above, if a mixed solution of hydrofluoric acid and nitric acid is used, the reaction product 4 attached to the side wall of the mask 3 can be completely removed.

【0019】以上のようにして得られた容量素子用電極
または容量絶縁膜2の厚さは0.2〜0.4μmであっ
た。なお、本実施の形態では、容量素子用電極として、
白金を用いたが、パラジウム、ルテニウム、酸化ルテニ
ウム、イリジウム、酸化イリジウム、チタン、酸化チタ
ン、または窒化チタンを少なくとも含む材料でも同様の
効果が得られる。
The thickness of the capacitor electrode or capacitor insulating film 2 obtained as described above was 0.2 to 0.4 μm. Note that, in this embodiment, as the capacitor element electrode,
Although platinum was used, a similar effect can be obtained with a material containing at least palladium, ruthenium, ruthenium oxide, iridium, iridium oxide, titanium, titanium oxide, or titanium nitride.

【0020】また、本実施の形態では洗浄剤として、塩
酸と水の混合液および弗酸と硝酸の混合液を用いたが、
容量素子用電極材料または容量絶縁膜に応じて種々の選
択が可能である。例えば、80℃以上の水、または有機
溶剤を少なくとも含む材料を用いることができる。
In this embodiment, a mixture of hydrochloric acid and water and a mixture of hydrofluoric acid and nitric acid are used as the cleaning agent.
Various selections can be made according to the electrode material for the capacitor element or the capacitor insulating film. For example, a material containing at least 80 ° C. water or an organic solvent can be used.

【0021】また、本実施の形態では、洗浄時の雰囲気
として窒素を用いたが、アルゴンまたはヘリウム等の不
活性ガスであれば同等の効果が得られる。
In this embodiment, nitrogen is used as the atmosphere during cleaning. However, an equivalent effect can be obtained with an inert gas such as argon or helium.

【0022】(実施の形態2)次に、本発明の第2の実
施の形態について、図を参照しながら説明する。図2
(a)〜(c)は本発明の第2の実施の形態における容
量素子の製造方法の工程断面図である。まず図2(a)
に示すように、支持基板1上に容量素子用電極または容
量絶縁膜2を第1の実施形態と同様の方法で形成し、続
いて所望の形状に加工するためのマスク3として75°
のテーパー角度θを有するフォトレジストを形成した。
次に、図2(b)に示すように、容量素子用電極または
容量絶縁膜2をドライエッチングした。この際、マスク
3の側壁に付着する反応生成物4はドライエッチング時
のイオン5の衝突によりスパッタエッチングされた。最
後に、図2(c)に示すように、マスク3を除去した。
(Embodiment 2) Next, a second embodiment of the present invention will be described with reference to the drawings. FIG.
(A)-(c) is process sectional drawing of the manufacturing method of the capacitive element in the 2nd Embodiment of this invention. First, FIG.
As shown in FIG. 5, a capacitor element electrode or a capacitor insulating film 2 is formed on a support substrate 1 in the same manner as in the first embodiment, and then a mask 3 for processing into a desired shape is formed at 75 °.
A photoresist having a taper angle θ was formed.
Next, as shown in FIG. 2B, the electrode for the capacitor element or the capacitor insulating film 2 was dry-etched. At this time, the reaction product 4 attached to the side wall of the mask 3 was sputter-etched by the collision of the ions 5 during the dry etching. Finally, as shown in FIG. 2C, the mask 3 was removed.

【0023】このように上記実施の形態によれば、75
°のテーパー角度を有するマスク形状を有しているた
め、マスク側壁部はドライエッチング時に常にイオン衝
突に曝されており、その結果側壁に付着する反応生成物
4がスパッタエッチングされ、マスク3の側壁に付着し
て残る反応生成部(以下、残さという)のないエッチン
グ形状を実現できた。
As described above, according to the above embodiment, 75
Because of the mask shape having a taper angle of 0 °, the mask side wall is always exposed to ion bombardment during dry etching, and as a result, the reaction product 4 attached to the side wall is sputter-etched, An etching shape without a reaction generating portion (hereinafter, referred to as a residue) remaining after adhering to the substrate was realized.

【0024】マスク3としてフォトレジストを用いたと
きのテーパーの角度θと、マスク3の側壁に反応生成物
4が付着する割合(側壁付着発生率)との関係は図3に
示すようになり、テーパー角度θが80°以下であれば
残さのない形状を実現できることが確認できた。また、
テーパー角度θが5°未満であると、マスクの両端でマ
スクとして機能しなくなる。したがって、テーパー角度
θは5°以上80°以下が好ましい。
FIG. 3 shows the relationship between the taper angle θ when a photoresist is used as the mask 3 and the ratio of the reaction product 4 adhering to the side wall of the mask 3 (side wall adhering rate). It was confirmed that a shape without residue can be realized if the taper angle θ is 80 ° or less. Also,
If the taper angle θ is less than 5 °, both ends of the mask will not function as a mask. Therefore, the taper angle θ is preferably 5 ° or more and 80 ° or less.

【0025】なお、本実施の形態によれば、マスク3の
材料としてフォトレジストを用いたが、酸化珪素、タン
タル、チタン、酸化チタン、窒化チタンまたはタングス
テンを少なくとも含む材料でも同様の効果が得られる。
According to the present embodiment, a photoresist is used as the material of the mask 3, but a similar effect can be obtained by using a material containing at least silicon oxide, tantalum, titanium, titanium oxide, titanium nitride or tungsten. .

【0026】(実施の形態3)次に、本発明の第3の実
施の形態について、図を参照しながら説明する。図4
(a)〜(c)は本発明の第3の実施の形態における容
量素子の製造方法の工程断面図である。まず図4(a)
に示すように、支持基板1上に容量素子用電極または容
量絶縁膜2を第1の実施形態と同様の方法で形成し、続
いて所望の形状に加工するためのマスク3を形成した。
次に、図4(b)に示すように、容量素子用電極または
容量絶縁膜2を、支持基板1の温度(以下、基板温度と
いう)を120℃に保ちながらドライエッチングした。
この際、基板温度を120℃に保っているため、反応生
成物4は揮発性に富んでおり、その結果マスク3の側壁
に付着することなく排気された。最後に、図4(c)に
示すように、マスク3を除去した。
(Embodiment 3) Next, a third embodiment of the present invention will be described with reference to the drawings. FIG.
(A)-(c) is process sectional drawing of the manufacturing method of the capacitive element in the 3rd Embodiment of this invention. First, FIG.
As shown in FIG. 5, an electrode for a capacitor or a capacitor insulating film 2 was formed on a support substrate 1 in the same manner as in the first embodiment, and then a mask 3 for processing into a desired shape was formed.
Next, as shown in FIG. 4B, the electrode for the capacitor element or the capacitor insulating film 2 was dry-etched while the temperature of the supporting substrate 1 (hereinafter, referred to as substrate temperature) was kept at 120 ° C.
At this time, since the substrate temperature was maintained at 120 ° C., the reaction product 4 was rich in volatility, and as a result, was exhausted without adhering to the side wall of the mask 3. Finally, as shown in FIG. 4C, the mask 3 was removed.

【0027】このように上記実施の形態によれば、基板
温度を120℃に保ちながらドライエッチングを行うた
め、室温では揮発性に乏しい材料でも容易に揮発させる
ことが可能となる。その結果、反応生成物4はマスク3
の側壁に付着することなく排気され、残さのないエッチ
ング形状を実現できる。
As described above, according to the above embodiment, since dry etching is performed while the substrate temperature is kept at 120 ° C., even a material having low volatility at room temperature can be easily volatilized. As a result, the reaction product 4 becomes the mask 3
The gas is exhausted without adhering to the side wall of the substrate, and an etched shape having no residue can be realized.

【0028】基板温度と側壁付着率発生率との関係は図
5に示すようになり、基板温度が100℃以上であれば
残さのない形状を実現できることを確認した。また、基
板温度が400℃を越えると、容量素子の特性が劣化し
やすい。したがって、基板温度は100℃以上400℃
以下が好ましい。
FIG. 5 shows the relationship between the substrate temperature and the rate of occurrence of the side wall adhesion rate, and it was confirmed that if the substrate temperature was 100 ° C. or higher, a shape with no residue could be realized. On the other hand, when the substrate temperature exceeds 400 ° C., the characteristics of the capacitor are likely to deteriorate. Therefore, the substrate temperature is 100 ° C. or more and 400 ° C.
The following is preferred.

【0029】[0029]

【発明の効果】以上のように本発明によれば、エッチン
グ直後に空気に曝されることなく洗浄する、またはマス
ク材料に5°以上80°以下のテーパー角度を付ける、
または基板温度を100℃以上400℃以下に保ちなが
らドライエッチングをすることにより、マスク側壁に残
さのない高精度のエッチング形状を実現する優れた信頼
性を有する容量素子の製造方法を提供することが可能と
なる。
As described above, according to the present invention, cleaning is performed without being exposed to air immediately after etching, or a taper angle of 5 ° or more and 80 ° or less is applied to a mask material.
Alternatively, it is possible to provide a method for manufacturing a capacitive element having excellent reliability that realizes a highly accurate etched shape that does not remain on a mask side wall by performing dry etching while maintaining a substrate temperature at 100 ° C. or higher and 400 ° C. or lower. It becomes possible.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 (a)〜(d)は本発明の第1の実施形態の
容量素子の製造方法における工程図。
FIGS. 1A to 1D are process diagrams in a method for manufacturing a capacitive element according to a first embodiment of the present invention.

【図2】 (a)〜(c)は本発明の第2の実施形態の
容量素子の製造方法における工程図。
FIGS. 2A to 2C are process diagrams in a method for manufacturing a capacitor according to a second embodiment of the present invention.

【図3】 本発明の第2の実施形態のフォトレジストの
テーパー角度と側壁付着発生率との関係を示す図。
FIG. 3 is a diagram showing a relationship between a taper angle of a photoresist and a rate of occurrence of side wall adhesion according to a second embodiment of the present invention.

【図4】 (a)〜(c)は本発明の第3の実施形態の
容量素子の製造方法における工程図。
FIGS. 4A to 4C are process diagrams in a method for manufacturing a capacitor according to a third embodiment of the present invention.

【図5】 本発明の第3の実施形態の基板温度と側壁付
着発生率との関係を示す図。
FIG. 5 is a diagram illustrating a relationship between a substrate temperature and a side wall adhesion occurrence rate according to a third embodiment of the present invention.

【図6】 (a)〜(c)は従来の容量素子の製造方法
における工程図。
6 (a) to 6 (c) are process diagrams in a conventional method for manufacturing a capacitive element.

【符号の説明】[Explanation of symbols]

1 支持基板 2 容量素子用電極または容量絶縁膜 3 マスク 4 反応生成物 DESCRIPTION OF SYMBOLS 1 Support substrate 2 Electrode or capacitive insulating film for capacitive elements 3 Mask 4 Reaction product

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 27/10 451 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 27/10 451

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 高誘電率を有する誘電体または強誘電体
を容量絶縁膜とする容量素子の形成において、マスク材
料をパターニングする工程と、前記容量素子を構成する
電極材料または誘電体材料をドライエッチングする工程
と、前記ドライエッチング後に大気に暴露することなく
洗浄を行う工程と、前記マスク材料を除去する工程とを
有することを特徴とする容量素子の製造方法。
In forming a capacitor using a dielectric or a ferroelectric having a high dielectric constant as a capacitor insulating film, a step of patterning a mask material and a step of drying an electrode material or a dielectric material forming the capacitor are performed. A method for manufacturing a capacitive element, comprising: a step of performing etching; a step of performing cleaning without exposing to air after the dry etching; and a step of removing the mask material.
【請求項2】 高誘電率を有する誘電体または強誘電体
を容量絶縁膜とする容量素子の形成において、マスク材
料を5゜以上80゜以下のテーパー角度を持つようにパ
ターニングする工程と、前記容量素子を構成する電極材
料または誘電体材料をドライエッチングする工程と、前
記マスク材料を除去する工程とを有することを特徴とす
る容量素子の製造方法。
2. A step of patterning a mask material so as to have a taper angle of not less than 5 ° and not more than 80 ° in forming a capacitive element using a dielectric or a ferroelectric having a high dielectric constant as a capacitive insulating film; A method for manufacturing a capacitive element, comprising: a step of dry-etching an electrode material or a dielectric material forming a capacitive element; and a step of removing the mask material.
【請求項3】 高誘電率を有する誘電体または強誘電体
を容量絶縁膜とする容量素子の形成において、マスク材
料をパターニングする工程と、前記容量素子を構成する
電極材料または誘電体材料を100℃以上400℃以下
の基板温度でドライエッチングする工程と、前記マスク
材料を除去する工程とを有することを特徴とする容量素
子の製造方法。
3. A step of patterning a mask material in forming a capacitive element using a dielectric or ferroelectric having a high dielectric constant as a capacitive insulating film, and using an electrode material or a dielectric material constituting the capacitive element by 100%. A method for manufacturing a capacitive element, comprising: a step of performing dry etching at a substrate temperature of not less than 400C and a temperature of not more than 400C; and a step of removing the mask material.
【請求項4】 容量素子を構成する電極材料が、白金、
パラジウム、ルテニウム、酸化ルテニウム、イリジウ
ム、酸化イリジウム、チタン、酸化チタン及び窒化チタ
ンから選ばれる少なくとも一つを含む材料である請求項
1〜3のいずれかに記載の容量素子の製造方法。
4. An electrode material constituting a capacitive element is platinum,
The method for manufacturing a capacitive element according to any one of claims 1 to 3, wherein the material includes at least one selected from palladium, ruthenium, ruthenium oxide, iridium, iridium oxide, titanium, titanium oxide, and titanium nitride.
【請求項5】 マスク材料が、フォトレジスト、酸化珪
素、チタン、酸化チタン、窒化チタン、タンタルおよび
タングステンから選ばれる少なくとも一つを含む材料で
ある請求項1〜3のいずれかに記載の容量素子の製造方
法。
5. The capacitive element according to claim 1, wherein the mask material is a material containing at least one selected from photoresist, silicon oxide, titanium, titanium oxide, titanium nitride, tantalum and tungsten. Manufacturing method.
【請求項6】 洗浄を行う雰囲気が、窒素、アルゴン及
びヘリウムから選ばれる少なくとも一つの不活性ガス雰
囲気である請求項1に記載の容量素子の製造方法。
6. The method according to claim 1, wherein the atmosphere in which the cleaning is performed is at least one inert gas atmosphere selected from nitrogen, argon, and helium.
【請求項7】 洗浄に用いる溶液が、水、塩酸、硝酸、
弗酸及び有機溶剤から選ばれる少なくとも一つを含む溶
液である請求項1に記載の容量素子の製造方法。
7. The solution used for washing is water, hydrochloric acid, nitric acid,
The method according to claim 1, wherein the solution is a solution containing at least one selected from hydrofluoric acid and an organic solvent.
JP11122299A 1999-04-28 1999-04-28 Manufacture of capacitor elements Pending JP2000004010A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11122299A JP2000004010A (en) 1999-04-28 1999-04-28 Manufacture of capacitor elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11122299A JP2000004010A (en) 1999-04-28 1999-04-28 Manufacture of capacitor elements

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP8157293A Division JP2954877B2 (en) 1996-06-18 1996-06-18 Manufacturing method of capacitive element

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Publication Number Publication Date
JP2000004010A true JP2000004010A (en) 2000-01-07

Family

ID=14832527

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2000004010A (en)

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KR101142585B1 (en) 2009-06-12 2012-05-03 아이엠이씨 Substrate treating method and method of manufacturing semiconductor device using the same

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JPH07130702A (en) * 1993-11-08 1995-05-19 Fujitsu Ltd Method for patterning metal film made of platinum or palladium
JPH07307326A (en) * 1994-05-11 1995-11-21 Sony Corp Plasma etching apparatus and plasma etching method
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JP2008288292A (en) * 2007-05-16 2008-11-27 Renesas Technology Corp Semiconductor storage device and its manufacturing method
KR101142585B1 (en) 2009-06-12 2012-05-03 아이엠이씨 Substrate treating method and method of manufacturing semiconductor device using the same
US8324116B2 (en) 2009-06-12 2012-12-04 Imec Substrate treating method and method of manufacturing semiconductor device using the same

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