JP2000099391A - Printer, printer controlling method and storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To parallelly access respective memory banks to which a memory is divided. SOLUTION: When a CPU 6 issues a read or write request to a memory bank B 13, an arbitration circuit 9 immediately sends the read or write request from the CPU 6 to a bank B access circuit 15, and the CPU 6 reads or writes data from/in the memory bank B 13. When the CPU 6 issues a read or write request to a memory bank A 12, the arbitration circuit 9 sends the read or write access from the CPU 6 to a bank A access circuit 10 when a host data transfer circuit 8 does not perform access to the memory bank A 12 and controls in such a manner that the CPU 6 can read or write data from/in the memory bank A 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printer device, a printer control method, and a recording medium, and more particularly, to a printer device and a printer which can access memory banks constituting a memory in parallel. The present invention relates to a control method and a recording medium.

[0002]

2. Description of the Related Art Conventionally, in a memory bank division method of a printer controller in a printer device, when a memory capacity to be used is insufficient, a memory is divided into a plurality of banks so that the memory can be easily expanded. Was split.

FIG. 5 is a block diagram showing an example of the prior art in which a memory is divided into a plurality of banks for such a purpose. As shown in FIG. 5, the memory control circuit 7 includes a host data transfer circuit 8, an arbitration circuit 45, a bank selection circuit 44, a bank A access circuit 10, and a bank B access circuit 15.

The arbitration circuit 45 has a CPU (central)
processing unit) 6 to memory 1
When there is a read request or a write request to the host 1, the host data transfer circuit 8 determines whether data is currently being written to the memory 11. And if a write has not been performed, a read request or a write request is sent to the bank selection circuit 44.

When data is transferred from a host computer (hereinafter abbreviated as a host) 1, the host data transfer circuit 8 requests the arbitration circuit 45 to write to the memory 11. Upon receiving a write request from the host data transfer circuit 8, the arbitration circuit 45 determines whether the CPU 6 is reading or writing data to or from the memory 11, and the CPU 6 reads or writes data from or to the memory 11. If writing, wait for the end, then
As soon as U6 is not reading or writing data to or from the memory 11, write permission is given to the host data transfer circuit 8. As a result, the host data transfer circuit 8 sends a write request to the bank selection circuit 44.

When a read or write request is sent, the bank selection circuit 44 detects whether the bit 20 of the address included in the read or write request is 0 or 1, and sets the bit 20 of the address to 0. If 0,
A read or write request is sent to the bank A access circuit 10. If bit 20 of the address is 1, a read or write request is sent to the bank B access circuit 15.

When a read or write request is sent from the bank selection circuit 44, the bank A access circuit 10 reads or writes data from or to the memory bank A12. When a read or write request is sent from the bank selection circuit 44, the bank B access circuit 15 reads or writes data to or from the memory bank B13.

The memory 11 has a memory bank A12
And a memory bank B13. The memory bank A12 and the memory bank B13 are, for example,
It is composed of a 1 megabyte (1 Mbyte) memory chip. By the operation of the bank selection circuit 44, the address of the memory bank A12 is represented by 0 in hexadecimal.
00000000 to 000FFFFF, and the address of the memory bank B13 is represented by 0010 in hexadecimal.
0000 to 001FFFFF.

Further, when writing data from the host data transfer circuit 8 to the memory 11, bit 2 of the address is used.
0 is set to 0, which is a write to the memory bank A12,
In the reading and writing of data from and to the memory 11 by the PU 6, the bit 20 of the address is set to 0 or 1, and the reading or writing is performed to both the memory bank A12 and the memory bank B13.

Here, the memory bank B1 by the CPU 6
It is assumed that a read or write request has occurred for host 3 and data has been transferred from host 1.

In this case, in response to a read or write request from the CPU 6, the arbitration circuit 45 checks whether or not the host data transfer circuit 8 is currently writing data to the memory bank 11A. If not, a read or write request is sent to the bank selection circuit 44. The bank selection circuit 44 detects that bit 20 of the address included in the read or write request is 1, and sends a read or write request to the bank B access circuit 15.

The bank B access circuit 15 reads or writes data from or to the memory bank B13 in response to a read or write request from the bank selection circuit 44. Since the host data transfer circuit 8 has received data from the host 1, the host data transfer circuit 8 requests the arbitration circuit 45 to permit writing. At this time, as described above, the CPU 6
Since data is being read from or written to the memory bank B13, the write permission is waited until this is completed. Then, the memory bank B by the CPU 6
When the reading or writing of data to the memory 13 is completed, a write permission is given to the host data transfer circuit 8, and the host data transfer circuit 8 issues a write request to the bank selection circuit 4.
Send to 4.

The bank selection circuit 44 detects that bit 20 of the address included in the write request is 0, and sends a write request to the bank A access circuit 10. Bank A
The access circuit 10 writes data to the memory bank A12 in response to the write request.

The data read from the memory bank 13 by the CPU 6 is supplied to the printing mechanism 3, and the printing is performed by the printing mechanism 3.

[0015]

As described above, the memory 1
Arbitration of access to 1 is not performed for each memory bank, and after arbitration for the memory 11, it is configured to detect which memory bank data is read or written to.

For this reason, the memory bank A12 cannot be allocated as an area used only for the function of writing data received from the host 1 to the memory 11, and the memory bank A12 and the memory bank B13 cannot be allocated.
When reading or writing data to either one of them, there is a problem that reading or writing of data to the other is delayed.

The present invention has been made in view of such a situation, and arbitration at the time of reading or writing data from or to a memory is performed for each memory bank, so that each memory bank can be accessed simultaneously. Thus, the processing performance can be improved.

[0018]

According to a first aspect of the present invention, there is provided a printer having a memory divided into a plurality of memory banks, wherein the memory is used as a memory area for realizing a first function. Allocating means for exclusively allocating a predetermined one of the plurality of memory banks, and a first function when the second function uses a predetermined one of the plurality of memory banks allocated to the first function. Does not use a given one of multiple memory banks,
If the second function permits use of a predetermined one of the plurality of memory banks and the first function uses a predetermined one of the plurality of memory banks assigned to the first function, When the second function does not use the predetermined one of the plurality of memory banks, the first function is permitted to use the predetermined one of the plurality of memory banks, and the predetermined one of the plurality of memory banks is used. Arbitration means for arbitrating a conflict occurring when the memory bank is used, wherein the arbitration means unconditionally permits the use of another predetermined one of the plurality of memory banks by the second function. 3. The printer device according to claim 2, wherein the printer device has a memory divided into first and second memory banks, wherein the first access means accesses the first memory bank, and the second memory device. Second access means for accessing the bank, data receiving means for receiving data from a predetermined external device, accessing the first memory bank via the first access means, and writing data, and a predetermined function Access the first memory bank via the first access means,
The first through the first access means by the data receiving means
Arbitration so as not to conflict with the access to the memo bank of
Arbitration means for arbitration so as not to conflict with access to the first memory bank via the first access means by a predetermined function when accessing the memory bank of the second type. The access to the second memory bank via the access means is unconditionally permitted. The printer device according to claim 3, wherein the printer device has a memory divided into first, second, and third memory banks, wherein a first access unit accesses the first memory bank; Second
Second access means for accessing the memory bank of
Third access means for accessing the third memory bank, data receiving means for receiving data from a predetermined external device, accessing the first memory bank via the first access means, and writing data Printing means for printing data received by the data receiving means, data transfer means for reading data from the third memory bank via the third access means, and transferring the data to the printing means; When accessing the first memory bank via the first access means, the first memory bank is arbitrated so as not to conflict with the access to the first memo bank via the first access means by the data reception means, and the data reception means performs the arbitration. When the first memory bank is accessed via the first access means, the first memory bank via the first access means having a predetermined function is accessed. Arbitration so as not to conflict with the access to the third memory bank when the predetermined function accesses the third memory bank via the third access means. When the data transfer unit accesses the third memory bank via the third access unit, the data transfer unit accesses the third memory bank via the third access unit using a predetermined function. Arbitration means for arbitrating so as not to conflict with access, wherein the arbitration means is provided with a second function via the second access means having a predetermined function.
Access to the memory bank is unconditionally permitted. A printer control method according to claim 4, which controls a printer having a memory divided into a plurality of memory banks, wherein
As a memory area used to realize the functions of
An allocating step of exclusively allocating a predetermined one of the plurality of memory banks; and, if the second function uses a predetermined one of the plurality of memory banks allocated to the first function, the first function includes: When the predetermined one of the plurality of memory banks is not used, the second function is permitted to use the predetermined one of the plurality of memory banks, and the first function is assigned to the first function. When the second function does not use the predetermined one of the plurality of memory banks, the first function is performed when the predetermined one of the plurality of memory banks is not used.
The function of (a), using a predetermined one of the plurality of memory banks, and arbitrating a conflict that occurs when the predetermined one of the plurality of memory banks is used. The use of another predetermined one of the plurality of memory banks according to the second function is unconditionally permitted. 6. A printer control method according to claim 5, wherein said printer control method controls a printer device having a memory divided into first and second memory banks, wherein a predetermined function accesses said first memory bank. In order to receive data from a predetermined external device, arbitrate so as not to conflict with access to the first memory bank for writing data, receive data from the external device, and write data, An arbitration step of arbitrating when access to one memory bank is performed so as not to conflict with access to the first memory bank by a predetermined function; and in the arbitration step, the second memory bank by the predetermined function is provided. Is unconditionally permitted to access. Claim 6
Is a printer device having a memory divided into first, second, and third memory banks, receiving data from a predetermined external device,
A data receiving step of accessing and writing data to the memory bank of the third memory bank, a printing step of printing the data received in the data receiving step, a data transfer step of reading data from the third memory bank and transferring the data to the printing step; When the predetermined function accesses the first memory bank, a first function in the data receiving step is performed.
Arbitration so as not to conflict with the access to the memo bank, and when the first memory bank is accessed in the data receiving step, arbitration is performed so as not to conflict with the access to the first memory bank by the predetermined function. Arbitrates when accessing the third memory bank so as not to conflict with access to the third memo bank in the data transfer step, and when the third memory bank is accessed in the data transfer step, And an arbitration step of arbitration so as not to conflict with access to the third memory bank by the function of (a). In the arbitration step, access to the second memory bank by a predetermined function is unconditionally permitted. I do. A recording medium according to a seventh aspect is characterized by recording a program capable of executing the printer control method according to any one of the fourth to sixth aspects. In the printer device, the printer control method, and the recording medium according to the present invention, a predetermined one of a plurality of memory banks is exclusively assigned as a memory area used to realize the first function, and the second function is When using a predetermined one of the plurality of memory banks assigned to the first function, when the first function does not use a predetermined one of the plurality of memory banks, When the first function uses a predetermined one of the plurality of memory banks assigned to the first function, the second function may use a plurality of predetermined ones of the plurality of memory banks. When a predetermined one of the memory banks is not used, the first function is permitted to use the predetermined one of the plurality of memory banks, and when the predetermined one of the plurality of memory banks is used. With arbitrates conflicts that raw, permits the second function, the use of other predetermined plurality of memory banks which are unconditionally.

[0019]

FIG. 1 is a block diagram showing an example of the configuration of an embodiment of a printer according to the present invention. FIG.
FIG. 2 is a block diagram showing a detailed configuration example of the arbitration circuit 9 of FIG. First, an outline of the present embodiment will be described with an example of one function of the printer device 2, that is, a function of receiving data from a host computer (hereinafter abbreviated as a host) 1.

As shown in FIG. 1, the memory 11 includes a memory bank A12 and a memory bank B13, and the arbitration circuit 9 includes a CPU (central process).
ngunit) 6 is a comparison circuit 2 for detecting whether a read or write from the memory 6 to the memory 11 is to the memory bank A12 or to the memory bank B13.
4 are provided.

First, the memory 1
It is detected whether a read or write request to 1 is for the memory bank A12 in which a conflict occurs, and arbitration by the arbitration circuit 9 is performed only when the request is for the memory bank A12 in which a conflict occurs.

In the case of the embodiment shown in FIG.
The memory received from the host 1 is written to the memory bank A12 by a write request to the memory bank A12 by allocating the memory bank A12 as a memory area used for a function of receiving data from the host 1. However, the memory bank A1
Since the CPU 6 also reads or writes the area 2, the host data transfer circuit 8 and the CPU 6 compete for the memory bank A12, that is, a conflict occurs.

Therefore, the address of the memory 11 at the time of a read or write request from the CPU 6 is detected by the comparison circuit 24. If the read or write request of the CPU 6 is for the memory bank A12, arbitration is performed. That is, while the host data transfer circuit 8 is writing to the memory bank A12, the CPU 6
When a request for reading or writing is made to the memory 12, the request is waited until the writing to the memory 11 by the host data transfer circuit 8 is completed. Also, the CPU 6
However, if the host data transfer circuit 8 makes a write request to the memory bank A12 while reading or writing to the memory bank A12, the request is kept waiting until the CPU 6 completes reading or writing to the memory 11.

However, when the CPU 6 reads or writes data to or from the memory bank B13, no arbitration is performed by the arbitration circuit 9 because contention does not occur, and reading or writing to the memory bank B13 is immediately performed.

Therefore, even while the data received from the host 1 is being written to the memory bank A12, the CPU
No. 6 can immediately read or write to the memory bank B13, and the effect of improving the performance of the printer device 2 can be obtained.

Hereinafter, a detailed description will be given with reference to FIGS. As shown in FIG. 1, a host 1 that sends data to be printed to the printer 2
Is connected. The printer device 2 includes a controller 4 for creating an image for printing from data received from the host 1 and a printing mechanism 3 for printing the image on paper.

The controller 4 analyzes the data received from the host 1 and creates an image for printing.
PU 6 and memory 11 for storing various data described later
And a memory control circuit 57 for writing data received from the host 1 to the memory 11 or controlling reading or writing of the memory 11 by the CPU 6.

The memory 11 includes a memory bank A12 and a memory bank B13. Here, each of the memories 11 is configured by a memory chip having a capacity of, for example, 1 megabyte (1 Mbyte).

The memory control circuit 57 is provided with a bank A access circuit 10 for reading or writing to the memory bank A12 in response to a read or write request.
And a read or write request, the memory bank B1
After receiving data from the bank B access circuit 15 for reading or writing data from the host 1 and receiving a write permission from the arbitration circuit 9 described later to the memory bank A12, the bank A access circuit 10 The host data transfer circuit 8 that issues a write request and, in response to the write permission request from the host data transfer circuit 8 to the memory bank A12, if the CPU 6 is not reading or writing to the memory bank A12, the write permission is granted. And a read or write request from the CPU 6 to the memory 11 is received. If the request is for the memory bank A12, the host data transfer circuit 8
2 is being written, and if it is being written, after writing is completed, a read or write request from the CPU 6 is sent to the bank A access circuit 10, and a read or write request from the CPU 6 to the memory 11 is received. In the case of the memory bank B13, the arbitration circuit 9 immediately sends a read or write request to the bank B access circuit 15.

As shown in FIG. 2, the arbitration circuit 9 includes a CPU
6 included in the read or write request from memory 6
A comparison circuit 24 for detecting whether the bit 20 of the address to 1 is 0 or 1; and when the comparison circuit 24 detects that the bit 20 of the address is 0, a read from the CPU 6 or A write request is sent to the enable A circuit 26, and when the comparison circuit 24 detects that the bit 20 of the address is 1, the CPU
6 and a read or write request from the selector circuit 25 to the bank access circuit 10 according to an instruction from an access detection circuit 27 to be described later. And an enable A circuit 26 for sending the signal to the control circuit 10.

Further, the arbitration circuit 9 receives a write request from the host data transfer circuit 8 during reading or writing to the memory 11 by the CPU 6 when the comparison circuit 24 detects that the bit 20 of the address is 0. When the read or write by the CPU 6 is completed,
Write permission is given in response to a write request from the host data transfer circuit 8, and while the host data transfer circuit 8 is writing to the memory bank A 12, the read operation is performed by the comparison circuit 24 which detects that bit 20 of the address is 0. Alternatively, when a write request is received from the CPU 6, after the writing of the host data transfer circuit 8 is completed, the enable A circuit 2
6 has an access detection circuit 27 for instructing the bank A access circuit 10 to send a read or write request from the selector circuit 25.

The comparison circuit 24 and the selector circuit 2
From the configuration of No. 5, when viewed from the CPU 6, the address at the time of reading or writing to the memory 11 is 00000000 to 000FFFFF when expressed in hexadecimal.
The M-byte area indicates the memory bank A12,
When expressed in base, 00100000 to 001FFF
The 1 Mbyte area that is the FF is stored in the memory bank B13.
Point to.

In FIGS. 1 and 2, reference numerals 5, 16, 1
The 7, 18, 19, 20, 21, 22 digitized and III lead data are directly input to the encoding unit 4,
Reference numerals 23, 28, and 29 indicate signal lines, respectively, and description thereof is omitted here.

Next, the operation of the embodiment shown in FIGS. 1 and 2 will be described. First, it is assumed that data from the host 1 has been received by the host data transfer circuit 8. At this time, the host data transfer circuit 8
Is made to the memory bank A12 to the access detection circuit 27 constituting Access detection circuit 2
When receiving a write request from the host data transfer circuit 8, the CPU 7 sends a write permission to the host data transfer circuit 8 when the CPU 6 is not reading or writing data to the memory bank A12.

When the host data transfer circuit 8 obtains the write permission from the access detection circuit 27, it sends a write request to the bank A access circuit 10. Thus, the bank A access circuit 10 writes data from the host 1 to the memory bank A12.

At this time, from the CPU 6, the memory bank B
It is assumed that a read or write request to the T.13 has occurred. The arbitration circuit 9 receives the read or write request from the CPU 6. If the bit 20 of the address included in the read or write request is 1, the comparison circuit 24 determines that the bit 20 of the address is 1 Is detected, and the read or write request from the CPU 6 is immediately sent to the bank B access circuit 15 by the selector circuit 25. As a result, the CPU 6 operates in the memory bank B13.
To read or write data.

Next, it is assumed that a read or write request has been generated from the CPU 6 to the memory bank A12 corresponding to the address where the bit 20 is 0. At this time, the comparison circuit 24 detects that the bit 20 of the address included in the read or write request from the CPU 6 is 0, and the selector circuit 25 sends the read or write request from the CPU 6 to the enable A circuit 26. .

When the comparison circuit 24 detects that the bit 20 of the address included in the read or write request from the CPU 6 is 0, the host data transfer circuit 8 switches the memory bank to the memory bank. A
In the case where the writing is being performed on the selector 12, the selector A 25 is supplied to the enable A circuit 26 after the writing is completed.
From the CPU 6 to the bank A access circuit 10. As a result, the bank A access circuit 10
To read or write data.

As described above, the CPU 6 operates in the memory bank A
The data read from the host 1 written in 12 is read and analyzed, an image for printing is created while reading or writing to the memory bank B13, and the image is sent to the printing mechanism 3 to be printed on paper. Perform

As described above, since arbitration is performed for each of the memory bank A12 and the memory bank B13 when reading or writing to the memory 11, functions such as writing data from the host 1 to the memory 11 are provided.
It is possible to assign to each of the memory bank A12 and the memory bank B13. While a given function is reading or writing data to one of memory banks A12 and B13, at the same time, in parallel, another function is reading or writing data to the other. be able to. Thereby, the performance of the printer device 2 can be improved.

FIGS. 3 and 4 are block diagrams showing a configuration example of another embodiment of the printing apparatus of the present invention. The configuration of the embodiment shown in FIG. 3 and FIG. 4 is basically the same as that of the embodiment shown in FIG. 1 and FIG. 2, but the configuration of the embodiment shown in FIG. 3 and FIG. The memory bank C37 is allocated as a memory area used in a function of transferring an image to be printed to the printing mechanism 3.

3 and 4, the memory 11 is constituted by a memory bank A12, a memory bank B13, and a memory bank C37, each of which is constituted by a memory chip having a capacity of, for example, 1 Mbyte.

The memory control circuit 67 includes the host data transfer circuit 8, the arbitration circuit 69, the image transfer circuit 35, the bank A access circuit 10, the bank B access circuit 15, and the bank C access circuit 36. I have.

When reading data from the memory bank C37, the image data transfer circuit 35 requests the access detection circuit 41 constituting the arbitration circuit 69 to permit the read operation. A read request to memory bank C37 is made to C access circuit. Then, the print image created on the memory bank C37 is output to the printing mechanism 3.

At this time, if the CPU 6 is reading or writing to the memory bank C37,
Until this is completed, the access detection circuit 41 does not give read permission to the image data transfer circuit 35.

The comparison circuit 38, the selector circuit 39, the access detection circuit 41, and the enable A circuit 26 provide the memory bank A12 if the bit (21, 20) of the address included in the read or write request of the CPU 6 is (0, 0).
If the bit (21, 20) of the address is (0, 1), it is processed as a read or write request to the memory bank B13. These operations are basically the same as those in the above-described embodiment shown in FIGS. 1 and 2 when the bit 20 of the address is 0 or 1.

The bit (21, 20) of the address is (1,
In the case of (0), when the comparison circuit 38 detects this, the selector circuit 39 sends a read or write request from the CPU 6 to the enable C circuit 40. Also, the access detection circuit 41 confirms that the image data transfer circuit 35 has not read data from the memory bank C37 and reads or writes data from the selector circuit 39 to the enable C circuit 40 by the CPU 6 from the selector circuit 39. The request is sent to the bank C access circuit 36.

At this time, if the image data transfer circuit 35 has read the memory bank C37, the access detection circuit 41 waits until the image data transfer circuit 35 has finished reading the memory bank C37. Is sent to the bank C access circuit 36.

When a read or write request is sent from the access detection circuit 41, the bank C access circuit 36 reads or writes data from or to the memory bank C37.

Note that reference numerals 30, 31, and 3 in FIGS.
Lines denoted by reference numerals 2, 33, 34, 42, and 43 represent signal lines, respectively, but the description thereof is omitted here.

For example, when data from the host 1 is received,
At the same time, the image data transfer circuit 35 sends a print image to the printing mechanism 3, and at the same time, the CPU 6
It is assumed that data needs to be read from or written to T.13.

At this time, for example, the host data transfer circuit 8 supplies the memory bank A to the access detection circuit 41.
The image data transfer circuit 35 requests the access detection circuit 41 to permit data reading from the memory bank C37.

In this case, since the memory bank A12 and the memory bank C37 have not been read or written by the CPU 6, permission is immediately given to the host data transfer circuit 8 and the image data transfer circuit 35.
As a result, the host data transfer circuit 8 can write data to the memory bank A12, and the image data transfer circuit 35 can read data from the memory bank C37.

The bit (21, 20) of the address included in the read or write request from the CPU 6 is (1, 20).
0), a read or write request is sent from the selector circuit 39 to the bank B access circuit 15, and the memory bank B13 can be read or written.

As described above, in the present embodiment, the host 1
A memory bank A12 is allocated as a memory area used in a function of receiving data from the printer, a memory bank C37 is allocated as a memory area used in a function of transferring an image to be printed to the printing mechanism 3, and other functions are processed. The memory bank B13 is allocated as a memory area used by the CPU 6 for the
, A process of transferring an image to be printed to the printing mechanism 3, and other processes performed by the CPU 6 can be performed simultaneously. Thereby, the performance of the printer device 2 can be improved.

As described above, in each of the above-described embodiments, the controller 4 of the printer device 2 uses the functions of the printer device 2, for example, the data for printing supplied from the host 1. Memory 1
The functions such as writing to the memory 1 are performed by a memory bank A12 constituting the memory 11 of the controller 4 of the printer device 2,
It corresponds to the memory bank B13 and the memory bank C37, respectively. As described above, the memory area to be read or written by the predetermined function of the printer device 2 is defined as a memory bank A12, a memory bank B13, a memory bank C.
By allocating the data to a predetermined one of the memory banks A12, B13, and C37 by this function, the data is read from or written to a predetermined one of the memory banks C37. Data can be read from or written to a predetermined one.

In each of the above embodiments, an example in which the memory is divided into two and three memory banks has been described. However, the present invention is also applicable to the case where the memory is divided into four or more memory banks. Can be applied.

In the above embodiment, the contention of access to the memory bank is arbitrated by hardware, but the arbitration may be performed by software.

[0059]

As described above, according to the printer apparatus, the printer control method, and the recording medium according to the present invention, as the memory area used to realize the first function, a predetermined one of a plurality of memory banks is used. Is assigned exclusively, and the second function uses a predetermined one of the plurality of memory banks assigned to the first function.
When the function does not use the predetermined one of the plurality of memory banks, the second function is permitted to use the predetermined one of the plurality of memory banks, and the first function is used as the first function. When a second function does not use a predetermined one of the plurality of memory banks, a predetermined one of the plurality of memory banks allocated to the first function is used. Allow the use of certain
The present invention arbitrates a conflict that occurs when a predetermined one of the plurality of memory banks is used, and unconditionally permits the use of another predetermined one of the plurality of memory banks by the second function. Arbitration occurs when access to memory banks of the
Access to each memory bank can be performed in parallel, and the performance of the printer device can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of an embodiment of a printer device according to the present invention.

FIG. 2 is a block diagram illustrating a detailed configuration example of an arbitration circuit 9 of FIG. 1;

FIG. 3 is a block diagram illustrating a configuration example of another embodiment of the printer device of the present invention.

FIG. 4 is a block diagram illustrating a detailed configuration example of an arbitration circuit 69 of FIG. 3;

FIG. 5 is a block diagram illustrating a configuration of an example of a conventional printer device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Host 2 Printer device 3 Printing mechanism 4 Controller 6 CPU 7,57,67 Memory control circuit 8 Host data transfer circuit 9,45,69 Arbitration circuit 10 Bank A access circuit 11 Memory 12 Memory bank A 13 Memory bank B 15 Bank B Access circuit 24 Comparison circuit 25 Selector circuit 26 Enable A circuit 27 Access detection circuit 35 Image data transfer circuit 36 Bank C access circuit 37 Memory bank C 44 Bank selection circuit

Claims (7)

[Claims] 1. A printer device having a memory divided into a plurality of memory banks, wherein a predetermined one of the plurality of memory banks is exclusively allocated as a memory area used for realizing a first function. Allocating means, wherein the second function uses a predetermined one of the plurality of memory banks allocated to the first function;
When the first function does not use a predetermined one of the plurality of memory banks, the second function is permitted to use a predetermined one of the plurality of memory banks; Uses a predetermined one of the plurality of memory banks assigned to the first function,
When the second function does not use a predetermined one of the plurality of memory banks, the first function permits use of a predetermined one of the plurality of memory banks; Arbitration means for arbitrating a conflict that occurs when a predetermined one of the memory banks is used, wherein the arbitration means unconditionally permits the use of another predetermined one of the plurality of memory banks by the second function. A printer device. 2. A printer device having a memory divided into first and second memory banks, wherein the first access means accesses the first memory bank, and the second memory bank is accessed. A second access unit that receives data from a predetermined external device, accesses the first memory bank via the first access unit, and writes the data, and a predetermined function. Arbitrates when accessing the first memory bank via the first access means so as not to conflict with access to the first memo bank via the first access means by the data receiving means. And when the data receiving unit accesses the first memory bank via the first access unit, Arbitration means for arbitrating so as not to compete with access to the first memory bank via the access means, wherein the arbitration means is provided with the second function via the second access means by the predetermined function. A printer device which unconditionally permits access to a memory bank. 3. A printer device having a memory divided into first, second, and third memory banks, wherein the first access means accesses the first memory bank; and A second access unit for accessing a memory bank; a third access unit for accessing the third memory bank; receiving data from a predetermined external device, and receiving the data via the first access unit. A data receiving unit that accesses one memory bank and writes the data; a printing unit that prints the data received by the data receiving unit; and a third memory bank via the third access unit. A data transfer unit that reads data and transfers the read data to the printing unit; and a predetermined function is stored in the first memory bank via the first access unit. Arbitration so as not to conflict with access to the first memo bank via the first access unit by the data reception unit, and the data reception unit is configured to arbitrate the data via the first access unit. When accessing the first memory bank, arbitration is performed so as not to conflict with access to the first memory bank via the first access means by the predetermined function, and the predetermined function is executed by the third access bank. When accessing said third memory bank via means,
Arbitration is performed so as not to conflict with access to the third memo bank via the third access unit by the data transfer unit, and the data transfer unit is configured to arbitrate the third memory bank via the third access unit. Arbitration means for arbitration so as not to conflict with access to the third memory bank through the third access means by the predetermined function when accessing the predetermined function. A printer apparatus, wherein access to the second memory bank via the second access means is unconditionally permitted. 4. A printer control method for controlling a printer having a memory divided into a plurality of memory banks, wherein a predetermined area of the plurality of memory banks is used as a memory area used to realize a first function. Allocating dedicated ones of the memory banks, wherein the second function uses a predetermined one of the plurality of memory banks allocated to the first function;
When the first function does not use a predetermined one of the plurality of memory banks, the second function permits use of a predetermined one of the plurality of memory banks; Uses a predetermined one of the plurality of memory banks assigned to the first function,
When the second function does not use a predetermined one of the plurality of memory banks, the first function permits use of a predetermined one of the plurality of memory banks; Arbitration step of arbitrating a conflict that occurs when using a predetermined one of the following. In the arbitration step, by the second function,
A printer control method, wherein use of another predetermined one of the plurality of memory banks is unconditionally permitted. 5. A printer control method for controlling a printer having a memory divided into a first memory bank and a second memory bank, wherein a predetermined function accesses a first memory bank when the first function accesses the first memory bank. Receiving the data from the external device, arbitrating so as not to conflict with access to the first memory bank for writing the data, receiving the data from the external device, and writing the data; An arbitration step of arbitrating so as not to conflict with access to the first memory bank by the predetermined function when an access is made to one memory bank; and in the arbitration step, A printer control method, wherein access to a second memory bank is unconditionally permitted. 6. A printer device having a memory divided into first, second, and third memory banks, wherein the printer device receives data from a predetermined external device and accesses the first memory bank. A data receiving step of writing the data; a printing step of printing the data received in the data receiving step; a data transfer step of reading data from the third memory bank and transferring the data to the printing step; Arbitrates when accessing the first memory bank so as not to conflict with the access to the first memo bank in the data receiving step, and to access the first memory bank in the data receiving step. Is performed, the predetermined function accesses the first memory bank. Arbitration so as not to conflict with each other, and when the predetermined function accesses the third memory bank, arbitration so as not to conflict with access to the third memo bank in the data transfer step; And an arbitration step of arbitrating when the access to the third memory bank is performed so as not to conflict with the access to the third memory bank by the predetermined function. A printer control method, wherein access to the second memory bank is unconditionally permitted. 7. A recording medium on which a program capable of executing the printer control method according to claim 4 is recorded.