JP2000098001A - Test facilitation circuit - Google Patents

Abstract

(57) Abstract: A semiconductor integrated circuit with reduced circuit area overhead due to insertion of test points, and an analysis method for obtaining the same are provided. In a circuit under test 101, signal lines 111, 1 are provided.
21 and 131 are inserted, and the inserted signal lines 114, 124 and 134 are connected to the compression circuit 1 respectively.
41, and its output is connected to a flip-flop with a scan function via a signal line 142. Region 112,
122, 132 are signal lines 111, 121,
The range of signal lines traced to the input side from 131 to the scan FF groups 113, 123, 133 is the inspection point effect area of the observation point for the signal lines 111, 121, 131.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit in which area overhead due to inspection points is reduced, and a method of analyzing the same.

[0002]

2. Description of the Related Art One of techniques for facilitating test of semiconductor integrated circuits.
One method is to insert a test point into a circuit. In general,
The inspection points include “1 control point” for improving the ease of controlling the signal line to 1 (hereinafter, referred to as “1 controllability”) and ease of controlling the signal line to 0 (hereinafter, “0 controllability”). "Control point" for improving the ease of observing the signal value of the signal line (hereinafter referred to as "observability").
There is. In the case where 1 control point and 0 control point are not distinguished, they are simply called control points.

The circuit of the inspection point and the method of analyzing the insertion position are described in Proceeding of 2nd European Test Confe
"Test Points Insertion f" by B. Seiss et al., published on pages 253 to 262 of Rence (1991).
or Scan-Based BIST "and JP-A-6-331709," Circuits with Improved Testability and Methods for Improving Testability of Circuits ".

[0004] In particular, the method of analyzing inspection points described in the former document is based on COP (Controllability Observability).
A cost function is defined using a probabilistic testability measure called Procedure), and inspection points are determined one by one so as to minimize the cost function. That is, as a procedure for obtaining one inspection point, first, an inspection point candidate is selected based on an approximate value of the cost function when the inspection point is inserted, and an actual cost function when the inspection point candidate is inserted for each candidate. Is calculated, an inspection point candidate that minimizes the cost function is determined as an inspection point. This process is repeated for the number of inspection points. It has been experimentally confirmed that this inspection point analysis method is effective for facilitating the random number pattern test.

On the other hand, there are several methods for reducing the area overhead due to inspection points. In "Design for ease of inspection to achieve complete detection rate" in this document etc., published in Document 19 of the Information Processing Society of Japan Design Automation Study Group Material 19 (1983), a plurality of control points having the same output element It is described that controllable elements can be reduced by controlling by branching from one controllable element.
Also, literature Proceedingof International Test Conferen
“Modfying User-Defined Logic f” by B. Pouya et al., pp. 60-68 of ce (1997).
or Test Access to Embedded Cores ”, there is a sharing of test data input lines for control points. in this way,
By the implication operation from the insertion position of the control point to the input direction, the test data input line of the pair of control points that does not cause a new redundant fault even when shared is shared.

[0006]

Generally, in order to insert one test point into a circuit under test, it is necessary to add a flip-flop with a scan function dedicated to one test.
This leads to an increase in circuit area (hereinafter, referred to as area overhead). In particular, when the number of inspection points is large, there is a problem that the size of the area overhead cannot be tolerated.

Further, in the method described in the literature and the like in the conventional example and the method of B. Pouya et al., The area overhead due to the insertion of control points can be reduced, but the effect of reducing the area overhead of the entire inspection point including the observation point is insufficient. It is.

In view of the above problems, an object of the present invention is to provide a semiconductor integrated circuit in which the overhead of a circuit area due to insertion of a test point is reduced, and an analysis method for obtaining the same.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor integrated circuit having a plurality of observation points inserted in a circuit to be inspected. A signal line branched from a signal line in the circuit is connected to an input of a predetermined compression circuit, and each output of the compression circuit is connected to an external output element or an observable element such as a flip-flop with a scan function. This is achieved by converting a multi-bit signal value into a signal value with fewer bits than the input.

A signal line branched from a signal line in the circuit under test into which the observation point is inserted is finally connected to an external output element or an observable element such as a flip-flop with a scan function in the circuit under test. A compression circuit between the observation point and the observable element that receives the signal line and the signal line in the circuit under test as inputs, and a circuit that masks the logical value of the signal line used at the observation point during normal operation Achieved by

In a semiconductor integrated circuit in which a control point is inserted in a circuit under test, a signal line for inputting test data of the control point is finally connected to an external input element or a flip-flop having a scan function in the circuit under test. This is achieved by providing a circuit between the control point and the controllable element and masking a logical value of a signal line for inputting test data of the control point during normal operation.

Further, the signal line for inputting test data at a control point inserted into a signal line which is logically equivalent or the equivalent of the negation is made of the same external input element or a controllable element such as a flip-flop with a scan function. The above object is achieved by connecting to.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described.
This will be described with reference to the drawings.

FIG. 1 shows the configuration of a semiconductor integrated circuit according to the first embodiment in which the area overhead at the observation point is reduced. The semiconductor integrated circuit includes a circuit under test 101, an external input terminal or a scan chain input terminal 102, a pattern generator 103, a multiplexer 104, an input signal line 105 to the circuit under test 101, and a signal from the circuit under test. It comprises an output line 106, an external output terminal or a scan chain output terminal 107, and a pattern compressor 108. The multiplexer 104 selects one of the pattern of the external input terminal or the scan chain input terminal 102 and the pattern generator 103, and
Output to 5

The operation of the circuits around the circuit under test 101 will be described. First, BIST (built-in self test)
In the case of the pattern generator 10
3 is selected, and the signal line 105 is selected.
Is input to the circuit under test 101 through the
1 is tested. The pattern output from the circuit under test 101 is passed through a signal line 106 to a pattern compressor 108.
To compress the pattern. On the other hand, when a pattern is directly input / output from the tester, an external input terminal or a scan chain input terminal
The pattern input by the tester is selected, and the signal line 10
5 to the circuit under test 101 and the circuit under test 1
01 is tested. The pattern output from the circuit under test 101 is observed by a tester through a signal line 106, an external output terminal or a scan chain output terminal 107.

Before describing the circuit under test 101, test points will be briefly described with reference to FIG.
FIG. 8A is a logic circuit diagram before a test point is inserted, and is a flip-flop with a scan function (hereinafter, referred to as a scan FF).
Scan in 801-813, scan out 84
1,842, and EOR elements 821-824, BU
F elements 825 to 828, 832, 833, AND element 8
29, 830, 834, 835 and OR elements 831 and signal lines connecting them. FIG.
(B) is a logic circuit diagram after a test point is inserted.

For example, the BUF element 825 is replaced with the AND element 8
The conversion into 51 and scan FF 855 inserts 0 control points. That is, since the element 851 can be set to 0 by setting the signal value of the scan FF 855 to 0, it can be said that the 0 controllability of the output line of the element 851 is improved during the test. Note that during normal operation, the scan FF 855 is fixed at the signal value 1. Similarly, BUF elements 826 to 828
And AND elements 852-854 and scan FFs 856-8
Conversion to 58 is also zero control point insertion.

The BUF element 832 is an OR element 861
Is converted to the scan FF 863 to insert one control point. That is, since the element 861 can be set to 1 by setting the signal value of the scan FF 861 to 1, it can be said that the 0 controllability of the element 861 at the time of the test is improved. During normal operation, the scan FF 863 is fixed at a signal value of 0. Similarly, BUF element 833 is OR element 862
Is converted to scan FF 864 to insert one control point.

Returning to the description of the circuit under test 101, FIG. In the circuit under test 101, observation points for the signal lines 111, 121, 131 are inserted, and the inserted signal lines 11, 121, 131 are inserted.
4, 124 and 134 are connected to the compression circuit 141, and the output is connected to the scan FF 143 through the signal line 142. The regions 112, 122 and 132 are respectively connected to the scan FF groups 113 and 1 from the signal lines 111, 121 and 131, respectively.
This is a region of the signal line traced to the input side until it reaches 23, 133, and is a region for the signal lines 111, 121, 131. The observation point effect area is defined as a signal line area in which observability is improved by inserting observation points.

The operation of the circuit under test 101 during a test will be described. Here, the compression circuit 141 is configured as shown in FIG.
As shown in the above, a multi-input / one-output exclusive OR element is used. First, logical value patterns are set in the scan FF groups 113, 123, and 133. The signal values sequentially propagate in the output direction, and reach the signal lines 111, 121, and 131, respectively. The same signal value as the signal value on the signal line into which the observation point is inserted propagates through the signal lines 114, 124, and 134, and the compression circuit 1
The signal value which is input to 41 and exclusive ORed is observed by the scan FF 143. It is assumed that a different signal value (hereinafter, referred to as a fault signal) propagates to the signal line 111 during normal and fault conditions due to the presence of the fault in the region 112, and no fault signal propagates to the other signal lines 121 and 131. Then, a failure signal propagates to the scan FF 143.
This is because the observability does not change with the input / output of the exclusive OR, and when a failure signal enters one of the inputs, it can always be observed at the output.

In this embodiment, the scan FF conventionally required for each observation point is replaced by one scan FF 143, a compression circuit 141, and extension of wiring (signal lines 114, 124, 1).
34). In addition, the testability at this time is as follows. Assuming a single stuck-at fault model, scan FF
Is completely equivalent to the case where

In this embodiment, the scan FFs of the observation point groups whose observation point effect areas do not intersect with each other are shared, but the scan FFs of the observation points may be freely shared without considering the conditions. . However, in that case, a failure may occur in the area where the observation point effect areas intersect, and a failure signal may propagate to two observation point insertion positions. At this time, the failure signal may be extinguished by the compression circuit. . That is, the sharing of the scan FF without setting the condition of the observation point effect area slightly lowers testability. Of course, the reduction rate of the area overhead is larger than when the condition of the observation point effect area is considered.

As described above, by sharing the scan FFs of a plurality of observation points whose observation point effect areas do not intersect with each other, it is possible to reduce the area overhead due to the observation point insertion without lowering the testability. In addition, by sharing the scan FF of an arbitrary observation point, the area overhead due to the insertion of the observation point can be significantly reduced.

FIG. 2 shows a circuit example of the compression circuit 141.

Referring to FIG. 2A, as described above,
Observability can be maintained even with compression. In the case of the multi-input one-output NAND element shown in FIG. 2B, in order to observe a failure signal of one input at the output, the other input needs to be non-control logic (logical value 1 in the NAND element). You. Therefore, when the controllability of one of the input lines 114 to 134 to the compression circuit 141 is large, the observability of the input line is hardly reduced. When the above conditions are satisfied, a compression circuit using a NAND element is used. In general, since a NAND element can be configured with fewer transistors than exclusive OR,
It can be said that the area overhead can be further reduced as compared with the case (a).

FIG. 2C shows the compression circuit 141 when the input lines 114 and 124 have a large 1-controllability and the input line 134 has a large 0-controllability. To input line 134
By inserting the NOT element 232, all the input lines of the NAND element can be made to have a large controllability, and the observability of the input line does not need to be reduced.

FIG. 2D also shows an example similar to FIG. 2C. The input lines 114 and 124 have a large 0-controllability and the input line 13
Reference numeral 4 denotes a compression circuit 141 when the controllability is large. By inserting the NOT element 242 into the input line 134, all the input lines of the NOA element can be set to have a large 0-controllability, and the observability of the input line does not need to be reduced. As described above, a multi-input / one-output AND element or NA
Including ND element or OR element or NOR element,
By connecting a negation element immediately before each input line of the element according to the controllability of each input line of the compression circuit so that the controllability of the non-control logic value at each input line of the element becomes large. Further, the area overhead due to the insertion of the observation point can be further reduced without lowering the testability.

Regarding the above controllability and observability, when the test method is BIST (built-in self test), CO
It is common to use a stochastic testability measure of P. In this method, the controllability (1 controllability) is calculated from the input toward the output side according to the probability law, and the observability is calculated from the output toward the input side. If the test method inputs test generation patterns using a tester,
ldstain scale (reference IEEE Trans.on Circuits and Sys
LHGoldstain, published in tems (1979)
`` Controllability / Observability analysis of digit
al circuits ”).

FIG. 3 shows a configuration of a semiconductor integrated circuit according to the second embodiment in which the area overhead at the observation point is reduced. The peripheral circuits of the circuit under test 101 are the same as those in FIG.

In the circuit under test 101, the signal lines 111, 1
21 and 131 are inserted, and the inserted signal lines 114, 124 and 134 are connected to the compression circuit 1 respectively.
Connect to 41. Its output is sent through signal line 301 to AN
It is connected to the D element 302 and takes a logical product with the test mode signal line 303. Further, the output line 304 is input to the compression circuit 305 together with the signal line 311 in the circuit under test, and is connected to the scan FF 307 through the output line 306. Areas 112, 122, 132, and 312 are signal line areas traced to the input side from the signal lines 111, 121, 131, and 311 until reaching the scan FF groups 113, 123, 133, and 313, respectively.
Observation point effect area of observation points for 1, 121, 131,
And an observation point effect area of the scan FF 307 used in normal logic. The region 321 includes the observation point effect region 112,
A region of the signal line traced in the output direction from 122 and 132 to the scan FF group 322 is called an observation point quasi-influence region. The test mode signal line 303 has logical values of 1 at the time of test and 0 at the time of normal operation, and compresses signals from a plurality of observation points so that the signal value of the signal line 311 propagates correctly to the signal line 306 at the time of normal operation. The signal value on the signal line 301 is masked by the AND element 302.

In the observation point quasi-influence area, the observability changes only in the observation point effect area, but the observable elements in the circuit under test where the observation point and the observation point effect area do not cross each other are obtained. Is used in the case (for that reason, "quasi" is attached). In a certain observation point group, the observable elements in the circuit under test that do not belong to the union of the observation point quasi-influence areas of each observation point do not intersect with each other.

The operation of the circuit under test 101 during a test will be described. Here, the compression circuits 141 and 305 are exclusive OR elements as shown in FIG. First, logical value patterns are set in the scan FF groups 113, 123, and 133. The signal values sequentially propagate in the output direction, and reach the signal lines 111, 121, and 131, respectively. The same signal value as the signal value on the signal line into which the observation point has been inserted propagates through the signal lines 114, 124, and 134 and is input to the compression circuit 141.
Propagate to Since the logical value of the test mode signal line 303 is 1, the signal value of the signal line 301 propagates to the signal line 304 as it is. On the other hand, in the pattern set in the scan FF group 313, the signal value sequentially propagates in the output direction, and the signal line 311
To reach. The two signal values of the signal lines 304 and 311 are compressed to one bit by the compression circuit 305 and observed by the scan FF 307 used in normal logic. If it is assumed that a fault exists in the area 112 and a fault signal propagates to the signal line 111 and no fault signal propagates to the other signal lines 121, 131, and 311, the fault signal propagates to the scan FF 307. Further, if a fault exists in the area 312 and a fault signal propagates to the signal line 311, the other signal lines 11
Assuming that the fault signal does not propagate to 1, 121 and 131, the fault signal propagates to the scan FF 307.

The operation of the circuit under test 101 during normal operation will be described. First, the scan FF groups 113, 123,
In the pattern of the logical value set to 133, the signal value is sequentially propagated in the output direction, and the signal lines 111, 121,
Reach 131. The same signal value as the signal value on the signal line where the observation point is inserted propagates through the signal lines 114, 124, and 134 and is input to the compression circuit 141, and the signal value obtained by performing an exclusive OR operation propagates to the signal line 301. I do. However, since the logical value of the test mode signal line 303 is 0, the signal value of the signal line 304 becomes 0 regardless of the signal value of the signal line 301. Therefore, in the compression circuit 305, the signal value of the signal line 311 is propagated as it is to the signal line 306, and is observed by the scan FF 307.

In this embodiment, a scan FF dedicated to an observation point, which is conventionally required for each observation point, is replaced with a compression circuit 141,
305, an AND element, and a test mode signal line 303;
Extension of wiring (signal lines 114, 124, 134) is sufficient,
It is not necessary to insert any scan FF dedicated to the observation point.
Further, the testability at this time is completely equivalent to the case where a scan FF is provided for each observation point, assuming a single stuck-at fault model. However, the path of the normal logic (signal line 31)
1 to 306), there is a problem that a signal delay increases because a compression circuit is inserted.

In this embodiment, the observation point and the normal logic scan FF whose observation point effect areas do not intersect are shared, but the observation point and the normal logic scan FF are freely shared without considering the conditions. May be. However, in that case, a failure may occur in the area where the observation point effect areas intersect, and a failure signal may propagate to two observation point insertion positions. At this time, the failure signal may be extinguished by the compression circuit. . That is, the sharing of the scan FF without setting the condition of the observation point effect area slightly lowers testability. Of course, the reduction rate of the area overhead is larger than when the condition of the inspection point effect area is considered.

As described above, by sharing the observation point where the observation point effect areas do not intersect with each other and the scan FF of the normal logic, it is possible to reduce the area overhead due to the insertion of the observation point without lowering the testability.

FIG. 4 shows a configuration of a semiconductor integrated circuit according to the third embodiment in which the area overhead of control points is reduced. The peripheral circuits of the circuit under test 101 are the same as those in FIG.

In the circuit under test 101, the 0 control points 415 and 421 for the signal line 411 and the 1 control points 425 and
0 control point 435 for 431 is inserted, and 0 controllability and 1 controllability of signal lines 412, 422, and 432, respectively.
Controllability and 0 controllability are improved. The test data signal of each control point is supplied from one signal line 464. The signal line 464 is a scan FF used in normal logic.
An AND element 46 having a signal line 461 branched from an output line 451 of the 455 and a test mode signal line 462 as inputs.
3 is an output line. The test mode signal line 462 has logical values of 1 during test and 0 during normal operation, and the test data signal is used as a non-control logical value of the element used at the control point so that the function of each control point disappears during normal operation. In this case, NOT logics 416 and 436 are inserted. Regions 413 and 42
3, 433 and 453 are signal lines 412 and 42, respectively.
Scan FF groups 414 and 42 from 2,432 and 452
In the area of the signal line traced to the output side until it reaches 4,434,454, the control point effect area of the control point for the signal lines 411, 421, 431 and the control point effect area of the scan FF 455 used in normal logic is there. Region 44
Reference numeral 1 denotes a signal line area traced in the input direction from the control point effect areas 413, 423, and 433 to the scan FF group 422, which is called a control point influence area. The test mode signal line 462 has a logical value of 1 at the time of test and 0 at the time of normal operation. A signal value on the signal line 461 obtained by compressing signals from a plurality of observation points is masked by the AND element 463.

The control point influence area 441 is an area where controllability or observability changes, and includes the control point effect area. This is used to find a controllable element in a circuit under test where the control point and the control point effect area do not cross each other. In a certain control point group, controllable elements in the circuit under test that do not belong to the union of the control point influence areas of the control points do not intersect with each other.

The operation of the circuit under test 101 during a test will be described. First, a logical value pattern is set in the scan FF group 442. The signal values sequentially propagate in the output direction, and reach the signal lines 411, 421, and 431, respectively.
One of the signal values set in the scan FF 455 used in the normal logic is one of the signal lines 451 and 452 and the area 45.
3 and reaches the scan FF group 454. On the other hand, since the signal value of the test mode signal line 462 is 1, the signal value of the scan FF 455 propagates through the signal line 461 to the signal line 464 as it is. And each control point 41
Used as test data input to 5,425,435,
The signal lines 412, 422, 432 and the region 4 respectively
Scan FF groups 414, 4 passing through 13, 423, 433
24,434.

The operation of the circuit under test 101 during normal operation will be described. First, a logical value pattern is set in the scan FF group 442. The signal values sequentially propagate in the output direction, and reach the signal lines 411, 421, and 431, respectively. One of the signal values set in the scan FF 455 used in the normal logic reaches the scan FF group 454 through the signal lines 451, 452, and the area 453. On the other hand, since the signal value of the test mode signal line 462 is 0, the signal value of the scan FF 455 is masked by the AND element 463 and the signal value of the signal line 464 is always 0. Since the control points 415, 425, and 435 receive 1, 0, and 1, which are non-control logic values of the respective element types, as test data inputs, the signal lines 411, 421, and 431
Are signal lines 412, 422, and 432, respectively.
Propagate as it is.

In this embodiment, the scan FF dedicated to the control point, which is conventionally required for each control point, is replaced by the test mode signal line 462, the AND element 463, and the extension of the wiring (signal line 46).
4), and no scan FF dedicated to the control point needs to be inserted. The testability at this time is exactly the same as the case where a scan FF is provided for each control point.

In this embodiment, the control point and the normal logic scan FF where the inspection point effect areas do not intersect are shared, but the control point and the normal logic scan FF are freely shared without considering the conditions. May be. However, in this case, a failure may occur on the input side of the area where the control point effect area intersects, and the failure signal may disappear due to the reconvergence structure formed by sharing the scan FF. That is, the sharing of the scan FF without setting the condition of the control point effect area slightly lowers testability. Of course, the reduction rate of the area overhead is larger than when the condition of the control point effect area is considered.

As described above, by sharing the control point where the control point effect areas do not cross each other and the scan FF of the normal logic, the area overhead due to the insertion of the control point can be reduced without lowering the testability.

FIG. 5 shows a circuit example in which the area overhead of the control points according to the fourth embodiment is reduced.

FIG. 5A shows an example of a circuit before inserting a test point. When a control point is inserted, there is a method of permitting only replacement for a specific cell in order to suppress signal delay overhead. Here, the case where control points can be inserted
Only the replacement of the elements 511, 512, 513 with AND elements or OR elements is limited. At this time, the OR element 501
In order to further improve the 0 controllability on the output side, FIG.
(b) AND element 52 functioning as a control point
1, 522, 523 and scan FFs 524, 525,
526 is inserted. However, as shown in FIG. 5C, when the scan FF of each control point is shared by the scan FF 534, the scan FF dedicated to the control point, which is three in FIG. 5B, becomes 1 in FIG. 5C. It only needs an individual. As for testability, when it is desired to set the output line of the OR element 501 to 0, the scan FFs 524 and 52 in FIG.
It is necessary to set all signal values of 5,526 to 0,
In the case of FIG. 5C, the signal value of the scan FF 534 is set to 0.
5C can be said to have better controllability of the output line of the OR element 501 in FIG. 5C than in FIG. 5B. The case of FIG. 5C is substantially equivalent to the case of FIG. 5D in which a zero control point is inserted into the output line of the OR element 501. Is modeled as shown in FIG.

As described above, by sharing the scan FF of the control point for the signal line input to the same element, it is possible to reduce the area overhead due to the insertion of the control point without lowering the testability.

FIG. 6 shows a circuit example in which the area overhead of the control points according to the fifth embodiment is reduced.

FIG. 6A shows an example of a circuit before inserting a test point. Here, in order to suppress the signal delay due to the insertion of the control point, the case where the control point can be inserted is described in the BUF elements 611, 612,
613 is limited to the replacement with the AND element or the OR element. At this time, in order to improve the 1 controllability of the BUF elements 611 and 612 and the 0 controllability of the BUF element 613, it is necessary to use FIG.
(B) AND element 62 functioning as a control point
1, 622, 623 and scan FFs 624, 625,
626 is inserted. However, as shown in FIG. 6C, when the scan FF of each control point is shared by the scan FF 634, the scan FF dedicated to the control point, which is required three in FIG. 6B, becomes 1 in the case of FIG. 6C. It only needs an individual. As for testability, when it is desired to set the output lines of the BUF elements 611 and 612 to the signal values 1 and 613 to the signal value 0, the scan FFs 624, 625 and 626 in FIG.
Need to be set to 1, 1, and 0, respectively, but in the case of FIG. 6C, it is only necessary to set the signal value of the scan FF 534 to 0. In the case of FIG. 6C, the zero control point is substantially inserted into the output line of the OR element 601.
Since it is equivalent to the case of (d), the control point dedicated scan F
In analyzing the sharing of F, modeling is performed as shown in FIG.

As described above, by sharing the scan FF of the control point for the logically equivalent signal line, the area overhead due to the insertion of the control point can be reduced without lowering the testability.

FIG. 7 shows the flow of the method of calculating the groups that can be shared by the scan FFs described above.

In step 701, circuit information and information on a test point which has been determined are input. First, step 70
In step 2, for each control point, by tracing from the signal line at the insertion position to the output direction, the output line has a signal line that is not equivalent to the signal line at the control point insertion position or that is not the negative logic. Calculate the set of elements close to the position. In step 703, for each control point, by tracing from the signal line at the insertion position to the input direction, the input line includes a signal line that is not equivalent to the signal line at the control point insertion position and that is not a negative logic. Calculate the element close to the insertion position. In step 704, a group of control points where the set of elements obtained in step 702 coincides is obtained and set to the same group. In step 705, a group of control points having the same set of elements obtained in step 703 is obtained and set to the same group.

Steps 706 to 709 are analyzes based on the conditions of the control point effect area of the control point and the observation point effect area of the observation point. The control point effect area and the observation point effect area are collectively called an inspection point effect area.
In step 706, the inspection point effect area of each inspection point or each inspection point group is calculated. In step 707, based on the result of step 706, an inspection point or an inspection point group that has the same inspection point type (control point or observation point) and whose inspection point effect areas do not intersect with each other is obtained. Set to. In step 709, for each inspection point or each inspection point group, a control point influence area is calculated for a control point, and an observation point quasi-influence area is calculated for an observation point.
Scan FFs used as normal logic in 01
One is selected as a controllable element at the control point or an observable element at the observation point. Finally, at step 710,
Output the grouping information of each inspection point.

Hereinafter, a specific example of processing and a circuit example in this embodiment will be described using an example of a semiconductor integrated circuit.

FIG. 8 shows an example of the logic circuit before the insertion of the test point (FIG. 8A) and an example of inserting the test point into it (FIG. 8B), as described above. Six control points and two observation points are inserted, and the number of scan FFs dedicated to inspection points is eight.

FIG. 10A shows information obtained by performing the processing of steps 701 to 705 of FIG. 7 on the plurality of inspection points of FIG. 8B. Column 1001 is the inspection point number, column 1002
Is the number of the scan FF element used at the inspection point, row 100
Reference numeral 3 denotes a test point type. A column 1004 indicates the number of the output element calculated in step 702, and a column 1005 indicates the number of the input element calculated in step 703. In a column 1006, a group ID is set for each inspection point, and information indicating that a scan FF may be shared when the same group ID is used. ,
Test points 5 and 6 with the same output element are assigned the same group ID
Set 2.

FIG. 9A shows a logic circuit in which the area overhead due to the insertion of test points is reduced using the information shown in FIG. The group of control points with group ID 1 is
The signal value of the scan FF 902 is shared, and the signal is branched to each control point 851 to 854 by the signal line 901. Group ID
The group of two control points shares the signal value of the scan FF 912, and the control points 861 and 862 are connected by the signal line 911.
Branch to

FIG. 10B shows information obtained by performing the processing of steps 706 to 709 in FIG. 7 on the plurality of inspection points in FIG. 9A. Column 1011 is the inspection point number, column 1012
Is the number of the scan FF element used at the inspection point, column 101
3 is an inspection point type, a column 1014 shows element numbers included in an inspection point effect area, a column 1015 shows an element number included in a control point influence area for a control point, and an element number included in an observation point quasi observation area for an observation point. Listed. A column 1016 is information indicating that a group ID is set for each inspection point, and that the scan FF may be shared when the group ID is the same. In the inspection points 1 and 2, the control point effect area intersects (elements 834 and 841), so that they cannot be set in the same group. Since the observation point effect areas do not intersect with the inspection points 3 and 4, the same group ID 3 is set. Column 1017 lists the numbers of scan FFs used in normal logic that can be shared as elements that can be controlled or observed. The inspection point 1 is a control scan FF 80 not included in the control point influence area.
9, 810 and 811 can be selected as scan FFs that can be shared. Since the control point influence area of the inspection point 2 includes the scan FFs 801 to 813 for all controls, there is no scan FF that can be shared. Inspection points 3 in the same group
In No. 4, there is no scan FF that can be shared because those observation point quasi-influence areas include scan FFs 841 and 842 for all observations.

FIG. 9B shows a logic circuit in which the area overhead due to the insertion of test points is reduced using the information shown in FIG. 10B. The control point group of group ID1 shares the scan FF 812 used for normal logic as a controllable element, branches to a signal line 922 at a branch point 921, and performs a logical AND with the test mode signal line 923.
Via the ND element 924, the signal line 901 branches to control points 851 to 854. The group of observation points of the group ID 3 is transmitted to the scan F via the compression circuit 931.
Observe at F932. In the circuit created in this way, there are two scan FFs dedicated to inspection points. FIG.
The number of scan FFs dedicated to test points is reduced to 1/4 as compared with the circuit example of FIG. 4B, and it can be seen that the area overhead due to test point insertion can be significantly reduced.

As described above, in the semiconductor integrated circuit according to the present invention, by sharing the scan FF for the observation point and the scan FF for the control point, the overhead of the circuit area can be reduced without changing the effect of facilitating the test. .

[0061]

According to the present invention, a scan FF for an observation point is provided.
It is an object of the present invention to provide a semiconductor integrated circuit in which the overhead of the circuit area due to the insertion of the inspection point is reduced by sharing the scan FF for the control point and the analysis method for sharing the scan FF.

[Brief description of the drawings]

FIG. 1 is a configuration example of a semiconductor integrated circuit according to the first invention, in which the area overhead at an observation point is reduced.

FIG. 2 is a circuit diagram showing an embodiment of a compression circuit.

FIG. 3 is a configuration example of a semiconductor integrated circuit according to the second invention in which the area overhead at the observation point is reduced.

FIG. 4 is a configuration example of a semiconductor integrated circuit according to a third invention in which the area overhead of control points is reduced.

FIG. 5 is a circuit example for reducing an area overhead of a control point according to the fourth invention.

FIG. 6 is an example of a circuit for reducing an area overhead of a control point according to the fifth invention.

FIG. 7 is a flowchart showing a processing procedure for obtaining a semiconductor integrated circuit of the present invention.

FIG. 8 is a circuit diagram of a semiconductor integrated circuit in which test points are inserted.

FIG. 9 is a circuit diagram of a semiconductor integrated circuit in which test points are inserted according to one embodiment of the present invention.

FIG. 10 is an example of a table in a process for obtaining a semiconductor integrated circuit according to the present invention.

[Explanation of symbols]

101: circuit to be inspected, 112, 122, 132 ... area,
141 ... compression circuit.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Kazumi Hatakeyama 7-1-1, Omikacho, Hitachi City, Ibaraki Prefecture Inside the Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Seiji Kobayashi 7-chome, Omikamachi, Hitachi City, Ibaraki Prefecture No. 1-1 F-term in Hitachi Laboratory, Hitachi, Ltd. F-term (reference) 2G032 AA01 AA04 AB20 AC04 AD05 AG01 AG04 AK15 5F038 DT02 DT04 DT06 DT07 DT08 EZ10 EZ10 EZ20

Claims (13)

[Claims] 1. A semiconductor integrated circuit in which a plurality of observation points are inserted into a circuit under test, wherein the plurality of observation points are divided into predetermined groups, and a multi-bit signal output from each of the groups is provided. A semiconductor integrated circuit having at least one compression circuit that outputs a signal having a small number of bits to an external output element or an observable element such as a flip-flop having a scan function. 2. The observation point group connected to the compression circuit according to claim 1, wherein the observation point effect area, which is an area in which observability is improved by inserting each observation point, is separated from each other. Semiconductor integrated circuit. 3. A semiconductor integrated circuit having an observation point inserted in a circuit under test, wherein a multi-bit circuit is provided between the observation point and an observable element such as an external output element or a flip-flop with a scan function. A semiconductor integrated circuit comprising: a compression circuit that converts a signal into a signal with a small number of bits; and a circuit that masks a logical value of a signal line used at the observation point. 4. An observation point effect area in which observability is improved by inserting observation points and an area where a signal propagates to an observable element in a circuit under test. Semiconductor integrated circuit. 5. The semiconductor integrated circuit according to claim 1, wherein said compression circuit is a circuit having a function of exclusive OR of multiple inputs and one output or a function of negating the exclusive OR. 6. The compression circuit according to claim 1, wherein the compression circuit includes a multi-input, one-output AND element or N
An AND element, an OR element, or a NOR element, which is controlled according to the controllability of each input line of the compression circuit so that the controllability of the non-control logic value of the element at each input line of the element is increased. A semiconductor integrated circuit, wherein a negation element is connected immediately before each input line of the element. 7. A semiconductor integrated circuit in which a control point is inserted in a circuit under test, wherein a signal line for inputting test data of the control point and an external input element or a flip-flop with a scan function in the circuit under test are controlled. A semiconductor integrated circuit having a circuit between a possible element and a mask for masking a logical value of a signal line for inputting test data of a control point in a normal operation. 8. A semiconductor device according to claim 7, wherein a control point effect region, which is a region in which controllability is improved by inserting a control point, and a region in which a signal propagates from a controllable element in the circuit under test, do not cross each other. Integrated circuit. 9. A semiconductor integrated circuit having a plurality of control points inserted in a circuit under test, wherein a signal line for inputting test data at a control point inserted into a signal line which is logically equivalent or the equivalent thereof is provided. ,
A semiconductor integrated circuit connected to the same external input element or a controllable element such as a flip-flop with a scan function. 10. A method for obtaining a group of observation points in a case where insertion positions of a plurality of observation points are already determined in a circuit under test, wherein the observation point effect area is calculated for each observation point. An observation point group calculation method for a semiconductor integrated circuit, comprising: a first step; and a second step of obtaining a group of observation points where the observation point effect areas do not intersect each other. 11. A method for obtaining observable elements in a circuit under test when an insertion position of at least one observation point in the circuit under test has already been determined. First to calculate the observation point quasi-influence area, which is the area where the signal propagates from the effect area to the output direction
And a second step of selecting an observable element in the circuit under test which is not included in the observation point quasi-influence area. 12. The method for calculating a controllable element in a circuit under test according to claim 8, wherein the insertion positions of a plurality of control points in the circuit under test have already been determined. A first step of calculating, for each control point, a control point-influence area, which is an area in which a signal propagates from the control point-effect area in an input direction; And a second step of selecting an appropriate element. 13. A method for determining a group of control points that can be connected to the same controllable element when a plurality of control point insertion positions have already been determined in a circuit under test. On the other hand, by tracing from the signal line at the insertion position to the output direction, a set of elements that are closest to the insertion position and have a signal line that is not equivalent to the signal line at the control point insertion position or a logic that is not its negative logic on the output line. A first step of calculating, a second step of obtaining a group of control points having the same set of elements obtained in the first step, and a trace from the signal line at the insertion position to the input direction for each control point Thus, the third step of calculating an element closest to the insertion position, which includes a signal line that is not equivalent to the signal line at the control point insertion position and a signal line that is not its negative logic in the input line, and the third step Elemental A method of calculating a control point group of a test point of a semiconductor integrated circuit, comprising a fourth step of obtaining a group of control points having the same set.