JP2000091545A - Semiconductor device and semiconductor storage device - Google Patents

Abstract

(57) Abstract: The most important feature of the present invention is to enable a source region to be connected more reliably in a nonvolatile semiconductor memory device employing an STI structure for element isolation. For example, a shallow first buried element isolation insulating film and a second buried element isolation insulating film deeper than the first buried element isolation insulating film on a surface portion of a P-type silicon substrate. An element isolation region 24 comprising
To form Then, the first buried element isolation insulating film 2
After removing 2, impurity ions are implanted into the bottom and the source region of the memory cell transistor. Thus,
By lowering the aspect ratio of the first buried element isolation insulating film 22 so that a diffusion layer can be sufficiently formed even on the side wall portion of the trench, a continuous N ⁺ type source region serving as the source line SL is formed. 19 is made possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device employing an STI (Shallow Trench Isolation) structure for element isolation.

[0002]

2. Description of the Related Art Conventionally, as a method for electrically isolating cell transistors in a memory cell portion of a nonvolatile semiconductor memory device, a LOCOS method (selective oxidation method) using field oxidation is known.

[0005] FIG. 25 shows a structure obtained by adopting the LOCOS method.
2 schematically shows a configuration of a memory cell section of a nonvolatile semiconductor memory device. FIG. 3A is a plan view showing a pattern seen through the inside, and FIG.
A sectional view taken along the line b, and FIG.
FIG. 4D is a cross-sectional view taken along line dd in FIG. 4A, and FIG. 5E is a cross-sectional view taken along line ee in FIG.

For example, a plurality of memory cell transistors are formed on a P-type silicon substrate 101 in a matrix. Each memory cell transistor has a floating gate electrode 103 formed on the P-type silicon substrate 101 via a gate insulating film 102 and a control gate formed on the floating gate electrode 103 via an inter-gate insulating film 104. An electrode 105 and N ⁺ -type drain regions 106 formed on the surface of the P-type silicon substrate 101, respectively.
And an N ⁺ type source region 107.

The N ⁺ type drain region 106 is shared by two adjacent memory cell transistors in the column direction, and a bit line ( (Not shown).

In the N ⁺ type source region 107, all adjacent memory cell transistors are connected to each other in the row direction, and are shared as a source line SL.

The memory cell transistors in the row direction are electrically separated from each other by a field oxide film 110 formed on the surface of the P-type silicon substrate 101 by using the LOCOS method. I have.

In the case of such a memory cell portion in which element isolation is performed by the LOCOS method, as means for connecting the N ⁺ type source regions 107 to each other, for example,
After removing the field oxide film 110 between the source regions of the memory cell transistors, a method of forming a continuous N ⁺ -type source region 107 serving as the source line SL by ion-implanting impurities into the P-type silicon substrate 101 Is adopted.

At present, there is a demand for an increase in the degree of integration of a memory cell transistor due to a demand for a large capacity of a semiconductor memory device. One of the methods is a trench isolation method capable of reducing the area of an element isolation region. The adoption of is being considered.

As the element isolation technique, since there is no problem of bird's beak like a field oxide film, LOCO
The trench isolation method is more effective for miniaturization than the S method.

FIG. 26 shows an STI as a trench isolation method.
1 schematically shows a configuration of a memory cell portion of a nonvolatile semiconductor memory device having a structure. FIG. 2A is a plan view of the pattern seen through the inside, FIG. 2B is a cross-sectional view taken along the line bb of FIG. 2A, and FIG. (D) is a cross-sectional view taken along line dd in FIG. (A), and FIG. (E) is a cross-sectional view taken along line ee in FIG. (A). FIG.

In the case of this memory cell portion, for example, a space between the memory cell transistors having the above-described structure is formed on the surface portion of the P-type silicon substrate 101 by using a trench isolation method instead of the field oxide film 110. By the formed embedded element isolation insulating film 210 having the STI structure,
It is electrically isolated.

According to the memory cell portion having such a configuration,
Since the bird's beak does not occur, the width of the buried element isolation insulating film 210 can be reduced, and the LOCOS
The memory cell transistor can be highly integrated as compared with the method.

However, the buried element isolation insulating film 210 is generally made of RIE (Reactive Ion Etching).
A trench is formed on the surface of the P-type silicon substrate 101 by anisotropic etching by a method or the like, and an insulating material (embedding material) is embedded in the trench.

For this reason, as shown in FIG. 1D, for example, it is difficult to continuously form the N ⁺ type source regions 107 of all the adjacent memory cell transistors in the row direction. there were.

That is, the trench is formed substantially perpendicular to the P-type silicon substrate 101. As a result, as a means for connecting the N ⁺ -type source regions 107 to each other, in the above-described ion implantation method, formation of a diffusion layer on the side wall portion of the trench groove tends to be insufficient, so that the source line SL is formed. It becomes difficult to form a continuous N ⁺ type source region 107.

[0017]

As described above, in the related art, when the STI structure is adopted, although the memory cell transistor can be highly integrated, a continuous N ⁺ type source region is formed by the ion implantation method. There is a problem that the formation of the film becomes difficult.

Accordingly, an object of the present invention is to provide a semiconductor device and a semiconductor memory device capable of forming a continuous diffusion layer and improving reliability without impairing the insulating characteristics of element isolation. And

[0019]

In order to achieve the above object, in a semiconductor device according to the present invention, an element isolation formed by a first trench having a first depth in a semiconductor substrate is provided. And an element isolation region formed by a second trench having a second depth, which is deeper than the first trench, and wherein the first trench has a depth of It is configured to be equal to or less than the depth of the diffusion layer formed in the element region of the semiconductor substrate.

In a semiconductor memory device according to the present invention, a semiconductor substrate and a memory cell formed on the semiconductor substrate and having an element isolation region formed by a first trench having a first depth. And a peripheral circuit portion provided on the semiconductor substrate and having an element isolation region formed by a second trench having a second depth that is deeper than the first trench.

Further, in the semiconductor memory device of the present invention, an element isolation region formed by a semiconductor substrate, a first trench provided on the semiconductor substrate and having a first depth, and And a memory cell unit provided with an element isolation region formed by a second trench having a second depth, which is deeper than the first trench.

According to the semiconductor device and the semiconductor memory device of the present invention, it is possible to sufficiently form the diffusion layer even on the side wall of the trench. Thus, in a portion where a continuous diffusion layer is formed, the diffusion layers can be connected to each other continuously.

More specifically, an element isolation region having a trench structure is formed with two or more depths, and at least
By making the shallow element isolation region correspond to the portion where the continuous diffusion layer is formed, the diffusion layer can be formed continuously.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic configuration of a memory cell section of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. FIG. 3A is a plan view of the pattern seen through the inside, and FIG.
A cross-sectional view taken along the line B, and FIG.
(D) is a cross-sectional view along the line DD in FIG. (A), and FIG. (E) is a cross-sectional view along the line EE in FIG. (A). (F) is a cross-sectional view along the line FF in FIG.

For example, a plurality of memory cell transistors are formed in a matrix on a P-type silicon substrate (semiconductor substrate) 11. Each memory cell transistor is formed on the P-type silicon substrate 11 via a gate insulating film 12 via a gate insulating film 12 and on the floating gate electrode 13 via an inter-gate insulating film (ONO film) 14. The control gate electrode (word line) 15, an N ⁺ -type drain region 17 formed in an island shape on one of the surface portions of the P-type silicon substrate 11 via a P-type pocket region 16, and the P-type silicon substrate 11. An N ⁺ -type source region (diffusion layer) 19 formed in a stripe shape via an N ^-- type source region 18 on the other surface of the silicon substrate 11.

The floating gate electrode 13 is divided into a plurality of parts by a slit part 13a in the row direction, and is provided for each memory cell transistor.

The control gate electrode 15 is provided integrally in the row direction so as to be shared by all the memory cell transistors in the row direction.

The N ⁺ -type drain region 17 is shared by two adjacent memory cell transistors in the column direction, and a bit line ( (Not shown).

In the N ⁺ type source region 19, all the memory cell transistors are connected to each other in the row direction, and are shared as a source line SL.

Then, the P-type silicon substrate 1 corresponding to between the memory cell transistors adjacent in the row direction.
1 is formed on the surface by using a trench isolation method.
An element isolation region 24 composed of two types of embedded element isolation insulating films 22 and 23 having different STI structures with different depths is formed.

That is, each memory cell transistor in the row direction has a first buried element isolation insulating film (first trench) 22 having a first depth, and
It is electrically isolated by a second buried element isolation insulating film (second trench) 23 having a second depth.

The first buried element isolation insulating film 22
, Said N ⁺ -type source region 19 to the extent that there is no conflict in forming connected to the row direction depth, for example, the N ⁺
The same as or shallower than the depth of the mold source region 19,
The N ⁺ type source region 1 having a depth of about 0.15 μm;
9 (between the source regions of the memory cell transistors).

The N ⁺ -type source region 19 is formed, for example, by the first buried element isolation insulating film 22.
Is removed, an N-type impurity is implanted into the P-type silicon substrate 11 by an ion implantation method or the like, and heat treatment is performed.

The second buried element isolation insulating film 23
Is a depth that does not impair the insulation characteristics of element isolation,
For example, deeper than the N ⁺ -type source region 19 has a depth of about 0.4 .mu.m, the N ⁺ -type drain region 17
Are formed substantially corresponding to the formation positions (between the drain regions of the memory cell transistors).

In short, the element isolation region 24 is formed, for example, such that the first and second elements are separated from each other at a substantially central portion between the floating gate electrode 13 and the control gate electrode 15. Embedded element isolation insulating film 22,
23 are formed.

The regions corresponding to each other between the device isolation regions 24 are device regions 25 in which memory cell transistors are formed.

According to the above-described structure, by limiting the depth of the element isolation region (first buried element isolation insulating film 22) 24 provided corresponding to the source region of the memory cell transistor, N ⁺ Type source region 19
Can be formed efficiently.

That is, the depth of the first buried element isolation insulating film 22 formed between the source regions of the memory cell transistors is limited to the same or less than the depth of the N ⁺ type source region 19. I have.

For this reason, even if the side wall portion of the trench for forming the first buried element isolation insulating film 22 is formed substantially perpendicular to the P-type silicon substrate 11. , The diffusion layer can be sufficiently formed on the side wall by the ion implantation method.
^{The +} type source region 19 can be connected efficiently (without increasing the resistance).

Next, a method of manufacturing the nonvolatile semiconductor memory device having the above-described configuration will be described with reference to FIGS. Here, a non-volatile semiconductor memory device in which the memory cell unit having the above configuration and its peripheral circuit unit (not shown) are mixedly described will be described as an example.

First, for example, as shown in FIG.
A gate insulating film 12 having a thickness of about 100 Å is formed on the entire surface of the P-type silicon substrate 11. Also,
An amorphous silicon layer (or phosphorus-doped polysilicon) 31 is deposited on the gate insulating film 12 to a thickness of about 600 angstroms.

Next, as shown in FIG. 3, for example, after forming an SiN film 32 having a thickness of about 1500 angstroms on the amorphous silicon layer 31, a thickness of about 1500 angstroms is further formed on the SiN film 32. A TEOS (Tetra Ethoxy Silane) film 33 is deposited by a CVD (Chemical Vapor Deposition) method.

Next, as shown in FIG. 4, for example, a resist film is applied on the TEOS film 33 and is patterned by photolithography to form a resist pattern (FIG. (FIG. 4 corresponds to the cross section along the DD line and the cross section along the FF line (or the EE line), respectively).

Then, using the resist pattern as a mask, the TE
The OS film 33 and the SiN film 32 are etched to expose the amorphous silicon layer 31 thereunder.

Then, after removing the resist pattern, as shown in FIG.
Of these, the portion (corresponding to the cross section along the DD line described above) corresponding to the formation position of the first buried element isolation insulating film 22 (between the source regions of the memory cell transistors) is covered with the resist film 34. .

Then, a portion corresponding to the formation position of the second buried element isolation insulating film 23 (between the drain regions of the memory cell transistors) (the above-mentioned FF line or E).
The amorphous silicon layer 31 and the gate insulating film 12 (corresponding to the cross section along the -E line) are removed by anisotropic etching using the TEOS film 33 as a mask. Expose the surface.

At this time, the surface of the P-type silicon substrate 11 is similarly exposed by the above-described anisotropic etching to the portion corresponding to the formation position of the element isolation region in the peripheral circuit portion.

Next, as shown in FIG. 6, for example, after the resist film 34 is removed, anisotropic etching is performed using the TEOS film 33 as a mask to expose the second buried element isolation insulating film 23. The P-type silicon substrate 11 at a portion corresponding to the formation position is removed, and a groove 35 is formed on the surface thereof. At the same time, the amorphous silicon layer 31 in a portion corresponding to the position where the first buried element isolation insulating film 22 is formed is removed.

In this case, the etching at the portion corresponding to the position where the first buried element isolation insulating film 22 is formed is as follows:
After removing the amorphous silicon layer 31 described above,
Stop at the gate insulating film 12. Therefore, the etching of the groove 35 at a portion corresponding to the formation position of the second buried element isolation insulating film 23 can be advanced to a desired depth.

Incidentally, together with the formation of the trench for forming the first buried element isolation insulating film 22 later, finally, the second buried element isolation insulating film 23 is formed.
The etching of the groove 35 here is adjusted so that the depth of the trench groove for forming the trench becomes a desired depth.

Next, as shown in FIG. 7, for example, the portion of the gate insulating film 12 corresponding to the position where the first buried element isolation insulating film 22 is formed is etched to form the P-type silicon substrate 11. After exposing the surface,
This time, the P-type silicon substrate 11 is etched to form the shallow trench groove 36 for forming the first buried element isolation insulating film 22 and the second buried element isolation insulating film 23. Deep trenches 37 are formed respectively.

In this case, the shallow trench groove 36 is formed to have the same depth as the N ⁺ type source region 19 formed in the source region of the memory cell transistor.

The deep trench 37 is formed by further etching the trench 35 by the depth of the shallow trench 36, and the depth thereof is set to be equal to the depth of the shallow trench 36. It is almost equal to the sum of the depth.

Next, as shown in FIG. 8, for example, an insulating material (filling material) 38 is deposited on the entire surface, and the inside of the shallow trench groove 36 and the inside of the deep trench groove 37 are filled with the insulating material 38.

Next, as shown in FIG. 9, for example, using the amorphous silicon layer 31 as a stopper,
A part of the insulating material 38 including the TEOS film 33 and the SiN film 32 is removed by a (chemical mechanical polishing) method.

In this manner, the insulating material 38 is left in the shallow trench groove 36 and the deep trench groove 37, respectively, so that the shallow first buried element isolation insulating film 22 is formed between the source regions of the memory cell transistors. And a deep second buried element isolation insulating film 23 is formed between the drain regions of the memory cell transistors.

At this time, in the peripheral circuit portion, similarly, a trench having the same depth as the deep trench 37 is formed, and the insulating material 3 is inserted into the trench.
As a result, the element isolation region is formed at the same depth as the second embedded element isolation insulating film 23.

After the first buried element isolation insulating film 22 and the second buried element isolation insulating film 23 are formed in this manner, the formation of the floating gate electrode 13 and the control gate electrode 15 are performed. Is performed to form a memory cell transistor.

That is, for example, as shown in FIG.
Amorphous silicon is deposited on the entire surface, and the thickness of the amorphous silicon layer 31 is adjusted to the value of the floating gate electrode 13.
To the thickness required for the formation of

Next, as shown in FIG. 11, for example, the amorphous silicon layer 31 having an increased thickness is divided for each element region 25, and is divided on the first buried element isolation insulating film 22 and the second buried element isolation insulating film 22. Element isolation insulating film 2
The slits 13a are formed on each of the three.

Next, as shown in FIG. 12, for example, after forming the slit portion 13a, an insulating film (ONO film) 39 for forming the inter-gate insulating film 14 on the entire surface.
Is deposited.

Next, as shown in FIG. 13, for example, after forming the insulating film 39, a poly or amorphous silicon film 40 for forming the control gate electrode 15 is deposited on the entire surface.

FIG. 11A corresponds to the cross section along the line FF described above, and FIG.
-A cross section along the line B (the element isolation region 24),
FIG. 3C corresponds to the cross section (the element region 25) along the line CC described above.

Next, as shown in FIG. 14, for example, a resist pattern 41 for forming the floating gate electrode 13, the control gate electrode 15, and the like is formed on the silicon film 40.

Then, using the resist pattern 41 as a mask, the silicon film 40, the insulating film 39, and
Each of the amorphous silicon layers 31 is etched to form the floating gate electrode 13 and the inter-gate insulating film 1.
4 and the control gate electrode 15 are formed.

At this time, as shown in FIG. 9A, in the element isolation region 24 corresponding to the cross section along the line BB, for example, the floating gate electrode 13 and the control gate electrode 15 A substantially central portion thereof is formed so as to be exactly at a boundary between the depth of the first buried element isolation insulating film 22 and the depth of the second buried element isolation insulating film 23.

Then, as shown in FIG. 15, for example, a portion of the element isolation region 24 other than the position where the N ⁺ type source region 19 is formed is covered with a resist film 42.
Using the control gate electrode 15 as a mask, the first buried element isolation insulating film 22 is etched in a self-aligned manner,
The underlying P-type silicon substrate 11 is exposed.

Next, as shown in FIG. 16, for example, the gate insulating film 12 exposed between the control gate electrodes 15 on the element region 25 corresponding to the source region and the drain region of the memory cell transistor is formed. Then, the P-type silicon substrate 11 is exposed.

In order to form a source line SL connecting a plurality of memory cell transistors in a self-aligned manner,
After the drain region of the memory cell transistor is covered with a resist film (not shown) or the like, N ⁻ -type impurities and N ⁺ -type impurities are implanted by ion implantation, respectively, and heat treatment is performed. The N ⁻ -type source region 18 and the N ⁺ -type source region 19 are continuously formed on the bottom of the first buried element isolation insulating film 22.

At this time, the depth of the shallow trench groove 36 for forming the first buried element isolation insulating film 22 is limited as described above. Therefore, even if the side wall portion of the shallow trench groove 36 is formed substantially perpendicular to the P-type silicon substrate 11, the formation of the diffusion layer by ion implantation into the side wall portion is not required. As a result, the N ⁺ -type source region 19 can be efficiently connected and formed.

After the source region of the memory cell transistor is covered with a resist film (not shown) or the like so that the impurity is not implanted, a P-type impurity and an N ⁺ -type impurity are implanted by ion implantation, respectively. To form the P-type pocket region 16 and the N ⁺ -type drain region 17 in the drain region of the memory cell transistor.

Thus, a plurality of memory cell transistors are formed in a matrix. Thereafter, the interlayer insulating film 21 is deposited on the entire surface to planarize the surface, and then the contact portion 20 connected to the N ⁺ type drain region 17 is formed, and the memory having the structure shown in FIG. A cell part is manufactured.

The memory cell section having the above-described structure is completed as a memory cell section of a nonvolatile semiconductor memory device by further forming a bit line connected to the contact section 20.

As described above, a sufficient diffusion layer can be formed also on the side wall of the trench.

That is, the element isolation region having the trench structure is formed with two or more types of depths, and at least the portion where the continuous source region is formed is made to correspond to the shallow first buried element isolation insulating film. Like that.

Thus, in a portion where a continuous source region is formed, the first buried element isolation insulating film is formed almost perpendicular to the P-type silicon substrate, but the source of the adjacent memory cell transistor is formed. The regions can be connected continuously.

Further, an existing, deep second buried element isolation insulating film is formed as an element isolation region for the drain region and the peripheral circuit portion of the memory cell transistor. Therefore, the breakdown voltage of the element does not deteriorate.

Therefore, a continuous source region can be formed by the ion implantation method without impairing the insulating characteristics of element isolation, and the reliability can be improved.

In the first embodiment of the present invention, a shallow first buried element isolation insulating film is formed only in the source region of the cell transistor in the memory cell portion. In the drain region and the peripheral circuit portion of the second embedded element isolation insulating film deeper than the first embedded element isolation insulating film is described as an example, but is not limited to this,
It is also possible to form a shallow first buried element isolation insulating film in the memory cell portion and a deep second buried element isolation insulating film in the peripheral circuit portion.

In this case, there is a concern that the formation of the shallow first buried element isolation insulating film in the drain region of the memory cell transistor in the memory cell portion slightly lowers the breakdown voltage. By forming the region 16, it is possible to secure a required breakdown voltage.

FIG. 17 shows a second embodiment of the present invention. In particular, a shallow first buried element isolation insulating film is formed in a memory cell portion, and a second buried element is formed deep in a peripheral circuit portion. 13 shows another method for manufacturing a nonvolatile semiconductor memory device, which is suitable for use when an isolation insulating film is formed.

That is, when a shallow first buried element isolation insulating film is formed in a memory cell portion and a deep second buried element isolation insulating film is formed in a peripheral circuit portion thereof, the method according to the first embodiment described above is used. For example, the memory cell unit 5
1 and the peripheral circuit portion 52
And the formation of the deep trench groove 37 can be performed collectively. Here, for simplification of description, only a method for forming the shallow trench groove 36 and the deep trench groove 37 will be described.

First, for example, as shown in FIG.
The memory cell portion 51 for forming the shallow first buried element isolation insulating film 22 is covered with a resist film 53. Further, a resist pattern 54 for forming a deep trench groove 37 is formed on the P-type silicon substrate 11 in the peripheral circuit section 52 where the deep second buried element isolation insulating film 23 is formed.

Then, as shown in FIG. 9B, anisotropic etching such as RIE is performed using the resist pattern 54 as a mask to form the second buried element isolation insulating film 23 at the formation position. P of the corresponding part
The mold silicon substrate 11 is removed, and a deep trench 37 is formed on the surface thereof. Then, after forming the deep trench groove 37, the resist film 53 and the resist pattern 54 are removed.

As a result, a deep trench 37 for forming the deep second buried element isolation insulating film 23 in the peripheral circuit section 52 is formed on the surface of the P-type silicon substrate 11 on the peripheral circuit section 52. Formed.

Next, as shown in FIG. 9C, the peripheral circuit portion 52 in which a deep trench groove 37 for forming a deep second buried element isolation insulating film 23 is formed is resisted. Covered by membrane 55.

Further, in the memory cell portion 51 where the shallow first buried element isolation insulating film 22 is formed, a shallow trench groove 36 is formed on the P-type silicon substrate 11.
A resist pattern 56 is formed.

Next, as shown in FIG. 11D, the resist pattern 56 is used as a mask and anisotropic etching such as RIE is performed to correspond to the position where the first buried element isolation insulating film 22 is formed. By etching the P-type silicon substrate 11 in a part,
6 is formed. Then, after forming the shallow trench groove 36, the resist film 55 and the resist pattern 56 are removed.

As a result, a shallow trench groove 36 for forming the shallow first buried element isolation insulating film 22 with respect to the memory cell portion 51 is formed on the surface of the P-type silicon substrate 11 on the memory cell portion 51. Formed.

As described above, the resist pattern 5 is formed when the shallow trench groove 36 is formed in the memory cell portion 51 and when the deep trench groove 37 is formed in the peripheral circuit portion 52.
Only by changing 4, 56, a shallow trench groove 36 for forming the first buried element isolation insulating film 22 and a deep trench groove 37 for forming the second buried element isolation insulating film 23 can be easily formed. Can be made separately.

It is to be noted that the present invention is not limited to the case where the deep trench groove 37 is formed first, and it is of course possible to form the shallow trench groove 36 first.

FIGS. 18 to 22 show a method of manufacturing a nonvolatile semiconductor memory device according to the third embodiment of the present invention. Here, as another method for forming a shallow trench groove and a deep trench groove without using an amorphous silicon layer for forming a floating gate electrode as described in the first embodiment, ,
A case where a shallow trench groove and a deep trench groove are formed in a memory cell portion will be described as an example.

In this case, for example, as shown in FIG.
First, a gate insulating film 12 having a thickness of about 100 Å is formed on the entire surface of a P-type silicon substrate 11.
After forming a SiN film 32 having a thickness of about 1000 angstroms on the gate insulating film 12 by the CVD method, a TEOS film 33 having a thickness of about 1000 angstroms is further formed on the SiN film 32 by the CVD method. Is deposited.

Then, a resist film is applied on the TEOS film 33 and is patterned by photolithography to form a resist pattern 61 for forming the element isolation region 24.

Next, as shown in FIG. 19, using the resist pattern 61 as a mask, the TEOS film 33 is patterned by anisotropic etching such as RIE, and the underlying SiN film 32 is exposed.

After removing the resist pattern 61, a portion of the element isolation region 24 corresponding to the formation position of the first buried element isolation insulating film 22 (between the source regions of the memory cell transistors) is removed. Membrane 62
To cover.

Next, as shown in FIG. 20, for example, the SiN film 32 at a position corresponding to the formation position of the second buried element isolation insulating film 23 (between the drain regions of the memory cell transistors) is replaced with the TEOS film. The gate insulating film 12 is exposed by removing it by anisotropic etching using the resist film 33 and the resist film 62 as a mask.

Then, the gate insulating film 12 exposed at the portion corresponding to the formation position of the second buried element isolation insulating film 23 is removed by etching, and the P
After exposing the mold silicon substrate 11, the resist film 6
Remove 2.

Then, as shown in FIG. 21, for example, the TEOS film 33 and the SiN
Using the film 32 as a mask, the P-type silicon substrate 11 is anisotropically etched to form a groove 35 in a portion corresponding to a position where the second buried element isolation insulating film 23 is exposed.

In this case, the second buried element isolation insulating film 23 is finally formed together with the later formation of the shallow trench groove 36 for forming the first buried element isolation insulating film 22. The etching of the groove 35 here is adjusted so that the depth of the deep trench groove 37 to be formed becomes a desired depth.

Next, as shown in FIG. 22, for example, the patterned SiN film 32 and the gate insulating film 12 which are present in the portion corresponding to the position where the first buried element isolation insulating film 22 is formed are etched. Then, the P-type silicon substrate 11 thereunder is exposed.

Thereafter, using the TEOS film 33 as a mask,
The P-type silicon substrate 11 is etched. At this time, the depth of the shallow trench groove 36 for forming the first buried element isolation insulating film 22 is substantially equal to the depth of the N ⁺ type source region 19 formed in the source region of the memory cell transistor. Is controlled so as to have a depth of.

Thus, the shallow trench groove 36 for forming the first buried element isolation insulating film 22 and the second buried element isolation insulating film 23 having a different depth from the shallow trench groove 36 are formed. A deep trench groove 37 for forming can be formed.

FIG. 23 shows a method of manufacturing a nonvolatile semiconductor memory device according to the fourth embodiment of the present invention. Here, a method of forming a shallow trench groove and a deep trench groove will be described by taking as an example a case where a shallow trench groove and a deep trench groove are formed in a memory cell portion.

In this case, a resist film having a desired thickness is first formed on the entire surface of the P-type silicon substrate 11, as shown in FIG. The resist film is patterned by photolithography to form a resist pattern 71 for forming the element isolation region 24.
To form

Next, as shown in FIG. 13B, the P-type silicon substrate 11 is subjected to anisotropic etching such as RIE using the resist pattern 71 as a mask.
Is etched to form the first buried element isolation insulating film 2
2 is formed.

After forming the shallow trench 36,
The resist pattern 71 is removed.

Next, as shown in FIG. 11C, of the region (element isolation region 24) where the shallow trench groove 36 is formed, the position (memory cell) where the first buried element isolation insulating film 22 is formed (Between the source regions of the transistors).
1 is covered with a resist film 72.

Then, as shown in FIG. 11D, the second buried element isolation insulating film 23 except for the position where the first buried element isolation insulating film 22 is formed is formed using the resist film 72 as a mask. In the portion corresponding to the formation position (between the drain regions of the memory cell transistors)
The mold silicon substrate 11 is further etched to form a deep trench groove 37 for forming the second buried element isolation insulating film 23.

Finally, as shown in FIG. 11E, by removing the resist film 72, a shallow trench groove 36 for forming the first buried element isolation insulating film 22 and the shallow trench groove 36 are formed. A deep trench 37 for forming the second buried element isolation insulating film 23, which is different in depth from the trench 36, can be formed.

As described above, the method of connecting the source regions of the memory cell transistors is not limited to the usual ion implantation method in which an impurity is implanted perpendicularly to the P-type silicon substrate. The angle of ion implantation with respect to the silicon substrate is 15 degrees, 30 degrees,
You may make it incline like 45 degrees.

In short, when the source region of the memory cell transistor is formed, the angle of the impurity implantation in the ion implantation method is set so that a continuous source region can be efficiently formed. What is necessary is just to perform it at the angle which can form a diffusion layer more reliably with respect to a part.

The method of connecting the source regions of the memory cell transistors is not limited to the ion implantation method, but may be formed by, for example, a solid phase diffusion method. That is, it can be formed almost in the same way by burying arsenic glass in which arsenic is doped into glass in a shallow trench groove, and subjecting the arsenic glass to heat treatment to diffuse arsenic in a solid phase.

In the case where a shallow trench groove and a deep trench groove are formed in the memory cell portion, for example, as shown in FIG. 24, the side wall portions of trench grooves 36 and 37 are formed on P-type silicon substrate 11. The present invention is not limited to the case where the trench is formed so as to be substantially perpendicular thereto, and the deep trench groove 37 may be formed with at least a desired taper angle.

In this case, not only is the filling property of the burying material in the deep trench groove 37 for forming the second buried element isolation insulating film improved, but also the memory cell is formed by ion implantation or solid phase diffusion. The connectivity of the source region of the transistor can also be improved.

Further, the present invention is not limited to a nonvolatile semiconductor memory device. For example, a diffusion layer is formed in a trench for forming an element isolation region having an STI structure, and the diffusion layer is used as a wiring. Of the present invention.

In addition, it is needless to say that various modifications can be made without departing from the scope of the present invention.

[0119]

As described above, according to the present invention, it is possible to form a continuous diffusion layer without deteriorating the insulating characteristics of element isolation and improve the reliability. A semiconductor memory device can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a configuration of a memory cell section of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is also a schematic cross-sectional view for explaining the method for manufacturing the nonvolatile semiconductor memory device.

FIG. 3 is also a schematic cross-sectional view for explaining the method for manufacturing such a nonvolatile semiconductor memory device.

FIG. 4 is also a schematic cross-sectional view shown for explaining the method for manufacturing such a nonvolatile semiconductor memory device.

FIG. 5 is also a schematic cross-sectional view for explaining the method for manufacturing such a nonvolatile semiconductor memory device.

FIG. 6 is also a schematic cross-sectional view shown for explaining the method for manufacturing such a nonvolatile semiconductor memory device.

FIG. 7 is also a schematic cross-sectional view for explaining the method for manufacturing such a nonvolatile semiconductor memory device.

FIG. 8 is also a schematic cross-sectional view for explaining the method for manufacturing such a nonvolatile semiconductor memory device.

FIG. 9 is also a schematic cross-sectional view for explaining the method for manufacturing such a nonvolatile semiconductor memory device.

FIG. 10 is also a schematic cross-sectional view shown for explaining the method for manufacturing such a nonvolatile semiconductor memory device.

FIG. 11 is also a schematic cross-sectional view for explaining the method for manufacturing the nonvolatile semiconductor memory device.

FIG. 12 is also a schematic cross-sectional view for explaining the method for manufacturing the nonvolatile semiconductor memory device.

FIG. 13 is also a schematic cross-sectional view for explaining the method for manufacturing the nonvolatile semiconductor memory device.

FIG. 14 is also a schematic cross-sectional view shown for explaining the method for manufacturing such a nonvolatile semiconductor memory device.

FIG. 15 is also a schematic cross-sectional view for explaining the method for manufacturing the nonvolatile semiconductor memory device.

FIG. 16 is also a schematic cross-sectional view for explaining the method for manufacturing the nonvolatile semiconductor memory device.

FIG. 17 is a schematic cross-sectional view for explaining another method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 18 is a perspective view for schematically illustrating still another method for manufacturing a nonvolatile semiconductor memory device according to the third embodiment of the present invention.

FIG. 19 is also a perspective view schematically illustrating still another method for manufacturing such a nonvolatile semiconductor memory device.

FIG. 20 is also a perspective view schematically illustrating another method for manufacturing such a nonvolatile semiconductor memory device.

FIG. 21 is a perspective view for explaining the outline of still another method for manufacturing such a nonvolatile semiconductor memory device.

FIG. 22 is a perspective view for explaining an outline of still another method for manufacturing such a nonvolatile semiconductor memory device.

FIG. 23 is a schematic perspective view for explaining still another manufacturing method of the nonvolatile semiconductor memory device according to the fourth embodiment of the present invention;

FIG. 24 is a sectional view schematically showing another shape of the trench for forming the first and second buried element isolation insulating films according to the first to fourth embodiments of the present invention.

FIG. 25 is a schematic view of a nonvolatile semiconductor memory device, for illustrating a conventional technique and its problems.

FIG. 26 is a schematic view showing another example of the configuration of a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

11 ... P-type silicon substrate 12: gate insulating film 13 ... floating gate electrode 13a ... slit 14 ... gate insulating film 15 ... control gate electrode 16 ... P-type pocket regions 17 ... N ⁺ -type drain region 18 ... N ^- -type source Region 19 ... N ⁺ type source region 20 ... Contact part 21 ... Interlayer insulating film 22 ... First buried device isolation insulating film 23 ... Second buried device isolation insulating film 24 ... Device isolation region 25 ... Device region 31 ... Amorphous silicon Layer 32 SiN film 33 TEOS film 34 Resist film 35 Groove 36 Shallow trench groove 37 Deep trench groove 38 Insulating material 39 Insulating film 40 Silicon film 41 Resist pattern 42 Resist film 51 Memory cell Part 52: Peripheral circuit part 53: Resist film 54: Resist pattern 55: Resist film 56: Resist Turn 61 ... resist pattern 62 ... resist film 71 ... resist pattern 72 ... resist film SL ... source line

Continuing from the front page (72) Inventor Seiji Yamada 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside the Toshiba Yokohama Office (72) Inventor Kazuki Isobe 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Corporation F-term in Toshiba Tamagawa Factory (reference) 5F001 AA04 AA25 AA34 AA43 AA63 AB04 AB08 AD17 AD18 AD19 AD23 AD60 AF10 5F032 AA34 AA35 DA33 5F083 EP09 EP23 EP55 EP56 EP64 EP68 JA04 JA33 MA06 MA20 NA01 PR37 PR40

Claims (14)

[Claims] An element isolation region formed in a semiconductor substrate by a first trench having a first depth, and
An element isolation region formed by a second trench having a second depth, which is deeper than the first trench, wherein the first trench has an element depth of the semiconductor substrate. A semiconductor device having a depth equal to or less than a depth of a diffusion layer formed in a region. 2. The semiconductor device according to claim 1, wherein the diffusion layer is provided continuously by an ion implantation method in a portion of the first trench and a portion of an element region of the semiconductor substrate separated by the first trench. The semiconductor device according to claim 1, wherein: 3. The semiconductor device according to claim 1, wherein said second trench has a depth greater than a depth of a diffusion layer formed in an element region of said semiconductor substrate. 4. The first and second trenches vary in depth from a gate electrode provided on the semiconductor substrate substantially orthogonal to the first and second trenches. The semiconductor device according to claim 1, wherein: 5. A semiconductor substrate, a memory cell portion provided on the semiconductor substrate and having an element isolation region formed by a first trench having a first depth, provided on the semiconductor substrate, And a peripheral circuit portion having an element isolation region formed by a second trench having a second depth, which is deeper than the first trench. 6. The semiconductor memory device according to claim 5, wherein a depth of said first trench is equal to or less than a depth of a source diffusion layer of said memory cell portion. 7. The semiconductor memory device according to claim 6, wherein said source diffusion layers are formed by an ion implantation method, and are connected to each other via a portion of said first trench. 8. The semiconductor memory device according to claim 5, wherein said second trench has a depth greater than a depth of a source diffusion layer of said memory cell portion. 9. An element isolation region provided on the semiconductor substrate and formed by a first trench having a first depth, and a second isolation region deeper than the first trench. A semiconductor memory device, comprising: a memory cell portion provided with an element isolation region formed by a second trench having a depth. 10. The semiconductor memory device according to claim 9, further comprising a peripheral circuit portion provided on said semiconductor substrate and having an element isolation region formed by said second trench. 11. The first trench has a depth of:
10. The semiconductor memory device according to claim 9, wherein the depth is equal to or less than the depth of the source diffusion layer of the memory cell portion. 12. The semiconductor memory device according to claim 11, wherein said source diffusion layers are formed by an ion implantation method, and are connected to each other via a portion of said first trench. 13. The second trench has a depth of:
11. The semiconductor memory device according to claim 9, wherein a depth of the drain diffusion layer in the memory cell portion is greater than a depth of the drain diffusion layer. 14. The semiconductor device according to claim 1, wherein the depth of the first and second trenches changes at a boundary of a gate electrode provided substantially perpendicular to the first and second trenches. 10. The semiconductor memory device according to item 9.