JP2000090662A - Semiconductor integrated circuit - Google Patents

Abstract

(57) Abstract: The operation frequency of a semiconductor device having a circuit in which the number of circuits to be activated changes and the operation timing of which changes in accordance with the number of circuits is constant, and the operation frequency is improved. SOLUTION: A plurality of circuits 20-0 to 20-n which operate in parallel according to a timing signal clko and can be set to an operation state and a non-operation state, respectively, and a plurality of circuits respectively according to an operation mode And a timing adjustment circuit 21 that adjusts a timing signal according to the number of circuits in an operation state among a plurality of circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a plurality of circuits that operate in parallel according to a timing signal, and the number of circuits that operate in parallel changes according to an operation mode. The present invention relates to a semiconductor integrated circuit, such as an eggplant dynamic random access memory (SDRAM), which operates in synchronization with an external clock and has a variable data width of input / output data.

[0002]

2. Description of the Related Art In a semiconductor device, a circuit is formed so as to realize a plurality of types of functions in one chip for reasons such as cost reduction and prompt response to market demands. A circuit to be operated is selected by changing an internal wiring state. For example,
Higher integration is being promoted in semiconductor storage devices such as DRAMs. However, if the storage capacity per semiconductor device is increased due to the higher integration, the conventional 1-bit data width is not easy to use. Is generally multi-bit. In DRAM, 1 bit, 4 bits,
There are products with various data widths (bit widths) such as 8-bit and 16-bit. However, the parts such as the memory cell array are shared and the data input / output unit is selectively used according to the data width. 2. Description of the Related Art Various types of chips are used to support products having a plurality of data widths. The data width can be set after setting the data width in the internal circuit before shipping.
In some cases, the data width can be arbitrarily set by an external identification signal and the data width can be changed during operation.

In order to increase the data width, it is necessary that a plurality of memory cells corresponding to the data width can access the same address. As a configuration method, for example, a method of activating a plurality of column lines and / or word lines for one address, a method of configuring a memory cell with a plurality of blocks, and accessing a plurality of blocks simultaneously And methods combining these.

When the data width is changed, a part of the input / output data is made possible so that a part of the write (input) data is not written into the memory cell at the time of data write, and the data is read at the time of data read. Data must not be output to some of the output terminals. Here, such a process is referred to as masking.
To mask at the time of data writing, it is necessary not to write the data to be masked to the memory cell, and it is necessary not to activate the word line, the column line, or both. Therefore, masking of write data is performed in a portion such as an address decoder. When masking is performed on a block basis, access to the block to be masked may be stopped.

On the other hand, the mask at the time of data reading does not cause any problem even if normal access is performed to each memory cell. Therefore, only the output of data from some data output circuits is stopped. Is fine. Even when masking is performed on a block basis, it is necessary to stop outputting data from the output circuit of each block. FIG. 1 is a diagram showing a configuration example of a portion related to an output circuit of a dynamic random access memory (DRAM) that can set such a data width. This configuration example is a synchronous (synchronous) type DRAM which has recently been put to practical use as a technique for speeding up.
This is called a synchronous dynamic random access memory (SDRAM). This is to increase the speed by inputting a clock signal from the outside and synchronizing the data input / output and internal operation with the clock signal, and to perform intermediate operations by multi-stage pipeline operation. It is.

As shown in FIG. 1, each block 8-0 to 8-8
-N has the memory cell array 1, the sense amplifier 17, and the data amplifier 18. In addition, other elements such as an address decoder (row decoder / column decoder), a driver, and a write amplifier, which are the same as those of a normal DRAM, are omitted here. Furthermore, each block 8-
Data output circuits 20-0 to 20- corresponding to 0 to 8-n
n is provided. At the time of reading, the memory cell designated by the address signal in the memory cell array 1 is accessed, and the stored data is amplified by the sense amplifier 17 and further amplified by the data amplifier 18 and output as complementary data. This complementary data is input to the output circuit. The input complementary data is input to transfer gates 44 and 45 via inverters 41 and 42. The transfer gates 44 and 45 open during a period when the output timing signal clko is “high (H)”, and transmit the outputs of the inverters 41 and 42 to the flip-flop constituted by the inverters 46 and 47 and 48 and 49. Inverter 4
The outputs of 1 and 42 are determined by the time transfer gates 44 and 45 open,
Are opened and transmitted to the two flip-flops, the output transistors 50 and 51 become in a state corresponding to the output data, and the data is output to the terminals 53-0 to 53-n. The transfer gates 44 and 45 are closed while the output timing signal clko is "low" (L), and the two flip-flops maintain the state at the time when the transfer gates 44 and 45 are closed until the next time the transfer gates 44 and 45 are opened. I do. The output timing signal clko is a signal synchronized with the clock.

Whether to mask the data output from this block is controlled by a mask control signal dm. dm is "H"
In the case of, the transfer gates 44 and 45 operate according to the output timing signal clko to output data, and when the dm is "L", the transfer gates 44 and 45 operate.
And 45 are always closed, and no data is output. dm is generated by a control circuit (not shown). The control circuit receives the mask data from the outside and outputs dm for each block according to the contents.

Here, a configuration for masking output data will be briefly described with reference to FIG. Block 8-0
8-3 and four sets of output circuits 20-0 to 20-3 are provided. This part is commonly manufactured regardless of product specifications. As shown in FIG. 2A, in the case of a product in which the number of blocks and output circuits and the number of data output terminals 53-0 to 53-3 match, each output circuit 20-0 to 0-3 is used.
20-3 is a corresponding data output terminal 53-0 to 53-3
Connected to. As shown in FIG. 2B, in the case of a product in which one data output terminal 53 is provided for four sets of blocks 8-0 to 8-3 and output circuits 20-0 to 20-3, As shown, the outputs of blocks 8-0 to 8-3 are set to 1
Output circuits 20-0 only.
To the data output terminal 53. In this case, dm input to the output circuits 20-1 to 20-3 is set to "L" so that output from the output circuits 20-1 to 20-3 is not performed.

To enable the data width to be arbitrarily set by an external identification signal, the dm input to each of the output circuits 8-0 to 8-3 is controlled by the configuration shown in FIG. I do. In any case, when the data width is changed, the number of activated output circuits changes according to the data width.

[0010]

In the conventional SDRAM, the output timing signal clko is constant regardless of the number of activated output circuits. However, when the number of activated output circuits changes, a difference occurs in power supply voltage drop or noise, so that even if the same output timing signal clko is supplied to the output circuit, data is output from the output circuit. The time until it changes. FIG.
Is a diagram showing a change in output data with respect to the output timing signal clko, Dout shows a change in output data when the output data width is small and the number of activated output circuits is small, and Dout 'shows an output data. FIG. 11 shows changes in output data when the data width is large and the number of activated output circuits is large. As shown in the figure, when the number of activated output circuits is large, the drop in power supply voltage and noise are large. Therefore, the time t2 from the rising of the output timing signal clko to the change of the output data is equal to the activated output circuit. It is longer than the time t1 when the number of circuits is small. When the number of activated output circuits is small, the reset time of the output data is short, and as a result, the data holding time is short. As described above, when the output timing signal clko is constant, there is a problem that the output timing of the output data differs depending on the number of activated output circuits.

Normally, the clock frequency is determined in consideration of the timing difference of the output data depending on the number of output circuits to be activated, which is an obstacle to speeding up the clock. Such a problem is not limited to the SDRAM, and a similar problem occurs in a semiconductor device having a circuit in which the number of activated circuits changes and the operation timing changes accordingly.

An object of the present invention is to solve such a problem and improve the operating frequency of a semiconductor device.

[0013]

In order to achieve the above object, the semiconductor device of the present invention adjusts a timing signal supplied to those circuits according to the number of circuits to be activated. That is, the semiconductor device of the present invention operates in parallel in response to a timing signal, and includes a plurality of circuits each of which can be set to an operation state and a non-operation state; and
A control circuit that sets each of the plurality of circuits to an operation state and a non-operation state; and a timing adjustment circuit that adjusts a timing signal according to the number of circuits in an operation state among the plurality of circuits. And

The control circuit has an operation mode storage circuit for determining the operation mode from an external mode identification signal when the operation mode can be set from the outside, and storing the operation mode set in the semiconductor device. In this case, the operation mode is determined by reading the operation mode from the operation mode storage circuit. The above problem occurs mainly in a data output circuit, and the present invention is applied to an output circuit of a semiconductor device having a variable data width, particularly to a data output circuit of a synchronous dynamic random access memory (SDRAM). It is effective. In that case, the timing adjustment circuit delays the output timing signal applied to the data output circuit when the number of active data output circuits is small compared to when the number is large.

With the above configuration, SD can be set according to the data width.
Even when the number of activated output circuits of the RAM changes, the data output timing can be kept constant, and the operating frequency can be improved.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to a synchronous dynamic random access memory (SDRA).
An embodiment applied to the data output circuit of M) will be described. However, the present invention is not limited to this, and can be similarly applied to a semiconductor device having a circuit in which the number of activated circuits changes and the operation timing changes accordingly.

The DRAM chip according to the first embodiment of the present invention comprises:
It is assumed that the output data width can be switched between 16 bits, 8 bits, and 4 bits. That is, 16 memory cells can be accessed in parallel, and 16 data output circuits are provided. The output data width is set externally, and the data output circuit is accordingly set to an activated state and an inactivated state. Here, it is assumed that the DRAM is composed of 16 blocks, and when the output data width is 16 bits, the corresponding memory cells in the 16 blocks are accessed in parallel. However, a configuration is also possible in which four of the sixteen blocks are accessed in parallel, and in each block, four memory cells are accessed in parallel.

FIG. 4 shows an SDRAM according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing the entire configuration of the embodiment. As shown, the address signal input from the address port 11 is supplied to the row decoder 3 and the column decoder 14 of each bank. A row selection signal output from the row decoder 3 is applied to each word line 15 via the word line driver 2 to activate a word line (selected word line) to which a memory cell to be accessed is connected, and to activate other word lines. (Non-selected word line) is kept in an inactive state. The column selection signal output from the column decoder 14 is applied to the sense amplifier row 17 to activate the sense amplifier connected to the bit line connected to the memory cell to be accessed, and to keep the other sense amplifiers inactive. Is done. The input address signal and control signal (for example, row address strobe signal / RAS, column address strobe signal / CAS, chip select signal / CS, and write enable signal / W
E) is supplied to the control circuit 12, and the internal control signal generated there is supplied to each bank. At the time of data writing, the write data input to the I / O port 13 is supplied to the sense amplifier array 17 via the write amplifier 19, and the activated sense amplifier sets the bit line to a state corresponding to the write data. . A potential state (charge) corresponding to the state of the bit line is stored in the memory cell connected to the selected word line. At the time of data reading, the state of the bit line changes according to the charge stored in the memory cell connected to the selected word line, and the activated state is amplified by the sense amplifier. The data amplifier 18 changes the state to I
Output to the / O port 13. Therefore, the output circuit and the terminal are included in the I / O port 13. The above is a conventional general configuration. In addition to such a configuration, the D of the first embodiment
The RAM includes a delay circuit 2 for adjusting an output timing signal clko supplied to the delay I / O port 13 as shown in the figure.
The control circuit 12 outputs delay control signals d4 and d8 corresponding to the output data width.

FIG. 5 is a diagram showing a configuration of a portion related to the output circuit of the SDRAM of the first embodiment. As is apparent from comparison with FIG. 1, the blocks 8-0 to 8-n, the output circuits 20-0 to 20-n, and the terminals 53-0 to 53-n have the same configuration as the conventional example of FIG. . SDRAM of the first embodiment
Is different from the conventional example in that the output timing signal clko supplied to the output circuits 20-0 to 20-n is different from the delay circuit 2
The delay output timing signal clk whose delay amount has been adjusted by 1
od.

The delay control signal d supplied to the delay circuit 21
4 and d8 are signals generated by the control circuit 12 as shown in FIG. 4, and are both "L" when the output data width is 16 bits, and d when the output data width is 8 bits.
8 is "H" and d4 is "L", and when the output data width is 4 bits, d4 is "H" and d8 is "L".
When both d4 and d8 are "L", NOR gate 70
Becomes "H", the output timing signal clko input to the delay circuit 21 passes through the NAND gate 71, further passes through the NAND gate 74 and the inverter 75, and is output as the delayed output timing signal clkod. . When d8 is “H” and d4 is “L”, the output of the NOR gate 70 becomes “L”, so that the output timing signal clko input to the delay circuit 21
After passing through a first delay circuit composed of 1 and 63 and a capacitor 62, it passes through a NAND gate 72, further passes through a NAND gate 74 and an inverter 75, and is output as a delayed output timing signal clkod. Therefore, the delay output timing signal c when d8 is “H” and d4 is “L”
lkod is a signal delayed by the first delay circuit from when both d4 and d8 are "L". Similarly, when d4 is “H” and d8 is “L”, the output of the NOR gate 70 is “L”, so that the output timing signal clko input to the delay circuit 21 is equal to the inverters 64 and 66 and the capacitor 65. After passing through a second delay circuit composed of the following and a third delay circuit composed of the inverters 67 and 69 and the capacitor 68, the signal passes through the NAND gate 73, further passes through the NAND gate 74 and the inverter 75, and has a delayed output timing. It is output as a signal clkod. Assuming that the delay amounts of the first and second delay circuits are the same, the delay output timing signal clkod when d4 is “H” and d8 is “L” is d
8 is a signal delayed by the third delay circuit from when “H” and d4 is “L”. The delay amounts of the first and second delay circuits and the third delay circuit are determined according to a change in the delay amount of the data output circuit according to the output data width.

FIG. 6 is a diagram showing the data output timing in the first embodiment. When the output data width is 16 bits, d4 and d8 are set to "L", so that the delay of the delayed output timing signal clkod is the smallest. However, since the delay when the output circuits 20-0 to 20-n output data in accordance with the delayed output timing signal clkod is the longest, the output data Dout changes as shown. Since the output circuit is supplied with the delayed output timing signal clkod, setting the output timing signal clko in consideration of the delay in the delay circuit so that the delayed output timing signal clkod has a desired timing is referred to. Not even. When the output data width is 8 bits, d8 is set to “H” and d4 is set to “L”, so that the delay amount of the delayed output timing signal clkod is intermediate,
The delay when the output circuits 20-0 to 20-n output data in accordance with the delayed output timing signal clkod is also intermediate. Therefore, if the delay amount of the first delay circuit is appropriately set, the output data Dout is as shown in FIG. Thus, the timing changes at the same timing as when d4 and d8 are "L". When the output data width is 4 bits, d4 is set to "H" and d8 is set to "L". Therefore, the delay amount of the delayed output timing signal clkod is the largest, but the output circuits 20-0 to 20-n are delayed. Since the delay when outputting data in accordance with the output timing signal clkod is minimized, if the delay amount of the third delay circuit is appropriately set, the output data Dout changes in the same manner as in the other cases as shown. .

As described above, in the first embodiment of the present invention,
The change timing of the output data is constant regardless of the output data width. FIG. 7 shows a modified circuit 2 of the delay circuit 21.
1A is shown. In the figure, the same elements as those shown in FIG. 5 are denoted by the same reference numerals. The first to third delay circuits described above
In addition to the delay circuit, the delay circuit 21A includes inverters 81 and 8
3 and a fourth delay circuit including a capacitor 82. Switches 84 to 87 are provided in the first to fourth delay circuits, respectively. Switch 85 closes, switch 84,
When 86 and 87 are open, delay circuit 21A is equivalent to delay circuit 21. That is, the switches 84 to 8
7 has a function of bypassing the corresponding delay circuit. N from the input terminal to which the output timing signal clko is supplied.
The delay system up to the AND gate 72 is connected to the NAN from the input terminal.
This is the same as the delay system up to the D gate 73. Therefore, a delay system can be formed using one pattern in the manufacturing process. The switches 84 to 87 can be configured by fuses, transistors, and the like.

One of the delay systems or circuits can be eliminated from the configuration of FIG. In this case, the switch is constituted by a transistor, and is controlled by a control signal based on the delay control signals d4 and d8. As a result, a desired delay amount can be selectively obtained. In the first embodiment, a mode identification signal indicating the output data width is given from outside the SDRAM device, and the control circuit 12 receiving the mode identification signal generates delay control signals d4 and d8.

FIG. 8 is a circuit diagram of the delay control signal generation circuit provided in the control circuit 12. The delay control signal generation circuit shown in FIG. 8 generates delay control signals d4 and d8 from signals fx0 and fx1. In the first embodiment, this signal fx
0 and fx1 are given as mode identification signals from outside the SDRAM device. As shown, the delay control signal generation circuit includes a NOR gate 88, inverters 89, 90, and 9
1 and 93, NAND gates 92, 94, 95 and 96
Having. Table 1 shows the operation of the delay control signal generation circuit.

[0025]

[Table 1]

In the first embodiment, the mode signal indicating the output data width is input from the outside, and the control circuit
Generated the delay control signals d4 and d8. With such a configuration, the output data width can be arbitrarily set during the operation. Generally, in order to handle large-width data at high speed, it is necessary to connect a DRAM and a CPU with a wide data bus.
A bus having a data width of 2 bits (4 bytes) is employed. By using a bus having such a wide data width, for example, when reading and writing 64-bit data, the exchange between the DRAM and the CPU is performed four times or 32 bits when the data width is 16 bits (2 bytes). (4 bytes) only needs to be done twice. As described above, when the data width is wide, it is advantageous for data having a large width, but when reading and writing data having a small width, it is necessary to prepare data having the same number of bits as the data width. There is a problem that it is not only wasteful but also complicated and slow because extra data is prepared. An example of reading and writing data of such a small width is when only a moving part of image data is stored, and most of the image data is stationary and only a part of the image data is often moved. Operation. The mask function is provided to reduce such waste. Therefore, it is necessary that the data width can be arbitrarily changed during the operation as in the first embodiment.

On the other hand, when a plurality of products having different data widths are to be handled simply by partially changing the internal wiring (bonding wiring) by sharing the core portion, the data width is changed during the operation. You don't have to. The second embodiment is an example of such an SDRAM. FIG. 9 is a block diagram showing the overall configuration of the DRAM according to the second embodiment of the present invention. The difference from the first embodiment is that a mode storage circuit 22 storing the data width is provided, and the control circuit 12 reads the data width stored in the mode storage circuit 22 at the time of power-on reset, and performs delay control accordingly. Signals d4 and d
8 is output. Note that it is also possible to output the delay control signals d4 and d8 from the mode storage circuit 22.

FIG. 10 is a circuit diagram showing an example of the configuration of the mode storage circuit 22. The signal fx0 is for the fuses 97 and 9
8, p-channel MOS transistors 100, 102, n
It has channel MOS transistors 99, 101, 103 and an inverter 104. Similarly, the signal fx1 is supplied to the fuses 105 and 106 and the p-channel MOS transistor 1
08, 110 and n-channel MOS transistor 10
7, 109, 111 and an inverter 112. V
ii indicates a power supply voltage, and Vss indicates a ground potential.
Fuses 97, 98, 105 and 106 are selectively blown according to a desired output data width. Table 2 shows the relationship between the fuses and the signals fx0 and fx1.

[0029]

[Table 2]

As described above, when the output data width is 4 bits, the signals fx0 and fx1 are "L" and "H", respectively.
It is. Therefore, in this case, the fuses 97 and 106 are cut. If the output data width is 8 bits, the signal f
x0 and fx1 are "H" and "L", respectively. Therefore, fuses 98 and 105 are cut. When the output data width is 16 bits, the signals fx0 and fx1 are each "L". Therefore, the fuses are not cut at all, or the fuses 98 and 106 are cut.

A bonding wire may be used instead of the fuse. No bonding wire is connected to the portion where the fuse is cut. FIG. 11 shows that the SDRAM is 16
I when there are (n = 16) blocks (banks)
FIG. 3 is a block diagram showing a configuration of an output system of an / O port 13. As shown in FIG. 11, the I / O port 13 includes a data bus decoder (DBDEC) 210-225, a common data bus switch (CDBSW) 230-245, a latch circuit LAT, an output transistor unit OUT_Tr, and an output terminal 53-0. ~ 53-15. Latch circuit LA
T and the output transistor section OUT_Tr constitute the aforementioned output circuits 20-0 to 20-15. The I / O port is
The data latch circuit 113 is connected to blocks 8-0 to 8-15 (not shown in FIG. 11).

Common data bus switch (CDBSW4)
230 is connected to four pairs of data lines extending from corresponding four blocks of the 16 blocks. The common data bus switch 231 is connected to four pairs of data lines extending from blocks different from the above four blocks. Similarly, common data bus switches 232 and 233
Are respectively connected to four pairs of data lines extending from the corresponding four blocks. The common data bus switches 230 to 233 are connected to the data bus decoders 210 to 21.
Under the control of 3, the switching operation of the data lines is performed.

Similarly, a common data bus switch (CDB)
SW8) 234 237 are also connected to the corresponding two pairs of data lines, respectively.
217. Common data bus switch (CD
BSW16) 238 to 245 are connected to respective corresponding data line pairs, and data bus decoders 218 to 225
Is controlled by

The data bus decoders 210 to 225 include:
Delay control signals d4 and d8 are provided. Further, predetermined decoded column address signals dca08z and dca09z supplied from the column decoder 14 are supplied to the data bus decoders 210 to 213. Each of the data bus decoders 210 to 213 decodes the delay control signals d4 and d8 according to the decoded column address signals dca08z and dca09z, and outputs a 4-bit switch control signal to the common data bus switch CDBSW4.

When the output data width is 4 bits, the delay control signals d4 and d8 are "H" and "L", respectively.
In this case, the switch control signal output from the decoder 210 controls the switch 230 to control one of four data lines extending from four blocks related to data DQ0, DQ1, DQ2, and DQ3 obtained at the output terminal. Select the data line. If the output data width is 8 bits,
The delay control signals d4 and d8 are "L" and "H", respectively. In this case, the switch control signal output from the decoder 210 controls the switch 230 to switch one pair of data lines from two pairs of data lines extending from two blocks related to the data DQ2 and DQ3 obtained at the output terminal. select. When the output data width is 16 bits, the delay control signals d4 and d8 are both "L". In this case, the switch control signal output from the decoder 210 is the switch 2
30 is selected to select a pair of data lines extending from the block associated with the data DQ2 obtained at the output terminal.

Decoders 211-213 and switch 231
233 operate in the same manner as the operation described above. Each of the decoders 214 to 217 decodes the delay control signals d4 and d8 according to the decoded column address signal dca08z, and controls the corresponding switch CDSWW8.
When the output data width is 8 bits, the switch control signal output from decoder 214 controls switch 234 to select one pair of two data lines extending from two blocks related to DQ0 and DQ1. Output data width is 1
In the case of 6 bits, the switch control signal output from the decoder 214 controls the switch 234, and the data DQ0
Select a data line pair extending from the block related to.
When the output data width is 4 bits, the mask control signal d
m prevents data from being output to the corresponding output terminal. Switches 235 to 237 associated with the other decoders 215 to 217 operate similarly.

Column data bus switch (CDBSW16) related to decoders (DBDEC) 218 to 255
238 to 245 are output data widths 218 to 255 of 16
Only used for bits. Decoder (DBDEC)
Each of 218 to 255 controls a corresponding switch to pass through the data line pair. When the output data width is 8 bits or 4 bits, the mask control signal dm prevents data from being output to the corresponding output terminal.

The complementary data signals from the switches 230 to 245 are latched by the latch circuit LAT. Each of the latch circuits LAT includes, as shown in FIG.
3, transfer gates 44 and 45, a flip-flop including inverters 46 and 47, a flip-flop including inverters 48 and 49, and a NAND gate 52. The latched complementary data signal is output from an output transistor circuit O composed of transistors 51 and 52.
UT_Tr.

FIG. 12 is a circuit diagram of the data bus decoder 210. Other data bus decoders 211, 212, and 213 have the same configuration as data bus decoder 210.
As shown in FIG. 12, the data bus decoder 210 includes inverters (NOT circuits) 310 to 313 and a NOR gate 3
14 to 316, NAND gates 317 to 322, and a logic circuit 323. Logic circuit 323 determines whether the output data width is 16 bits. The delay control signal d4 is provided to input terminals 302 and 304. The delay control signal d8 is provided to the input terminal 303. The decoded column address signal dca08z is supplied to the input terminal 30.
1 and the decoded column address signal dc
a09z is given to the input terminal 300. The switch control signals are bits cdd4jx, cdd4kx, cdd4l
x and cdd4mx, each having an output terminal 305
308 are output.

When the output data width is 4 bits, the decoder 210 operates as shown in FIG. As shown in FIG. 13, a low-level signal is output through an output terminal 305, and a high-level signal is output through output terminals 306 and 307.
And 308. Usually, the signal dca08
According to the combination of the levels of z and dca09z, only one of the output terminals 305 to 308 becomes “H”.

When the output data width is 8 bits, decoder 210 operates as shown in FIG. As shown in FIG. 14, both signals dca09z and dca08z are “L”.
And the delay control signals d4 and d8 are each "L".
And "H". Accordingly, a low-level signal is output through the output terminal 307, and a high-level signal is output through the output terminals 305, 306, and 308. Signal d
If ca08z is “H”, a low-level signal is output from the output terminal 308 and a high-level signal is output from the output terminal 3.
05, 306 and 307. When the output data width is 8 bits, a high-level signal is always output from the output terminals 305 and 306 and a low-level signal is output from the output terminal 307 or 308 according to the level of the signal dca08z.

When the output data width is 16 bits, the decoder 210 operates as shown in FIG. In the case shown in FIG. 15, the delay control signals d4 and d8 are both "L" and the decoded column address signal dca0
8z and dca09z are both “L”. Therefore,
A low-level signal is output from the output terminal 307, and a high-level signal is output from the output terminals 305, 306, and 308. When the output data width is 16 bits, a high level signal is always output via output terminals 305, 306 and 308, and a low level signal is always output via output terminal 307. A low-level signal can be output via all the output terminals 305 to 308.

The other data bus decoders 214 to 225 have the same configuration as the decoders 210 to 213.
FIG. 16 is a diagram showing the relationship between the signals dca08z and dca09z and the output terminal from which the low-level signal is output. FIG. 17 is a circuit diagram showing a configuration example of the common data bus switch 230. As shown, the common data bus switch 230 is connected to an inverter (NOT gate) 334.
343 and transfer gates 350 to 353. For convenience, FIG. 17 shows a configuration related to one data line of each of the four pairs of data lines. Inverters 334-3
37 are connected to the input terminals 330 to 333, respectively.
It is connected to the data latch circuit 113 shown in FIG. Four bits cdd4jx, c of the switch control signal
dd4kx, cdd4lx and cdd4mx are provided to transfer gates 350, 351, 352 and 353 via terminals 305, 306, 307 and 308, respectively. As described above, four bits cdd4j
One of x, cdd4kx, cdd4lx, and cdd4mx is “L” according to the output data width. Output data selected by one of the transfer gates 350 to 353 is latched by a flip-flop including inverters 342 and 343, and output via an output terminal 354. The output terminal 354 is connected to, for example, the inverter 41 shown in FIG.

When masking a block, it is preferable to set the output terminals 53-0 to 53-n to a high impedance state. FIG. 18 is a diagram showing an SDRAM provided with a high impedance control circuit for setting an output terminal to a high impedance state. This control circuit is provided in each of output circuits 20-0 to 20-n.
61, an inverter 362 and a NAND gate 363. High impedance control signal Hi-Z is applied to NOR gate 361,
It is also provided to the R gate 363. When the high-impedance control signal Hi-Z is “H”, a high-level signal is applied to the gate of the transistor 50 and a low-level signal is applied to the gate of the transistor 51. Therefore, the transistors 50 and 51 are both off, and the output terminal 53-0 is in a high impedance state. The high impedance control signal may be the same as the mask control signal.

The delay circuit in the delay circuit 21 is not limited to the configuration described above. For example, the capacitor 6 shown in FIG.
2, 65 and 68 may be omitted. As shown in FIG. 19, a resistor 364 may be provided between the inverters 61 and 63. Such a resistor may be provided between the inverters 64 and 66 and between the inverters 67 and 69. The present invention is summarized as follows. (1) a plurality of circuits that operate in parallel according to a timing signal, each of which can be set to an operation state and a non-operation state;
A control circuit for setting each of the plurality of circuits to an operation state and a non-operation state according to an operation mode; and adjusting the timing signal according to the number of circuits in the operation state among the plurality of circuits. A semiconductor integrated circuit comprising a timing adjustment circuit. (2) The semiconductor integrated circuit according to (1), wherein the control circuit determines the operation mode from an external mode identification signal. (3) The semiconductor integrated circuit according to (1), further including an operation mode storage circuit that stores the operation mode, wherein the control circuit reads the operation mode from the operation mode storage circuit. (4) The semiconductor integrated circuit according to any one of (1) to (3), wherein the plurality of circuits are data output circuits. (5) The semiconductor integrated circuit according to (4), wherein the semiconductor integrated circuit has a variable data width of input / output data, and the control circuit operates among the plurality of circuits according to the data width. The timing adjustment circuit sets an output timing signal to be applied to the data output circuit later when the number of active data output circuits is small than when the number of active data output circuits is large. circuit. (6) The semiconductor integrated circuit according to (5), wherein the semiconductor integrated circuit is a synchronous dynamic random access memory (SDRAM). (7) In a semiconductor memory device capable of selecting a bit configuration of read data, operating in response to a control signal, selecting data read from the memory cell array in accordance with the selected bit configuration, and transmitting the selected data to a data output unit. A semiconductor memory device comprising: a data selection circuit to be supplied; and a timing control unit that adjusts a timing of applying the control signal to the data selection circuit in response to a selected bit configuration. (8) In the above (7), the control signal is an address information signal, and the timing control unit controls an output timing of the address information signal in response to a selected bit configuration. Semiconductor storage device. (9) In the above (7), the control signal is a clock signal, the data selection circuit has a latch circuit for holding data in response to the clock, and the timing control unit outputs the clock signal. A semiconductor memory device wherein timing is controlled in response to a selected bit configuration. (10) In any one of the above (7) to (9). A semiconductor memory device, wherein the timing control unit is a selection signal delay unit, and the selection signal delay unit delays the address information signal according to a set bit configuration.

[0046]

As described above, according to the present invention,
Since the operation timing can be stabilized in a semiconductor device having a plurality of circuits that operate in parallel according to a timing signal and can be set to an operation state and a non-operation state,
Higher speed operation becomes possible. In particular, the operating frequency can be improved because the data output timing is constant in an SDRAM that has a core that can cope with a large data width in advance and that can cope with various product specifications or in an SDRAM that can change the data width during operation. .

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of a portion related to a data output circuit of a conventional SDRAM.

FIG. 2 is a diagram illustrating a mask structure of output data.

FIG. 3 is a diagram showing data output when data widths are different in a conventional example.

FIG. 4 is a block diagram showing an overall configuration of the SDRAM according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating a configuration example of a portion related to a data output circuit of the SDRAM according to the first embodiment;

FIG. 6 is a diagram showing data output when data widths are different in the first embodiment.

FIG. 7 is a diagram illustrating a configuration of a data output circuit different from that of FIG. 5;

8 is a circuit diagram of a delay control signal generation circuit in the delay circuit shown in FIG.

FIG. 9 is a block diagram showing an overall configuration of an SDRAM according to a second embodiment of the present invention.

FIG. 10 is a circuit diagram of the mode storage circuit shown in FIG. 9;

FIG. 11 is a block diagram of an I / O port shown in FIG.

12 is a circuit diagram of the 4-bit data bus decoder shown in FIG.

FIG. 13 is a circuit diagram showing the operation of a 4-bit data bus decoder when the output data bus width is 4 bits.

FIG. 14 is a circuit diagram showing the operation of a 4-bit data bus decoder when the output data bus width is 8 bits.

FIG. 15 is a circuit diagram showing the operation of a 4-bit data bus decoder when the output data bus width is 16 bits.

FIG. 16 is a diagram showing a relationship between a decoded column address signal and an output terminal from which a low level signal is output.

FIG. 17 is a circuit diagram of the 4-bit data bus switch circuit shown in FIG. 11;

FIG. 18 shows an SDR having a high impedance control circuit.
It is a circuit diagram of AM.

FIG. 19 is a circuit diagram of a delay circuit having another configuration.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory cell array 8-1 to 8-n block 12 Control circuit 13 I / O port 20-1 to 20-n Output circuit 21 Delay circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Makoto Yanagisawa 4-1-1 Kamikadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Fujitsu Limited

Claims (5)

[Claims] 1. A plurality of circuits that operate in parallel according to a timing signal, each of which can be set to an operation state and a non-operation state, and that each of the plurality of circuits is set to an operation state and a non-operation state according to an operation mode. A semiconductor integrated circuit, comprising: a control circuit provided in an operation state; and a timing adjustment circuit adjusting the timing signal according to the number of circuits in an operation state among the plurality of circuits. 2. The semiconductor integrated circuit according to claim 1, wherein said plurality of circuits are data output circuits. 3. The semiconductor integrated circuit according to claim 2, wherein said semiconductor integrated circuit has a variable data width of input / output data, and said control circuit controls said plurality of circuits in accordance with a data width. The number of circuits to be activated and the number of circuits to be deactivated are set, and the timing adjustment circuit delays the output timing signal to be applied to the data output circuit when the number of active data output circuits is small compared to when the number is small. Semiconductor integrated circuit. 4. A semiconductor memory device capable of selecting a bit configuration of read data, operating in response to a control signal, selecting data read from a memory cell array in accordance with the selected bit configuration, and outputting data. A data selection circuit for supplying the control signal to the data selection circuit, and a timing control unit for adjusting a timing of applying the control signal to the data selection circuit in response to a selected bit configuration. 5. The apparatus according to claim 7, wherein the timing control unit is a selection signal delay unit, and the selection signal delay unit delays the address information signal according to a set bit configuration. 10. The semiconductor memory device according to claim 9.