JP2000082739A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

An object of the present invention is to provide an improved semiconductor device manufacturing method and a semiconductor device manufactured by the manufacturing apparatus. SOLUTION: A lower wiring is formed in a concave portion formed in a first insulating film formed on the semiconductor substrate, and at least one conductive layer formed on the semiconductor substrate so as to cover the lower wiring. Forming at least one thin film on the layer conductive layer, patterning the thin film to form a hard mask, etching the conductive layer using the hard mask as an etching mask, and forming an upper surface on the lower wiring. Forming a conductive columnar structure covered with a hard mask, forming a second insulating film on the semiconductor substrate so that the columnar structure is embedded, and forming a wiring groove at least exposing the hard mask; After removing the hard mask, a conductor is buried in the wiring groove to form an upper layer wiring in the wiring groove.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a logic LSI.
(Logical Large Scale Inte
graded Circuit), DRAM (Dyna
mic Random Access Memory
y), SRAM (StaticRAM), CMOS (C
elementary Metal Oxide
The present invention relates to a semiconductor device having a multilayer wiring structure such as a semiconductor device or a bipolar transistor, and more particularly to a multilayer wiring structure including a wiring formation and a via contact formation using a conductive columnar structure (pillar) and a multilayer wiring structure. The present invention relates to a semiconductor device having the same.

[0002]

2. Description of the Related Art Conventionally, when a connection plug for electrically connecting upper and lower wirings in a multilayer wiring structure of a semiconductor device is formed, reactive ion etching (RIE (Reactive Ion Etc) is performed on an interlayer insulating film.
hing)) method is generally used in which a connection hole is formed by using a method or the like and a conductive material such as metal is buried therein.

[0003] This prior art has the following problems. At the time of RIE, physical damage and corrosion occur on the lower wiring surface exposed at the bottom surface of the connection hole due to the etching gas and sputtered particles. The adhesion of the etching residue and the sputtered particles causes an increase in the contact resistance between the connection plug and the lower wiring. Further, when a misalignment with the lower wiring pattern occurs when the connection hole is formed and the connection hole is not formed at a desired position,
The side surface of the lower wiring and the interlayer insulating film thereunder are excessively etched by RIE. Further, a short circuit may occur with a lower wiring, or a cavity may remain around the fine wiring. As a result, the reliability decreases.

[0004] When forming a lower wiring, a method of forming a conductive columnar structure (pillar) and a lower wiring at the same time is known. This is a method in which a metal film is deposited on an insulating film on a semiconductor substrate, a connection plug is formed by an etching method such as photolithography and RIE, and the metal film is left in a recess to form a lower wiring.
However, since the material of the lower wiring and the connection plug are the same, it is not possible to widen the range of material selection by changing both materials. When the connection plug is etched, the lower wiring may be over-etched. Further, there is a possibility that misalignment may occur when the connection plug and the upper wiring are connected.

Recently, high-speed devices have been required. Therefore, a wiring material having a lower resistance is required. Copper (Cu) has been attracting attention to meet such demands and has been widely used. The resistivity of copper is 1.8μΩcm
And, among the wiring materials, the resistance is remarkably low. Other commonly used resistance materials include tungsten (W) having a thickness of 10 to 20 μΩcm and aluminum (A).
l) is 3 to 4 μΩcm. Accordingly, for example, the lower wiring 12, the connection plug (conductor pillar) 14, and the upper wiring 18 in FIG.
Although the Cu alloy is used, the lower wiring 12 and the upper wiring 1
It is conceivable to reduce the wiring resistance by using Cu for 8 and Al for the connection plug 14.

However, inconvenient cases may occur when Cu is used as it is. First, Cu, when covered with an insulating film, has a property of diffusing in the insulating film in an atomic state. In particular, when the device is heated during use or during a heat treatment step during its manufacture, the movement of Cu becomes active, and the wiring is destroyed, which easily causes line breaks and short circuit accidents. Further, if Cu is exposed, the surface is oxidized, and its low resistance is impaired.

Further, in the above pillar technology, the columnar structure (pillar) is formed only at the connecting portion between the lower wiring and the upper wiring, so that the ratio of the region where the columnar structure is formed is about several percent or less of the whole. And will be very small. Therefore, for example, the columnar structure is excessively etched during dry etching, and it becomes difficult to process the columnar structure. In addition, the flatness of the interlayer insulating film formed after the processing of the columnar structure is deteriorated.

[0008]

As described above, when the pillar technology is used in the step of connecting the lower wiring and the upper wiring, the ratio of the region where the columnar structure is formed is very small.
There are problems such as poor processing controllability of the columnar structure and poor flatness of the interlayer insulating film.

The objects of the present invention are as follows.

(1) Before depositing an interlayer insulating film, a space for arranging a contact structure between an upper wiring and a lower wiring can be secured, and RIE on the wiring surface below the connection hole can be secured.
Provided is a method of manufacturing a semiconductor device having a multi-layered wiring structure that can prevent damage at the time and the interposition of impurities, and can ensure the reliability of a lower wiring contact even if misalignment occurs in a connection hole.

(2) Connecting between wirings on which a protective film for suppressing the diffusion of the wiring material into the insulating film (or for suppressing the oxidation of the wiring material) can be deposited without a significant increase in the number of steps. A method of manufacturing a semiconductor device having a multilayer wiring structure and a semiconductor device manufactured by the method.

(3) When the pillar technology is used in the step of connecting the lower wiring and the upper wiring, a manufacturing method capable of improving the processing controllability of the columnar structure (pillar) and the flatness of the interlayer insulating film. To provide.

[0013]

According to the present invention, the following means have been taken in order to solve the above-mentioned problems.

According to a first aspect of the present invention, in a semiconductor device or a method of manufacturing a semiconductor device, a columnar structure (pillar) is provided.
Connects the lower layer wiring (first embedded wiring) and the upper layer wiring (second wiring), forms a hard mask on the upper part of the pillar, and proceeds with the process while leaving the hard mask.
The hard mask is removed just before connecting to the upper wiring. Here, it is preferable that after forming the columnar structure, a protective film is formed on at least a surface of the lower wiring that is not covered by the columnar structure. In the first aspect, only the protective film may be used instead of the hard mask. Further, the pillar may have a structure protruding into a concave portion for connecting an upper layer wiring,
The top of the pillar may be lower than the bottom of the recess.

[0015] The hard mask may be silicon oxide, silicon nitride, or tungsten.

The first aspect of the present invention has the following features. First, after forming a first embedded wiring (lower wiring) made of Cu in the first interlayer insulating film, for example, Al
A conductive layer is formed on which a connection plug made of / W / WN or Cu is formed. Next, the conductive layer is processed into a connection plug by lithography and RIE. That is, in the first aspect of the present invention, a hard mask material such as a silicon nitride film or a silicon oxide film for forming a connection plug is deposited as an etching mask on a conductive layer for forming a connection plug. After forming the connection plug, if necessary, a protective film having an effect of suppressing diffusion of Cu or the like such as a silicon nitride film (Si ₃ N ₄ ) or an effect of suppressing surface oxidation is formed on the connection plug and the first interlayer. CVD on insulating film
A desired film thickness is deposited by a sputtering method or a reactive sputtering method. Thereafter, a second interlayer insulating film is deposited, the upper wiring is embedded in the second interlayer insulating film, and the lower wiring and the upper wiring are connected by a connection plug.

Further, a protective film having a Cu diffusion preventing effect and an oxidation suppressing effect is deposited in a region where no connection plug is present on the first buried wiring (lower layer wiring). Since the wiring (lower wiring) is not in contact with the interlayer insulating film, good characteristics can be obtained without requiring complicated steps. This hard mask also has a function of increasing the variation tolerance in the depth direction when the second wiring groove is processed.

Therefore, according to the present invention, the tolerance for variation in the depth direction is increased, and poor coverage of the barrier metal of the upper layer wiring is prevented. Further, it is possible to prevent Cu diffusion in the lower wiring.

Further, by proceeding the process while leaving the hard mask, the upper surface of the pillar for making electrical contact with the wiring is prevented from being oxidized, contaminated, or subjected to a chemical reaction during the process. it can.

According to a second aspect of the present invention, a semiconductor device includes a semiconductor substrate on which a first insulating layer having a recess embedded with a lower wiring is formed, and a component having a barrier metal function formed on the lower wiring. And a conductive columnar structure connected to the conductive layer and formed on the semiconductor substrate, and a second insulating layer formed on the semiconductor substrate so as to surround the columnar structure. And the second insulating layer has a concave portion formed so that an upper portion of the columnar structure is exposed. An upper wiring electrically connected to the columnar structure is formed in the recess.

A preferred embodiment of the second aspect is as follows.

(1) The conductive layer has at least two layers. Alternatively, the conductive layer includes WN, and preferably, the conductive layer further includes W. The connection plug on the first buried interconnect (lower interconnect) is intended to prevent overetching of the first buried interconnect when RIE processing Al and Al as main materials into a columnar structure, for example. And a conductive layer. Furthermore, when the first embedded wiring and the main material of the connection plug are different, for example, when the first embedded wiring is Cu and the main material of the connection plug is Al, the heat treatment during the process causes In order to prevent Cu and Al from reacting, the conductive layer has a barrier property. For example, as a conductive layer satisfying this requirement,
WN is conceivable, but WN has a high specific resistance, and when a necessary film thickness is formed to be compatible with the stopper function,
This increases the overall resistance of the connection plug. Therefore,
Preferably, W having only a stopper function and having a small specific resistance is laminated. Thereby, as a W and WN laminated film,
While balancing the stopper function and the barrier function, and
A low-resistance connection plug can be formed. That is, the conductive layer has at least first and second layers, the first layer of the conductive layer functions as an etching stopper and a barrier layer when processing the columnar structure, and the first layer of the conductive layer 2
This layer has a lower resistance than the first layer of the conductive layer, and functions as an etching stopper when processing the columnar structure, whereby the above-described effect is obtained.

(2) The surface of the lower wiring and the surface of the first insulating layer are substantially flush with each other, and the conductive layer is formed so as to be connected to at least a part of the lower wiring. And a protective film formed so as to cover at least a surface of the lower wiring not covered by the columnar structure and to be deposited on an upper portion of the columnar structure. Since the protective film can be used as the alignment margin in the depth direction between the bottom surface of the second wiring groove and the upper surface of the pillar, the margin is increased.

(3) The conductive layer is formed in the recess so as to cover the entire surface of the lower wiring.
In (2), the lower wiring is covered with a protective film in order to prevent Cu diffusion. However, in this case, it is not necessary to cover the upper surface of the wiring with a protective film having a high dielectric constant (for example, SiN). Has the effect of reducing

(4) The conductive layer contains a material that can be selectively etched with respect to the first insulating film. Here, a horizontal cross section of the columnar structure is narrower than a horizontal cross section of the conductive layer. The columnar structure or the conductive layer has a divergent shape. There is further provided a protective film formed to cover a side wall of the columnar structure, the lower wiring, and the first insulating layer.

(5) The columnar structure contains copper or an alloy thereof.

(6) The conductive layer is formed by connecting the lower wiring to C
It is used as a CMP stopper when forming by MP.

According to the second aspect of the present invention, a protective film having a Cu diffusion preventing effect and an oxidation suppressing effect is deposited in a region where no connection plug exists on the first embedded wiring (lower wiring). As described above, since the first embedded wiring (lower wiring) is not in contact with the interlayer insulating film, good characteristics can be obtained without requiring a complicated process. Further, the protective film made of the silicon nitride film deposited on the connection plug also has a function of increasing the variation tolerance in the depth direction when the second wiring groove is processed together with the hard mask.

In addition, there is a margin for the risk of generating a narrow space formed by the side surface of the connection plug and the second wiring groove when the bottom position of the upper wiring is lower than the uppermost surface of the connection plug. Prevention of poor coverage of the barrier metal of the upper layer wiring at the part.

When the connection plug is formed borderless with the lower layer wiring (there is no room for alignment), a part of the bottom of the connection plug is separated from the lower layer wiring. Therefore, in order to surely realize the formation of the protective film at this portion, a conductive layer having a horizontal cross section wider than the columnar structure is formed on the first interlayer insulating film, so that an overhang is intentionally formed below the connection plug. A highly reliable protective film that can be provided to reliably cover and protect the connection plug is formed.

According to the present invention, it is possible to form a protective film covering the entire pillar in a multilayer wiring structure interconnected by using pillar-shaped connection plugs. This expands the possibilities of metal materials that can be selected as connection plugs, and allows selection of a material with extremely low resistivity, such as copper, for example.

In a third aspect of the present invention, a semiconductor device comprises a plurality of columnar structures formed in a connection region for electrically connecting a lower wiring and an upper wiring, and a plurality of columnar structures formed in a predetermined region other than the connection region. A plurality of dummy columnar structures, and an interlayer insulating film formed so as to cover the plurality of columnar structures, the data of the arrangement position of the dummy columnar structures formed in the predetermined region, Based on the arrangement information of the arrangement positions of the lower-layer wirings and the arrangement information of the arrangement positions of the upper-layer wirings, it is obtained by performing a logical OR negation of data corresponding to both information. Here, the columnar structure formed in the connection region and the predetermined region is formed of a conductor.

In another semiconductor device according to a third aspect of the present invention, a plurality of columnar structures formed in a connection region for electrically connecting a lower wiring and an upper wiring, and a predetermined structure other than the connection region are provided. A plurality of dummy columnar structures formed in the region, and an interlayer insulating film formed so as to cover the plurality of columnar structures, the data of the arrangement position of the columnar structure formed in the predetermined region is , Based on the arrangement information of the arrangement position of the connection area, by logically negating data corresponding to the information.

A preferred embodiment of the third aspect of the present invention is as follows.

(1) The columnar structure formed in the connection region is removed after forming the interlayer insulating film.

(2) The dummy columnar structure formed in the connection region and the predetermined region is formed of an insulator.

(3) The dummy columnar structure formed in the predetermined area is formed in an area excluding a predetermined specific area.

According to the third aspect of the present invention, a columnar structure (pillar) is formed in a region other than the connection region for electrically connecting the lower wiring and the upper wiring. Therefore, the ratio of the region where the columnar structure is formed locally and entirely can be greatly increased, and the process controllability of the columnar structure, which has been difficult in the past, can be improved. The flatness of the insulating film can be improved.

An arrangement position of a columnar structure (dummy columnar structure) formed in a predetermined area other than the connection area can be determined by the following arithmetic processing.

The first arithmetic processing method performs a logical OR operation (NOR processing) on data corresponding to both information based on the layout information of the layout position of the lower layer wiring and the layout information of the layout position of the upper layer wiring. . A logical sum process (OR) is performed between the data obtained by such an arithmetic process and the data corresponding to the connection area, and a mask for forming a columnar structure is formed based on the data obtained by the logical sum process. It will be manufactured. For example, mask pattern data corresponding to a dummy columnar structure can be generated by performing a process of dividing a region corresponding to data obtained by a logical sum negation process into a plurality of island-shaped regions separated from each other. it can.

By performing pattern transfer using the mask manufactured in this manner, the columnar structure is formed not only in the connection region between the lower wiring and the upper wiring but also in a region where neither the lower wiring nor the upper wiring is arranged. Is formed, and the ratio of the region where the columnar structure is formed locally and entirely can be increased.

When the columnar structure is formed using the mask prepared by the first arithmetic processing method, the columnar structure is not formed in the region where the lower wiring and the upper wiring are arranged. It is also possible to leave the columnar structure without removing it after forming the insulating film. Therefore, the columnar structure formed in the connection region and a predetermined region other than the connection region can be formed of a conductor, and the columnar structure formed in the connection region can be used as a connection member between the lower wiring and the upper wiring. It is.

In the second arithmetic processing method, based on the arrangement information of the arrangement position of the connection region between the lower layer wiring and the upper layer wiring, logical NOT processing (NOT processing) of data corresponding to the information is performed. A logical sum process (OR) is performed between the data obtained by such an arithmetic process and the data corresponding to the connection area, and a mask for forming a columnar structure is formed based on the data obtained by the logical sum process. It will be manufactured. For example, mask pattern data corresponding to a dummy columnar structure can be generated by performing a process of dividing a region corresponding to data obtained by a logical negation process into a plurality of island regions separated from each other. .

By performing pattern transfer using the mask manufactured in this manner, it becomes possible to form columnar structures in all regions other than the connection region between the lower wiring and the upper wiring. That is, unlike the first arithmetic processing method, the columnar structure can be formed also in the region where the lower layer wiring and the upper layer wiring are arranged. Therefore, the ratio of the region where the columnar structure is formed can be further increased as compared with the first arithmetic processing method.

In the case where a columnar structure is formed in a predetermined area other than the connection area by the above-mentioned manufacturing method, for example, the first arithmetic processing method or the second arithmetic processing method, the columnar structure is previously formed in the predetermined area. It may be formed only in the region excluding the determined specific region (specific circuit region).

That is, when the arrangement position of the columnar structure is determined by the arithmetic processing, a dummy pattern of the columnar structure is not generated in a predetermined specific region. Specifically, a dummy pattern is prevented from being generated in a specific region where formation of a dummy columnar structure is not preferable in terms of circuit performance and chip characteristics.

The specific area where the dummy pattern is not generated is, for example, the following area. First,
A region where a circuit affected by the parasitic capacitance generated by the interlayer insulating film is arranged can be given. Also,
There is also an area where a spare circuit section, a redundant circuit section, and a fuse section arranged in the circuit section are formed. Further, a region where an external connection terminal portion (PAD portion) is formed and a region where a dicing line portion is provided can also be given as specific regions.

As described above, according to the present invention, the columnar structure is also formed in a region other than the connection region for electrically connecting the lower wiring and the upper wiring. Therefore, the ratio of the region where the columnar structure is formed locally and entirely can be greatly increased, and the process controllability of the columnar structure, which has been difficult in the past, can be improved. The flatness of the insulating film can be improved.

[0049]

Embodiments of the present invention will be described with reference to the drawings.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

A first embodiment of the present invention will be described with reference to FIGS.

In the method of manufacturing a semiconductor device according to the first embodiment, a groove-shaped or hole-shaped concave portion is formed in an insulating film at the time of manufacturing a semiconductor device, and a conductive material such as a metal is deposited thereon to form an embedded wiring. (Hereinafter, referred to as a damascene process). Therefore, when forming a connection wiring (hereinafter, referred to as a “connection plug”) that connects the upper layer wiring and the lower layer wiring, a columnar temporary connection plug (pillar structure: Pillar) is formed in a portion to be the connection plug with an arbitrary material. To form After that, an interlayer insulating film is deposited. When a conductor is used for the temporary connection plug material, it is left as connection wiring as it is. In the case of replacing the columnar structure with the connection wiring material, or performing the step of performing wiring groove processing for the upper layer wiring and embedding the wiring material, or performing the replacement step before or after processing the groove processing of the upper layer wiring,
Thereafter or at the same time, the wiring material of the upper layer wiring is embedded.

By using this method, it is possible to secure a space for arranging the contact between the upper wiring and the lower wiring before depositing the interlayer insulating film. In addition, it is possible to form a low-resistance connection plug because damage to the surface of the wiring below the connection hole at the time of RIE and the inclusion of impurities can be prevented, which have been problems in the conventional connection hole opening step. Further, even if the connection hole is misaligned, the reliability of the lower wiring and the contact can be ensured. For the same reason, conventionally the diameter of the connection hole had to be smaller than the lower wiring,
By using the pillar process, such restrictions are eliminated, and the processing margin can be increased. here,
The “margin” refers to a margin (tolerance) of the horizontal alignment between the wiring and the connection plug.

Hereinafter, this embodiment will be described with reference to the drawings. In this example, a method of forming a connection plug using a conductor pillar and forming an upper wiring connected to the connection plug will be described. 1 to 4 are a cross-sectional view and a plan view of a manufacturing process of the semiconductor device of the present embodiment. FIG. 1 (a)
FIG. 4A shows the semiconductor substrate 10, but is omitted in other drawings. For example, a silicon semiconductor is used for the semiconductor substrate 10.

On the semiconductor substrate 10, a CVD (Chemic)
A first insulating film 11 made of a silicon oxide film or the like formed by an Al Vapor Deposition method or the like is formed. The first insulating film 11 is flattened, and a first wiring groove having the same shape as the wiring pattern of the lower wiring is formed on the surface thereof. The lower wiring 12 as the first wiring is formed by burying a metal made of, for example, an AlCu alloy in the first wiring groove (FIG. 1). Here, as a material of the lower wiring 12, an aluminum alloy (AlSiCu), Cu, W, or the like generally used as a wiring material may be used. Next, A is formed on the first insulating film 11 and the lower wiring 12.
An lCu metal layer is formed by a sputtering method or the like. Thereafter, the AlCu metal layer is etched by RIE or the like to form a pattern of columnar structures (hereinafter, referred to as pillars) 14. Here, AlCu is used as the pillar material.
However, the metal layer is preferably made of a material having a low specific resistance that can be used as a fine metal wiring, for example, Al, AlS
iCu, Cu, or the like can be used.

Next, the conductor pillar 14 made of the metal layer is used.
A second insulating film 15 made of a silicon oxide film or the like is formed by a CVD method, a spin coating method, or the like so as to fill the pattern. For the purpose of improving the flatness of the buried insulating film and the step coverage at the time of burying, the step of forming the second insulating film 15 is divided into several steps, and heat treatment or the like is performed during the step. May be included. Alternatively, a stacked structure of several different insulating films may be used as the second insulating film 15. Further, in order to reduce irregularities on the surface of the formed second insulating film 15, chemical mechanical polishing (CMP) is performed.
(Cal Polishing), a resist etch-back method, or the like can be added. The thickness of the second insulating film 15 is made lower than the height of the conductor pillar 14 so that the tip of the pillar 14 is exposed.
The exposed upper portion of the conductor pillar 14 may be removed by using the P method or the like, and the surface may be flattened at the same time (FIG. 2).

Next, a second wiring groove 16 having the same shape as the wiring pattern of the upper wiring is formed on the surface of the second insulating film 15 by, eg, RIE (FIG. 3). In forming the groove, the conductor pillar 14 is dug down to a depth that is at least partially exposed. Second wiring groove 1
6 after forming CDE (Chemical Dry Etc)
(hing) method, wet etching method, sputter etching method using an inert gas, or the like, a step of cleaning the exposed surface of the conductor pillar 14 may be added.

Next, an AlCu metal layer is formed on the second insulating film 15 and in the second wiring groove by using a sputtering method or the like. Although an AlCu alloy is used in this description, Al, AlSiCu, Cu, or the like may be used for the metal layer. After the formation of the metal layer, the metal layer other than the second wiring groove 16 is removed using a CMP method, a CDE method, or the like to form an upper wiring 18 as a second wiring (FIG. 4).

According to the first embodiment of the present invention, it is not necessary to perform dry etching for opening a connection hole, which has been used in the conventional method for forming a connection hole, so that the contact resistance at the bottom of the connection hole is increased. And the problem of excessive etching at the time of pattern misalignment is eliminated. As a result, it is possible to form a multilayer wiring structure having excellent electrical characteristics and high reliability.

The second embodiment will be described with reference to FIGS.

The second embodiment is characterized in that a hard mask is formed on the upper surface of a conductive pillar serving as a connection plug to improve its workability. 5 and 6 are cross-sectional views illustrating a manufacturing process of the semiconductor device. FIG. 7 shows a plan view of the manufacturing process sectional view shown in FIG. FIG. 5 (a) and FIG.
(J) shows a semiconductor substrate 10 made of, for example, a silicon semiconductor, but is omitted in other drawings.

First, a first insulating film 11 made of a silicon oxide film or the like formed on a semiconductor substrate 10 by a CVD method or the like is formed. Flatten the surface of the first insulating film 11,
A first wiring groove having the same shape as the wiring pattern of the lower wiring is formed on the surface. Then, a metal made of, for example, an AlCu alloy is buried in the first wiring groove to form the lower wiring 12 as the first wiring (FIG. 5A). Next, after forming an AlCu metal layer 13 on the first insulating film 11 and the lower wiring 12 by a sputtering method or the like, a hard mask 131 made of a silicon nitride film (Si ₃ N ₄ ) is formed by a plasma CVD method or the like. It is formed (FIG. 5B).
Next, a photoresist (not shown) is patterned using a photolithography method. Using this photoresist as a mask, for example, the hard mask 131 of the silicon nitride film is patterned by the RIE method using a CF ₄ -based gas, and is patterned into a hard mask 132 (FIG. 5C). Subsequently, the AlCu layer 13 is processed into a conductive pillar 14 made of metal, which is a columnar structure, by an RIE method using a Cl ₂ -based gas. Since the etching rate of the silicon nitride film with respect to the Cl ₂ -based gas is sufficiently smaller than the etching rate of AlCu (aluminum alloy), the processing accuracy of the relatively thick AlCu layer into a pillar shape is determined by using only the photoresist as an etching mask. It can be improved more than the case. For example, in the case of a columnar structure having a diameter of 0.2 μm, when only a photoresist is used as an etching mask, the height that can be manufactured is 1000 °, whereas when a hard mask such as SiN is used, 9000 is used.
Heights of Å or more are feasible.

The material used for the hard mask 131 may be a material having an etching rate sufficiently lower than the etching rate of the metal layer 13, and it is preferable that the material can be easily removed by a CDE method or a wet etching method as described later. For example, examples of the material of the hard mask 131 include silicon oxide, silicon nitride, organic siloxane, inorganic siloxane, tungsten, C, niobium, and niobium nitride. Here, when a C film, an organic siloxane film containing a large amount of C, and other organic films are used as a hard mask, an effect of protecting the side walls of the pillars by the etching reaction product during the AlCu pillar processing can be expected. Processing accuracy can be improved. Alternatively, Al, AlSiCu, Cu, or the like may be used as the metal layer 13 (FIG. 5D). Next, the metal pillar 14
Then, a second insulating film 15 such as a silicon oxide film is formed by a CVD method, a spin coating method, or the like so as to fill the hard mask 132. Note that the step of forming the second insulating film 35 may be divided into several steps, and a step of performing a heat treatment or the like to modify the insulating film may be inserted between the steps. Also,
As the second insulating film 15, a stacked structure of several different insulating films may be used (FIG. 5E). After the second insulating film 15 is thus formed, the second insulating film 15 is etched back by the CMP method for the purpose of flattening the step. At this time, the second insulating film 15 is etched back until at least a part of the hard mask 132 is exposed.

Further, since the hard mask 132 partially exposed on the wafer surface is made of a silicon nitride film,
It can be used as an etching stopper at the time of CMP of the second insulating film 15 such as a silicon oxide film (FIG. 5F). Next, the second wiring groove 16 is formed by the RIE method or the like so that the tip portion of the metal pillar 14 in which the hard mask 132 is covered in the concave portion in the second insulating film 15 is exposed (FIG. 5 (g)). )). Subsequently, the hard mask 132 is set to R
The second insulating film 15 and the metal pillars 14 are selectively removed by using the IE method or the CDE method. After removing the hard mask 132, the surface of the metal pillar 14 exposed inside the second wiring groove 16 is cleaned by using any one of a CDE method, a wet etching method, an RIE method, and a sputter etching method using an inert gas. (FIG. 6 (h)). Next, an AlCu metal layer 17 is formed on the second insulating film 15 and the second wiring groove 16 by using a sputtering method or the like (FIG. 6I).

Then, the metal layer 17 other than the inside of the second wiring groove 16 is removed by using the CMP method or the like, and an upper wiring 18 as a second wiring is formed (FIGS. 6J and 7).

By using the second embodiment, it becomes unnecessary to perform dry etching for opening a connection hole, which has been used in the conventional formation method. Therefore, the problem of the increase in contact resistance at the bottom of the connection hole and the problem of excessive etching at the time of pattern misalignment are eliminated, and a multilayer wiring structure having excellent electrical characteristics and high reliability can be formed. Also,
Since a hard mask is used at the time of processing the metal pillar, the processing of the pillar is facilitated and the processing accuracy is improved. Further, since this hard mask can be used as an etching stopper at the time of flattening the CMP of the insulating film in the subsequent step, the accuracy of the flattening can be improved.

In the second embodiment, when the second wiring groove 16 is formed, the etching is performed so that the side wall of the metal pillar 14 is exposed. The second wiring groove 16 may be formed up to (on the way of 132). In this case, when the hard mask is removed, the result is as shown in FIG. FIG. 8 shows the same step as FIG. 6 (h). Others are the same as the procedure shown in FIG. 5 and FIG.

As described above, by using the hard mask 132, the effect of protecting the upper surface of the pillar during the process can be obtained, and the tolerance of the variation in the depth of the second wiring groove 16 can be increased. Further, when a process as shown in FIG. 9 is used, it functions as an absorption layer against misalignment.

Therefore, even if a mask misalignment occurs between the connection plug and the second wiring groove, the area of the upper surface of the pillar serving as an electrical contact surface can be made constant, and the variation in electrical characteristics can be reduced. Can be suppressed.

The third embodiment will be described with reference to FIGS.

FIG. 10 and FIG. 11 are cross-sectional views showing the manufacturing process of the semiconductor device. On a semiconductor substrate 10 such as silicon,
A first interlayer insulating film 11 made of SiO ₂ or the like is laminated. As the first interlayer insulating film 11, a 500-nm-thick silicon oxide film (SiO ₂ ) is used by a spin-on method.
Next, photolithography and anisotropic etching (RI
The first wiring groove 121 is formed by E). After the first wiring groove 121 is formed, the PVD titanium nitride film 122 is formed as a barrier metal by about 5 nm, and the PVD copper film 12 is formed by 800 nm.
Degrees are sequentially deposited on the inner wall of the first wiring groove 121 (FIG. 10A). Next, after the semiconductor substrate 10 is heat-treated to increase the filling degree of the wiring material into the grooves, the titanium nitride film 122 is formed.
And an excess portion of the PVD copper film 12 is removed by polishing by a CMP method so that the titanium nitride film 1 is formed in the first wiring groove 121.
The lower wiring 12 surrounded by 22 is formed.

The method of depositing these materials is not particularly limited, but is here deposited by sputtering. In addition, the semiconductor element already formed under this wiring,
Wiring and interlayer connection wiring are omitted (FIG. 10B).
Subsequently, the material for the connection plug is changed to a W / WN film (barrier layer) 12.
3. An Al film (metal pillar) 14 is deposited on the first interlayer insulating film 11 by sputtering in this order (FIG. 10).
(C)). The barrier layer 123 is used for preventing diffusion of Cu, and in addition, is used as a stopper for preventing excessive etching during etching of the metal pillar 14. In the present invention, the barrier layer 123
Is not limited to this material. When the lower interconnect 12 and the metal pillar 14 are made of different metals as in the present embodiment, it is necessary to form two layers so that Cu, which is the material of the lower interconnect 12 in the present embodiment, does not diffuse. However, when they are the same kind of metal, one layer may be sufficient. In that case, it functions as a stopper for preventing excessive etching when etching the metal pillar 14.

Next, a hard mask material 132 made of a silicon nitride film (Si ₃ N ₄ ) is deposited on the connection plug material 123 and the metal pillars 14. This hard mask material 13
After a photoresist 133 is applied on the substrate 2, the photoresist 133 is patterned into a connection plug shape by lithography. Thereafter, the hard mask material 132, the metal pillars 14, and the barrier layer 123 are etched by RIE using the patterned photoresist 133 as a mask, and the barrier metal layer (W / WN) 123 is disposed at the lower portion. Metal pillar 14
Is formed. W / WN film etching process only C
You may use DE (Chemical Dry Etching). The connection plug forming process described above
The contents are almost the same as those of the second embodiment (FIG. 10).
(D)). Here, the barrier layer 123 is W / WN, but other applications such as WN / W and W / WN / W are also applicable. Although a hard mask is used in the third embodiment (including the following embodiments), it is not always necessary in the present embodiment. Therefore, in the third and subsequent embodiments, an embodiment using a hard mask for giving a margin is described, but the present invention is also applicable to an embodiment in which the formation of the hard mask is omitted.

Next, the lower wiring (first wiring) 1 surrounded by the first interlayer insulating film 11 and the barrier metal layer 122
2 and a silicon nitride film (Si ₃ N) on the metal pillars 14.
₄ ), a protective film 19 having the function of suppressing the diffusion of Cu or suppressing the oxidation of the wiring is deposited by the CVD method (FIG. 10E). Subsequently, a second interlayer insulating film (SiO 2) is formed by CVD so as to cover the metal pillars 14.
₂ ) Deposit 15. At this time, the second interlayer insulating film 15 is formed on the metal pillar 14 so that a second wiring groove can be formed later.
Deposits thicker. Then, the second interlayer insulating film 15 is planarized by CMP (FIG. 10F). FIG.
At 0 (e), the protective film 19 does not need to be formed as a continuous film. For example, although details will be described later, as shown in FIG. 12, if the bottom of the metal pillar 14 is covered so that no gap is formed between the metal pillar 14 and the protective film 19, Cu does not diffuse. The protective film 19 may not be formed on the side wall of the metal pillar 14, and even when the protective film 19 is formed on the side wall, the protective film 19 on the side wall is thinner than the protective film 19 on the bottom. It doesn't matter. However, when Cu is used as the metal pillar 14, a protective film 19 having an appropriate thickness is also provided on the side wall of the metal pillar 14.
Need to be formed.

Next, the second wiring groove 16 is formed by a usual method. At least a part of the protective film 19 is exposed at the bottom of the wiring groove (FIG. 11G). The protective film 19 exposed on the inner bottom surface of the second wiring groove 16 formed in the second interlayer insulating film 15 and the hard mask 132 thereunder are removed by etching to form a barrier layer by PVD using PVD.
A titanium nitride film (TiN) 135 of about nm is formed, a copper film 17 is buried as a wiring material, and this is used as an upper layer wiring 17, and a surplus portion is polished by a CMP method to form an interlayer insulating film 1.
5 is flattened (FIG. 11H).

According to the above method, a protective film made of a silicon nitride film having a Cu diffusion preventing effect and an oxidation suppressing effect is deposited on the lower wiring, and there is no step of opening a contact hole in the interlayer insulating film. Good connection can be obtained without requiring a complicated process. Further, the protective film made of a silicon nitride film deposited on the connection plug also has a function of increasing the variation tolerance in the depth direction at the time of processing the second wiring groove together with the hard mask described in the second embodiment.

A first modification of the third embodiment will be described. In the third embodiment, FIGS.
In the step (h), after the second wiring groove 16 is formed to expose the protective film 19, the protective film 19 and the hard mask 132 are removed by etching to expose the metal pillar 14.

In the first modification, as shown in FIG. 11F, the second interlayer insulating film 15 is planarized by, eg, CMP so that the protective film 19 is exposed. Thereafter, a third interlayer insulating film 15 'is deposited thereon, and a mask material is formed on the third interlayer insulating film 15'. Then, the second wiring groove 16 is formed, and the protection film 19 and the hard mask 132 are removed. Other processes are the same as in the third embodiment. Therefore, in this case, it is possible to use a different material from the interlayer insulating films 15 and 15 '. For example, Si formed by CVD as a second interlayer insulating film
O ₂ can be used. According to the first modification, for example, it is possible to stack interlayer insulating films having different dielectric constants.

A second modification of the third embodiment will be described with reference to FIG. As shown in FIG. 13A, after the lower wiring is formed, the upper part of the lower wiring is removed by etching. Thereafter, a barrier layer 123 (hereinafter referred to as a cap) is deposited to form a stopper layer (FIG. 13).
(B)). Then, for example, the surface is flattened by the CMP method (FIG. 13C). After that, the process of forming the columnar structure is the same as that of the third embodiment, and the description is omitted. In this case, the second interlayer insulating film 15 is formed without forming the protective film 19 as shown in the third embodiment. Subsequent steps are the third embodiment, and a description thereof will be omitted. In the second modification, the protective layer 19
Without using the barrier layer 123 as a stopper layer and preventing contact with the upper layer without forming C.
It prevents the diffusion of u. Therefore, the protective film 19 is not required. This effect is as follows. The protection film 19 is basically formed of SiN. However, since the dielectric constant of SiN is high, the operating speed is reduced. However, according to the present modification, since there is no protective film 19, there is an advantage that the operation speed is higher than that of the third embodiment.

A third modification of the third embodiment will be described. The third modified example is characterized in that a cap is provided in the first modified example, similarly to the second modified example.
The effect in this case is similar to that of the second modification.

The fourth embodiment will be described with reference to FIGS.

The process of forming the metal pillar 14 on the lower wiring 12 from the state where the lower wiring 12 is formed on the interlayer insulating film 11 on the semiconductor substrate 10 will be described with reference to FIG. There are various methods for forming the connection plug into a column shape. Here, a method using electroless plating will be described.

A pattern corresponding to a connection plug is formed on the interlayer insulating film 11 by using a photoresist. A copper layer is grown in a contact hole serving as a connection plug by electroless plating using the surface of the lower wiring 12 as a plating generation nucleus. Thereafter, when the photoresist is stripped with an organic solvent, a copper pillar structure is formed as the metal pillar 14. And metal pillar 14
And a protective film 19 such as a silicon nitride film for the interlayer insulating film 11.
Cover with. Further, an interlayer insulating film 15 made of SiO ₂ is formed on the surface of the semiconductor substrate 10 by a spin-on method, and a groove for an upper layer wiring is formed thereon. A titanium nitride film (TiN) 135 having a thickness of about 10 nm is formed as a barrier layer in the wiring groove by using the PVD method.

The above is the description of the series of steps for connecting the wirings based on the fourth embodiment. As is well known, copper diffuses in an interlayer insulating film and adversely affects device elements. Therefore, it is necessary to cover the entire copper surface with a diffusion suppressing film (barrier layer) or a protective film. However, in the structure after the process shown in FIG. 14, it is not possible to cover all the contact surfaces of the metal pillars 14 with the interlayer insulating film 11. This occurs remarkably when the metal pillars 14 are subjected to lithography steps with no margin for alignment (FIG. 14).
13 sites). Therefore, in a substrate that has undergone a practical process, copper leaks and diffuses at the portion 13 due to the misalignment (copper diffuses in an interlayer insulating film such as a silicon dioxide film due to heat and an electric field, thereby degrading device characteristics). It is known to cause deterioration, so it is important to cover with a diffusion suppressing film).

Next, with reference to FIGS. 15 and 16, a description will be given of a manufacturing process of the semiconductor device according to the fourth embodiment. First, a first interlayer insulating film 211 made of SiO ₂ or the like and a sacrificial film 212 are sequentially stacked on a semiconductor substrate 200 made of silicon or the like. The sacrificial film 212 may be a thin film made of a silicon nitride film. Here, a 500 nm-thick silicon oxide film (SiO 2 film) is formed by a spin-on method as the first interlayer insulating film 211.
₂ ) is used. Also, the plasma CV is used as the sacrificial film 212.
D (Chemical Vapor Deposit)
ion), a silicon nitride film (Si ₃
N ₄ ). The sacrificial film used in the present invention does not need to be an insulating thin film, and may be, for example, a conductive thin film such as carbon. Next, photolithography and anisotropic etching (RIE: Reactive Ion Etch)
ing) to form a first wiring groove 213.

In this step, the sacrificial film 212 may be used as a mask material for etching. That is, the sacrificial film 212 is processed using the photoresist pattern as a mask, and the first interlayer insulating film 211 is further processed using the processed sacrificial film 212 as a mask. With this method, the degree of freedom in the etching conditions used for processing the first interlayer insulating film 211 is increased.
That is, the photoresist may deform or disappear during processing (FIG. 15A). After the formation of the first wiring groove 213, a PVD titanium nitride film 14 as a barrier metal and a PVD copper film 215 are sequentially deposited on the inner wall of the first wiring groove 213 to a thickness of about 5 nm and about 800 nm to form a lower wiring 215. Polishing and removal by CMP. Further, a tungsten film 216 is formed on the copper surface by selective growth as a protective film.
Deposit 5 nm by VD method. This film is used for the lower wiring 215.
This is not necessary when is aluminum (FIG. 15B).

A photoresist 217 is formed on the first interlayer insulating film 211 and the sacrificial film 212 in which the copper film 215 serving as the lower layer wiring buried as described above is buried. Is formed. The thickness of the photoresist 217 is determined in consideration of the finally required height of the connection plug. Here, the thickness is 800 nm.

Thereafter, copper plating is performed using an electroless plating solution containing copper sulfate as a main component and formalin as a reducing agent. The electroless plating is basically a selective film growth on a metal, grows on a metal portion (tungsten film 216) exposed at the bottom of the opening of the photoresist 217, and fills a contact hole by plating. In some cases, copper may be formed in unnecessary portions by using defects or dust on the photoresist 217 as nuclei. However, the unnecessary copper particles can be removed by CMP or wet processing (FIG. 15). (C)).

Next, when the photoresist 217 is peeled off with an organic solvent, a connection plug 218 is formed by plating of copper filling the contact hole. Further, the exposed portion of the silicon nitride film serving as the sacrificial film 212 is isotropically etched by downstream etching. By this step, a cavity 220 is formed below the connection plug 218. In this state, the tungsten film 219 by selective growth CVD
deposited on the entire exposed connection plug 218 by about nm.
The protective film 219 is used as a Cu diffusion suppressing film or an oxidation suppressing film. Naturally, the protective film 219 is
(FIG. 15D).

Further, a second film having a thickness of about 800 nm is formed on first interlayer insulating film 211 so as to bury connection plug 218.
Is formed by a spin-off method, and a third interlayer insulating film 222 made of Si ₃ N ₄ having a thickness of about 20 nm is formed thereon by a plasma CVD method (FIG. 1).
6 (e)). The third interlayer insulating film 222 is used when forming a connection plug for connecting a wiring higher than the upper wiring to the upper wiring, and is the same as the sacrificial film 212 in FIGS. 15A and 15B. Works.

Next, a wiring groove for an upper wiring is formed on the interlayer insulating films 221 and 222. An about 10 nm titanium nitride film (T
iN) 224, and an upper layer wiring 223 made of a copper film as a wiring material is buried and a surplus portion is CM
It is polished and removed by the P method. As described above, the protective film 219 is also formed in the cavity 220 (FIG. 16F). Hereinafter, the process is performed using a normal process until a device is formed.

The above is the description of the series of steps. According to the present embodiment, Cu used as a wiring material (particularly, a connection plug material) is sufficiently covered with a protective film such as a diffusion suppressing film or an oxidation suppressing film, so that it diffuses in the interlayer insulating film to make a device. And Cu oxidation is suppressed.

The various materials used in the present embodiment can be replaced with appropriate materials without departing from the gist of the present invention. Also, the steps in the process, for example, the tungsten film 216 selectively grown as a protective film on the copper surface may be omitted. In this case, when the selective tungsten 219 formed on the surface of the connection plug 218 is formed, it can be formed so as to extend simultaneously on the surface of the lower wiring 215. The formation method is not limited to the selective growth CVD, but a metal thin film is formed in a non-selective manner, and then an alloy reaction with copper is performed.
Various formation methods are possible, such as a method in which the metal film is left only at the contact portion with copper and a method in which a metal film is selectively grown by electroless plating.

In the third embodiment, the connection plug 218 is formed by forming copper using electroless plating using a photoresist mask. However, for example, a copper film is formed uniformly once by PVD. May be processed into a columnar shape by lithography and anisotropic etching.

Next, a fifth embodiment will be described with reference to FIGS.

FIG. 17 is a sectional view showing the manufacturing process of the fifth embodiment. FIG. 18 is a cross-sectional view of a manufacturing process in a case where the wiring groove does not follow the fifth embodiment but varies in the depth direction of the wiring groove. In the fifth embodiment, Cu is placed on the connection plug.
After depositing a protective film made of a silicon nitride film having a diffusion suppressing effect and an oxidation suppressing effect, the thickness of the laminated layer of the protective film deposited on the upper surface of the connection plug and the silicon nitride film used for the hard mask is determined by the following steps. It is characterized in that it is used as a depth machining allowance for the wiring groove machining of No. 2.

The fifth embodiment is the same as the fourth embodiment up to the formation of the second interlayer insulating film (that is, the same as the third embodiment up to FIG. 10F). .

When the second interlayer insulating film 319 is etched to form the second wiring groove 321, the silicon nitride film protective film 318 is exposed when the surface of the connection plug 320 is not etched without etching to the surface of the connection plug 320. Interlayer insulating film 31
The etching of the silicon oxide film (SiO2) 9 is stopped (FIG. 17A). Thereafter, etching is again performed under the condition that the etching rate of the silicon nitride is higher than that of the silicon oxide film to expose the surface of the connection plug 320 (FIG. 17B). Thereafter, an upper layer wiring (a barrier layer 322 made of TaN and a copper layer 323) as a second wiring is formed in the wiring groove 321. With the steps described above, the variation in the depth of the second wiring groove 321 can be absorbed by the thickness of the silicon nitride films 316 and 318.
In FIG. 18, in the concave portion on the right side, the second interlayer insulating film 319 is etched so as to expose the side wall of the pillar, so that the protective film on the side wall of the pillar is removed except for the protective film above the pillar. It is drawn as if.
However, actually, the protective film on the side wall may remain partially without being completely removed (the same applies hereinafter).

Next, a sixth embodiment will be described with reference to FIG.

FIG. 19 is a sectional view of a semiconductor device. In the fifth embodiment, in order to improve the coverage of the protective film 418 made of a silicon nitride film having a Cu diffusion suppressing action or an oxidation suppressing action near the junction between the connection plug 420 and the lower wiring 415 made of Cu, (FIG. 19 (a)) or a downward step (barrier layer 41).
6 (a part of FIG. 19B). In any case, the protective film 418 can sufficiently cover this portion. That is, connection plug 4
It is possible to improve the coverage of the protective film 418 in a portion other than the contact portion between the protective film 20 and the lower wiring 415 thereunder, and to enhance the reliability thereof.

In the sixth embodiment, in order to improve coverage, the barrier layer 416 has a flared shape or a stepped structure. However, the present invention is not limited to this, and for example, a structure in which the connection plug 420 itself is wider at the bottom may be used. In that case,
Any structure may be used as long as the cross-sectional area of the connection plug 420 increases from the upper part to the lower part, or the structure expands toward the bottom.

Next, a seventh embodiment will be described with reference to FIGS.

FIGS. 20 and 21 are cross-sectional views of a semiconductor device having protective films of various shapes. A protective film 518 made of a silicon nitride film having a Cu diffusion suppressing action or an oxidation suppressing action near a junction with the Cu lower wiring 515 is deposited on the Cu lower wiring 515 and the first interlayer insulating film 511. If it is, it has an effect of suppressing Cu diffusion. In this case, the effect of suppressing the diffusion of Cu does not depend on the method of depositing the protective film 518 on the connection plug 520.
For example, in FIG. 20A, a thin film is deposited on the side surface of the connection plug 520, and the other portions are uniformly thick. Also,
First interlayer insulating film 511 on and near lower wiring 515
If the protective film 518 is deposited thereon, a part of the protective film 518 deposited on the first interlayer insulating film 511 may be removed as needed (FIG. 20B). In FIG. 21,
The protective film 518 is deposited thin on the connection plug 520 and thick on the interlayer insulating film 511. As described above, the method of forming the protective film 518 can be variously modified, and may be formed in any structure as long as the diffusion of Cu can be prevented other than the deposition method of the seventh embodiment.

FIG. 22 is a process sectional view showing a manufacturing method according to the eighth embodiment of the present invention. Note that the process diagram shown in FIG. 22 omits the element isolation, the MOSFET, and the like, and mainly shows the processes related to the logical operation processing for generating the dummy pattern and the formation of the multilayer metal wiring.

First, as shown in FIG. 22A, a low dielectric constant film 620 is formed on a semiconductor substrate 600 such as a silicon substrate via an insulating separation layer 610, and then a high melting metal film 6 is formed.
A lower-layer metal wiring (lower-layer wiring 630) including the metal film 31 and the metal film 632 is formed. In the eighth embodiment, a case in which a buried Al-Cu alloy metal wiring (Al-Cu Damascene) is used as the lower wiring 630 will be described.

First, the insulating separation layer 6 is formed on the semiconductor substrate 600.
10, a low dielectric constant film 6 having a relative dielectric constant k value of 3.9 or less
20 is formed. Several materials and forming methods can be considered for the low dielectric constant film 620. For example, as the formation of the low dielectric constant film 620, a film in which a silicon oxide film to which fluorine (F) or boron (B) is added by a low-pressure plasma CVD method can be used. Alternatively, a silicate-based film or a polymer-based film formed by a coating method can be used. As the silicate-based film, either an organic-based film containing an organic component or an inorganic-based film containing no organic component can be used. Alternatively, an organic film obtained by a vapor deposition polymerization method can be used. Note that some semiconductor devices do not require an insulating film to have a low dielectric constant.
A SiO2 film, a BPSG or PSG film containing boron (B) or phosphorus (P) by a VD method may be used. In the seventh embodiment, an organic SO formed by a coating method is used.
The G film is used as a low dielectric constant film. In this case, the organic SOG is applied in a thickness of 0.5 μm corresponding to the thickness of the lower wiring 630 and then heat-treated at 450 ° C. to cure and stabilize the organic SOG.

After forming the organic SOG film 620, a groove is formed in the organic SOG film 620 by lithography and RIE, and the groove is filled with a metal material to be a lower wiring. In this filling step, for example, a titanium nitride film (TiN film) 14a, which is a high melting point metal, is deposited by a 10 nm sputtering method, and then the Al—Cu alloy film 63 is formed at 450 ° C.
2 is deposited at 0.6 μm. Thereafter, chemical mechanical polishing (C
Excess metal outside the groove is removed by MP) and the surface is flattened to form a lower wiring 630 embedded in the groove. Thus, a structure as shown in FIG. 22A is obtained.

Next, as shown in FIG. 22B, a step of forming pillars 640 and an interlayer insulating film 650 is performed.

In the prior art, pillars are formed only for portions that become contacts or vias. However, by forming pillars, lithography of a hole pattern may not be performed, and it is possible to avoid the problem of resolution. Have been. However, the pattern density of contact holes and via holes in a semiconductor device, in other words, the coverage density (coverage, occupancy) of the pillars is extremely low, less than about 5%, and the pillar pattern is excessively formed in the step of processing the pillars into pillars after lithography. Phenomenon occurs. In addition, when an interlayer insulating film is deposited after pillar formation and planarization is performed, pattern dependency increases and planarization characteristics deteriorate. Therefore, the flattened state changes due to the difference in the standard coverage of the local region standardized in the region of several hundred μm. That is, the thickness of the interlayer insulating film is large in a portion where the standard coverage of the local region is high, and in a portion where the standard coverage of the local region is low,
There is a problem that the thickness of the interlayer insulating film is reduced. This effect is particularly significant when an interlayer insulating film is formed using a coating type forming technique.

In order to solve such a problem, a dummy pattern having an auxiliary role in the manufacturing process is provided by:
The dummy pattern is generated by a logical operation based on the design information of the semiconductor device, and the dummy pattern, that is, the dummy pillar is arranged to increase the standard coverage of the local area and the coverage of the entire semiconductor device. .

Several methods are conceivable for the logical operation processing. In the present embodiment, the following operation processing is performed. FIG. 23 is an explanatory diagram showing the flow of this arithmetic processing, which will be described below with reference to FIG.

First, based on the wiring data of the upper layer wiring (n wiring) and the lower layer wiring (n-1 wiring), a logical operation of NOR (NOR) is performed on the data of these two layers. By this logical OR operation, data D11 in an area where neither the upper layer wiring nor the lower layer wiring is arranged is extracted. Next, a negative conversion difference (for example, ΔL = −1.0 μm) is added to this extraction region, and the data obtained by this is set as D12. Thus, the data D
By providing a conversion difference of, for example, 1 μm with respect to the region corresponding to 11, a region separated by 1 μm or more from the boundary of the region where at least one of the upper layer wiring and the lower layer wiring is arranged is extracted. In this processing, the area where the short side is 2 μm or less before the negative conversion difference is applied is the data D
12 is deleted. Next, a calculation process is performed to divide the region corresponding to the data D12 into island-shaped patterns and extract the data, and the data obtained by this is referred to as D13. In this case, it is desirable that the division process is performed according to the original connection pattern design rules used in the same layer, and is divided into uniform dimensions. For example, the island pattern is a square having a side of 1 μm, and the interval between adjacent island patterns is 1
μm.

Next, the data D13 obtained by the above series of arithmetic processing and the data D1 obtained by logical NOT (NOT) of the original connection hole pattern data.
4 is calculated, and the data obtained by this operation is used as final data D15.

Note that, regarding the procedure of the above-mentioned arithmetic processing, the exchange rule (X + Y = Y + X, XY = Y × X), the combination rule (X
+ (Y + Z) = (X + Y) + Z, X · (Y · Z) = (X
· Y) · Z), distribution rule (X + Y · Z = (X + Y) · (X
+ Z), X · (Y + Z) = X · Y + X · Z), absorption rule (X · (X + Y) = X · X + XY · X = X), logical transformation based on de Morgan's theorem, etc. Therefore, various methods for obtaining the same result can be considered.

The data D15 obtained as described above
In, the pattern exists in both regions of the original connection hole pattern portion and the dummy pattern portion obtained by the logical operation, and the resist remains in these regions at the time of lithography. Therefore, the coverage of the pattern over the entire semiconductor device can be increased. For example, in the case of a certain microprocessor, its coverage is 19%.

Returning to the description of FIG. 22B, for example, an Al—Cu film is deposited on the entire surface by a sputtering method so as to have a thickness (for example, 0.7 μm) equal to or larger than the depth of the via hole. Subsequently, the pattern of the pillar is transferred to the resist using a mask created based on the data obtained by the arithmetic processing by lithography technology, and the pillar of the Al-Cu film is formed by RIE using the patterned resist mask. 6
40 is formed. After that, an organic SOG to be the interlayer insulating film 650 is applied to a thickness of 1.1 μm corresponding to the thickness of the upper wiring, and then heat-treated at 450 ° C. to cure and stabilize the organic SOG 650.

Next, in order to remove a film thickness difference generated in the surface of the interlayer insulating film 650 and tuned to the arrangement of the pillars 11,
The interlayer insulating film 650 is planarized by using CMP. Subsequently, the buried type upper layer wiring 17 composed of the TiN film 661 and the Al—Cu alloy film 662, which are high melting point metals, is formed in the same manner as the formation of the lower layer wiring 630 described above. A two-layer metal wiring structure as shown in FIG.

FIG. 24 shows a ninth embodiment of the present invention.
This will be described with reference to FIG.

In the eighth embodiment, an example is shown in which the formed columnar structure (pillar) is left as it is and the upper layer wiring is directly connected to the columnar structure. However, the columnar structure can be removed in a subsequent step. Can simplify the logical operation processing for generating the dummy pattern as compared with the method described in the eighth embodiment. FIG. 24 is an explanatory diagram showing the flow of this arithmetic processing, which will be described below with reference to FIG.

First, the upper wiring (n wiring) and the lower wiring (n wiring)
A minus conversion difference (for example, ΔL = −1.0 μm) is added to the hole data D21 such as a contact or a via hole which is a connection region of (−1 wiring), and the data obtained by this is referred to as D22. In this case, by providing a conversion difference of, for example, 1 μm with respect to the region corresponding to the data D21, a region separated by 1 μm or more from the boundary of the region where the connection region between the upper wiring and the lower wiring is arranged is extracted. In this processing, the area where the short side is 2 μm or less before the minus conversion difference is applied is the data D22.
Is removed from. Next, a calculation process is performed to divide the region corresponding to the data D22 into island-shaped patterns and extract the data, and the data obtained thereby is referred to as D23. In this case, it is preferable that the division process is performed according to the original connection pattern design rules used in the same layer, and is divided into uniform dimensions. For example, the island pattern is a square having a side of 1 μm, and the interval between the adjacent island patterns is 1 μm.

Next, the data D23 obtained by the above series of arithmetic processing and the data D2 obtained by logical NOT (NOT) of the data of the original hole pattern for connection.
Then, a logical sum (OR) operation is performed with the data D.4, and the data obtained thereby is used as final data D25.

The data D25 obtained as described above
In, the pattern exists in both regions of the original connection hole pattern portion and the dummy pattern portion obtained by the logical operation, and the resist remains in these regions at the time of lithography. Therefore, the coverage of the pattern over the entire semiconductor device can be increased. For example, in the case of a certain microprocessor, its coverage is 42%.

Hereinafter, a manufacturing method using the above-described logical operation processing will be described with reference to the process sectional views shown in FIGS. Note that these process drawings omit element isolation and MOSFET, etc., and relate to a logic operation process for generating a dummy pattern and a process related to formation of a double-level metal wiring (a Double-Level-Metal: DLM) composed of two layers. Is mainly shown.

First, as shown in FIG. 25A, a semiconductor substrate 6 such as a silicon substrate is formed in the same manner as in the eighth embodiment.
A low-dielectric-constant film 620 is formed on the metal layer 00 via an insulating separation layer 610, and then a lower-layer buried metal wiring (lower-layer wiring 630) composed of a high-melting metal film 631 and a metal film 632 is formed.
To form

Next, as shown in FIG. 25B, a 5 nm-thick SiO2 film 7 is formed on the entire surface by low-pressure plasma CVD.
01 and subsequently HSQ (Hydrogen Silsesquioxan
e) 702 is deposited to a thickness equal to or greater than the depth of the via hole, and then a 10 nm thick SiO
2 703 is deposited.

Next, the pattern is transferred to the resist by lithography using a mask created based on the data obtained by the above-described arithmetic processing. Subsequently, using the formed resist pattern as a mask, RI
SiO2 film 701, HSQ film 702 and Si
By etching the laminated film made of O2 703, pillars 700 are formed as shown in FIG.

Thereafter, as shown in FIG. 25D, an organic SOG to be an interlayer insulating film 710 is applied to a thickness of 1.1 μm corresponding to the film thickness of the upper layer wiring, and then heat-treated at 450 ° C. to form the organic SOG 710. Cure and stabilize.

Next, the interlayer insulating film 710 is planarized by using CMP in order to remove a difference in film thickness generated on the surface of the interlayer insulating film 710 in accordance with the arrangement of the base pillar material 700. After that, a resist pattern 720 for forming an opening in a connection region between the lower wiring and the upper wiring is formed on the interlayer insulating film 710. Subsequently, the resist pattern 72
By using 0 as a mask, the interlayer insulating film 710 and the pillar 700 thereunder are removed. When removing the pillar 700,
The upper SiO2 film is subjected to RIE using a gas containing fluorocarbon, and then the HSQ film is diluted with diluted H
F or an alkaline solvent, and the lower SiO2 film is removed by RIE using a gas containing fluorocarbon.
I do. By this step, the structure of FIG. 26E is obtained.

Thereafter, a TiN film 731 which is a high melting point metal is used.
By forming the buried type upper layer wiring 730 made of the Al—Cu alloy film 732 and the DLM structure as shown in FIG.

In the eighth embodiment, by adopting the above-described logical operation processing, dummy regions are formed also in the regions where the lower layer wiring and the upper layer wiring are formed except for the connection between the lower layer wiring and the upper layer wiring. Pillars remain. Therefore, it is desirable to use an insulator having a low dielectric constant as the pillar.

Referring to the tenth embodiment of the present invention, FIG.
This will be described with reference to FIGS.

The ninth embodiment is an embodiment in which processing is performed so as not to generate a dummy pattern in a predetermined specific area. That is, a dummy pattern (dummy pillar) is not generated in a region where it is not preferable from the viewpoint of circuit performance and chip characteristics. In this case, a dummy pattern may not be generated for a specific region of all layers, or a dummy pattern may not be generated only for a specific region of a specific layer. Examples of the specific area in which the dummy pattern is not generated as described above include, for example, the following areas.

First, a region where a circuit or the like sensitive to a parasitic capacitance generated by an interlayer insulating film is formed can be given as a specific region. In addition, a region where a spare circuit portion, a redundant circuit portion, and a fuse portion arranged in the circuit portion are formed is also included. Furthermore, the area where the external connection terminal section (PAD section) is formed and the area where the dicing line section is provided can also be given as specific areas.

Specifically, for example, a dummy pattern may be generated for a region excluding the specific region from the dummy pattern obtained in the eighth or ninth embodiment.

FIGS. 27 and 28 are diagrams showing the flow of arithmetic processing when a dummy pattern is generated for an area excluding a specific area from the dummy pattern obtained in the ninth embodiment. FIG. 27 shows an example in which the processing for removing the specific area is performed after the processing for subtracting the conversion difference ΔL, and FIG. This is an example of a case where the processing of FIG.

FIGS. 29 and 30 correspond to FIG. 27 or FIG.
3 is a process sectional view when a DLM structure is manufactured based on the data obtained by the arithmetic processing shown in FIG. The steps in FIGS. 29 and 30 correspond to the steps in FIGS. 25 and 26, respectively, according to the ninth embodiment. Therefore, the detailed description of each step refers to the ninth embodiment, and here, only the characteristic portions of the present embodiment will be described.

In the present embodiment, the process of removing the specific region is performed as described above. The process of removing the specific region is performed in the process of FIG. That is, unlike the ninth embodiment shown in FIG.
In the step (c), no pillar serving as a dummy is formed in the specific region S. As a result, even in the finally obtained structure shown in FIG. 30 (f), no dummy pillar is formed in the specific region.

The present invention is not limited to the above embodiments of the present invention, and it is needless to say that various modifications can be made without departing from the spirit of the present invention.

[0139]

According to the present invention, the following effects can be obtained.

First, the present invention has the following features. First, after forming a first embedded wiring (lower wiring) made of Cu in the first interlayer insulating film, for example, Al /
A conductive layer is formed on which a connection plug made of W / WN or Cu is formed. Next, the conductive layer is processed into a connection plug by lithography and RIE.
That is, in the first aspect of the present invention, a hard mask material such as a silicon nitride film or a silicon oxide film for forming a connection plug is deposited as an etching mask on a conductive layer for forming a connection plug. After forming the connection plug, if necessary, a protective film having an effect of suppressing diffusion of Cu or the like such as a silicon nitride film (Si ₃ N ₄ ) or an effect of suppressing surface oxidation is formed on the connection plug and the first interlayer. CVD method on the insulating film,
A desired film thickness is deposited by a reactive sputtering method or the like. Thereafter, a second interlayer insulating film is deposited, and the upper wiring is
The lower wiring and the upper wiring are connected by a connection plug.

Further, in a region where no connection plug exists on the first buried wiring (lower layer wiring), a protective film having a Cu diffusion preventing effect and an oxidation suppressing effect is deposited. Since the wiring (lower wiring) is not in contact with the interlayer insulating film, good characteristics can be obtained without requiring complicated steps. This hard mask also has a function of increasing the variation tolerance in the depth direction when the second wiring groove is processed.

Therefore, according to the present invention, the degree of variation in the depth direction is increased, and poor coverage of the barrier metal of the upper layer wiring is prevented. Further, it is possible to prevent Cu diffusion in the lower wiring.

Further, by proceeding the process while leaving the hard mask, the upper surface of the pillar for making electrical contact with the wiring is prevented from being oxidized, contaminated, or subjected to a chemical reaction during the process. it can.

Further, according to the present invention, a region where no connection plug exists on the first buried wiring (lower wiring) is
A protective film having a diffusion preventing effect and an oxidation suppressing effect is deposited, and the first buried wiring (lower wiring) and the interlayer insulating film are not in contact with each other as in the related art, so that a good characteristic can be obtained without a complicated process. Is obtained. Further, the protective film made of the silicon nitride film deposited on the connection plug also has a function of increasing the variation tolerance in the depth direction when the second wiring groove is processed together with the hard mask.

In addition, there is a margin for the risk of a small space created by the side surface of the connection plug and the second wiring groove, which is generated when the bottom position of the upper wiring is lower than the top surface of the connection plug. Prevention of poor coverage of the barrier metal of the upper layer wiring at the part.

When the connection plug is formed borderless with the lower layer wiring (there is no room for alignment), a part of the bottom of the connection plug is separated from the lower layer wiring. Therefore, in order to surely realize the formation of the protective film at this portion, a conductive layer having a horizontal cross section wider than the columnar structure is formed on the first interlayer insulating film, so that an overhang is intentionally formed below the connection plug. A highly reliable protective film that can be provided to reliably cover and protect the connection plug is formed.

According to the present invention, it is possible to form a protective film covering the entire pillar in a multilayer wiring structure interconnected by using pillar-shaped connection plugs. This expands the possibilities of metal materials that can be selected as connection plugs, and allows selection of a material with extremely low resistivity, such as copper, for example.

As described above, according to the present invention, a columnar structure is formed in a region other than a connection region for electrically connecting a lower wiring and an upper wiring. Therefore, the ratio of the region where the columnar structure is formed locally and entirely can be greatly increased, and the process controllability of the columnar structure, which has been difficult in the past, can be improved. The flatness of the insulating film can be improved.

[Brief description of the drawings]

FIGS. 1A and 1B are a cross-sectional view and a plan view illustrating a manufacturing process of a semiconductor device according to a first embodiment.

2A and 2B are a cross-sectional view and a plan view illustrating a manufacturing process of the semiconductor device according to the first embodiment.

3A and 3B are a cross-sectional view and a plan view illustrating a manufacturing process of the semiconductor device according to the first embodiment.

4A and 4B are a cross-sectional view and a plan view illustrating a manufacturing process of the semiconductor device according to the first embodiment.

FIG. 5 is a sectional view showing a manufacturing process according to the second embodiment of the present invention.

FIG. 6 is a sectional view showing a manufacturing process according to the second embodiment of the present invention.

FIG. 7 is a plan view of a sectional view of the manufacturing process in FIG. 6 (j).

FIG. 8 is a view showing another embodiment in the step of FIG. 6 (h).

FIG. 9 is a diagram showing a case where there is misalignment of an upper interface in the second embodiment.

FIG. 10 is a sectional view showing the manufacturing process of the semiconductor device according to the third embodiment;

FIG. 11 is a sectional view showing the manufacturing process of the semiconductor device according to the third embodiment;

FIG. 12 is a view showing another embodiment in the step of FIG.

FIG. 13 is a view showing a second modification of the third embodiment;

FIG. 14 is a sectional view of a semiconductor device illustrating a fourth embodiment;

FIG. 15 is a sectional view of the manufacturing process of the semiconductor device according to the fourth embodiment;

FIG. 16 is a sectional view showing the manufacturing process of the semiconductor device according to the fourth embodiment;

FIG. 17 is a sectional view illustrating the manufacturing process of the semiconductor device according to the fifth embodiment;

FIG. 18 is a sectional view showing the manufacturing process of the semiconductor device according to the fifth embodiment;

FIG. 19 is a sectional view showing the manufacturing process of the semiconductor device according to the sixth embodiment;

FIG. 20 is a sectional view of the semiconductor device according to the seventh embodiment during the manufacturing process;

FIG. 21 is a sectional view showing the manufacturing process of the semiconductor device according to the seventh embodiment;

FIG. 22 is a process cross-sectional view showing the process in order in the manufacturing method according to the eighth embodiment of the present invention.

FIG. 23 is a diagram showing a procedure for generating mask data for forming pillars according to the eighth embodiment of the present invention.

FIG. 24 is a diagram showing a procedure for generating mask data for forming pillars according to the ninth embodiment of the present invention.

FIG. 25 is a process sectional view showing the process in order in the manufacturing method according to the ninth embodiment of the present invention.

FIG. 26 is a process cross-sectional view showing the process sequentially in the manufacturing method according to the ninth embodiment of the present invention.

FIG. 27 is a diagram showing a procedure for generating mask data for forming pillars according to the tenth embodiment of the present invention.

FIG. 28 is a diagram showing a procedure for generating mask data for forming pillars according to the tenth embodiment of the present invention.

FIG. 29 is a process cross-sectional view showing the process in order in the manufacturing method according to the tenth embodiment of the present invention.

FIG. 30 is a process cross-sectional view showing the process in order in the manufacturing method according to the tenth embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate 11 ... 1st insulating film 12 ... 1st wiring (lower wiring) 14 ... pillar (columnar structure) 15 ... 2nd insulating film 18 ... 2nd wiring (upper wiring)

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Akihiro Kajita 8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa Prefecture Inside the Toshiba Yokohama Office (72) Inventor Tetsuro Matsuda 8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa Inside the Toshiba Yokohama Office (72) Inventor Tadashi Iijima 8 Shinsugitacho, Isogo-ku, Yokohama, Kanagawa Prefecture Inside the Toshiba Yokohama Office (72) Naofumi Kaneko 8 Shinsugitacho, Isogo-ku, Yokohama, Kanagawa Prefecture Toshiba Corporation Inside Yokohama Works (72) Inventor Hideki Shibata 8-8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside Toshiba Yokohama Works (72) Inventor Naofumi Nakamura 8-8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Toshiba Yokohama Business Co., Ltd. (72) Inventor M.B.A.ANDANDO 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Company Toshiba Yokohama workplace (72) inventor Katsuya Okumura Yokohama, Kanagawa Prefecture Isogo-ku, Shinsugita-cho, address 8 Co., Ltd. Toshiba Yokohama workplace

Claims (28)

[Claims] A step of forming a recess in a first insulating film formed on a semiconductor substrate and forming a lower wiring in the recess; and forming at least one lower wiring on the semiconductor substrate so as to cover the lower wiring. Forming a conductive layer of a layer, forming at least one thin film on the conductive layer, patterning the thin film to form a hard mask, and forming the conductive layer using the hard mask as an etching mask. Forming a conductive columnar structure, the upper surface of which is covered with the hard mask, on the lower wiring, and forming a second insulating layer on the semiconductor substrate so that the columnar structure is embedded. Forming a film; forming a wiring groove at least exposing the hard mask; removing the hard mask and embedding a conductor in the wiring groove; The method of manufacturing a semiconductor device characterized by comprising a step of forming an upper wiring trench. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming a wiring groove exposing the hard mask includes a step of selectively etching a surface of the second insulating layer. A method for manufacturing a semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming a wiring groove exposing the hard mask includes the step of forming the second insulating layer after the step of forming the second insulating layer. A method for manufacturing a semiconductor device, comprising: forming a third insulating layer on a layer; and selectively etching the surface of the third insulating layer. 4. The method for manufacturing a semiconductor device according to claim 1, wherein after forming the columnar structure, at least an upper surface of the columnar structure and a surface of the lower wiring not covered by the columnar structure. A method for manufacturing a semiconductor device, further comprising a step of forming a protective film. 5. A semiconductor substrate on which a first insulating layer having a concave portion in which a lower wiring is embedded is formed; a conductive columnar structure connected to the lower wiring and formed on the semiconductor substrate; A protective film that covers a surface of the lower wiring that is not covered by the columnar structure and is formed to be deposited on at least an upper part of the columnar structure; and a protective film formed on the semiconductor substrate so as to surround the columnar structure. A second insulating layer having at least one concave portion formed by selectively etching to expose at least an upper portion of the protective film and further removing at least a part of the upper portion of the protective film. A semiconductor device, comprising: an upper wiring formed to be embedded in the recess and electrically connected to the columnar structure. 6. A semiconductor substrate on which a first insulating layer having a concave portion in which a lower wiring is buried is formed; and a semiconductor substrate connected to the lower wiring and formed on the semiconductor substrate;
A thin film serving as a hard mask is formed thereon, and a conductive columnar structure formed using the hard mask as a mask, and formed on the semiconductor substrate so as to surround the columnar structure, and selectively etched. A second insulating layer having at least one recess formed of a groove formed by removing at least the hard mask and removing the hard mask, and the columnar structure formed by being embedded in the recess. A semiconductor device comprising an upper wiring electrically connected to the semiconductor device. 7. The semiconductor device according to claim 6, wherein
Forming a protective film on at least the upper surface of the columnar structure and the surface of the lower wiring not covered by the columnar structure, and then removing the protective film on the upper surface of the columnar structure to form the second insulating layer. A semiconductor device in which at least one concave portion is formed. 8. A semiconductor substrate on which a first insulating layer having a recess in which a lower wiring is embedded is formed; a conductive columnar structure connected to the lower wiring and formed on the semiconductor substrate; A second insulating layer formed on the semiconductor substrate so as to surround the columnar structure; and an upper wiring electrically connected to the columnar structure, the second insulating layer or the second insulating layer being provided. A first concave portion having the same horizontal cross-sectional shape as the columnar structure is formed on the surface of the third insulating layer formed thereon, and a horizontal cross section of the columnar structure is formed above the first concave portion. A semiconductor device, wherein a second concave portion having a horizontal cross-sectional area larger than an area is formed, and the upper wiring is formed in the first concave portion and the second concave portion. 9. The semiconductor device according to claim 8, wherein
A semiconductor device further comprising a protective film formed on at least a surface of the lower wiring not covered by the columnar structure. 10. A semiconductor substrate on which a first insulating layer having a recess in which a lower wiring is embedded is formed, a conductive layer having a component having a barrier metal function formed on the lower wiring, and the conductive layer A conductive columnar structure connected to the semiconductor substrate and formed on the semiconductor substrate; and a recess formed on the semiconductor substrate to surround the columnar structure and formed so that an upper portion of the columnar structure is exposed. A second insulating layer having: and an upper wiring formed in the recess and electrically connected to the columnar structure. 11. The semiconductor device according to claim 10, wherein said conductive layer has at least two layers. 12. The semiconductor device according to claim 11, wherein the conductive layer has at least first and second layers,
The first layer of the conductive layer functions as an etching stopper and a barrier layer when processing the columnar structure, and the second layer of the conductive layer has a lower resistance than the first layer of the conductive layer. A semiconductor device that functions as an etching stopper when processing the columnar structure. 13. The semiconductor device according to claim 10, wherein said conductive layer contains WN. 14. The semiconductor device according to claim 11, wherein said conductive layer contains W. 15. The semiconductor device according to claim 10, wherein the lower wiring and a surface of the first insulating layer are substantially flush with each other, and the conductive layer is connected to at least a part of the lower wiring. The semiconductor device further includes a protective film formed so as to cover at least a surface of the lower wiring not covered by the columnar structure and to be deposited on an upper portion of the columnar structure. A semiconductor device characterized by the above-mentioned. 16. The semiconductor device according to claim 10, wherein said conductive layer is formed in said recess so as to cover the entire surface of said lower wiring. 17. The semiconductor device according to claim 10, wherein the conductive layer contains a material that can be selectively etched with respect to the first insulating film. 18. The semiconductor device according to claim 10, wherein said lower layer wiring contains copper or an alloy thereof. 19. The semiconductor device according to claim 10, wherein a horizontal cross section of said columnar structure is narrower than a horizontal cross section of said conductive layer. 20. The semiconductor device according to claim 10, wherein the columnar structure or the conductive layer has a divergent shape. 21. The semiconductor device according to claim 10, wherein the side wall of the columnar structure, the lower layer wiring, and the first layer are formed.
A semiconductor device further comprising a protective film formed so as to cover the insulating layer. 22. The semiconductor device according to claim 10, wherein the conductive layer is used as a CMP stopper when the lower wiring is formed by CMP. 23. A plurality of columnar structures formed in a connection region for electrically connecting a lower wiring and an upper wiring, a plurality of dummy columnar structures formed in a predetermined region other than the connection region, An inter-layer insulating film formed so as to cover the plurality of columnar structures, the data of the arrangement position of the dummy columnar structure formed in the predetermined region includes the arrangement information of the arrangement position of the lower wiring and the A semiconductor device which is obtained by performing a logical sum negation process on data corresponding to both information based on arrangement information of an arrangement position of an upper layer wiring. 24. The semiconductor device according to claim 23, wherein the columnar structure formed in the connection region and the predetermined region is formed of a conductor. 25. A plurality of columnar structures formed in a connection region for electrically connecting a lower wiring and an upper wiring, a plurality of dummy columnar structures formed in a predetermined region other than the connection region, An inter-layer insulating film formed so as to cover the plurality of columnar structures; and data of arrangement positions of the columnar structures formed in the predetermined region is based on the arrangement information of the arrangement positions of the connection regions. A semiconductor device obtained by performing a logical negation process on data corresponding to. . 26. The semiconductor device according to claim 25, wherein the columnar structure formed in the connection region is removed after forming the interlayer insulating film. . 27. The semiconductor device according to claim 26, wherein the dummy columnar structure formed in the connection region and the predetermined region is formed of an insulator. . 28. The semiconductor device according to claim 23, wherein the dummy columnar structure formed in the predetermined region is formed in a region excluding a predetermined specific region. Semiconductor device. .