JP2000078114A - Reception symbol error detection circuit and error detection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the error detection circuit that simplifies a processing corresponding to a transmission error in the case of detecting it and releases a processing load. SOLUTION: The detection circuit is provided with a 5B4B decoding circuit 2 that decodes a 5-bit parallel signal into a 4-bit, a control code detection means that detects whether or not the 5-bit parallel signal outputted from a serial parallel conversion means 1 is a prescribed predetermined control code, a reception error detection circuit 5 that receives a symbol error signal when the 5B4B decoding circuit 2 outputs the symbol error signal denoting disabled decoding of received data and outputs an error signal denoting occurrence of a reception error when the prescribed predetermined control code is detected in data received after the received data, and an error reception error display device 6 that receives the error signal outputted from the reception error detection circuit 5 and applies error countermeasure processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data receiving apparatus, and more particularly to a detection control system for an error detection circuit for detecting an error from received code data.

[0002]

2. Description of the Related Art Conventionally, an mBnB blocking code (m and n are integers of 2 or more and m is smaller than n) is used as a binary signal data transmission method for detecting an error occurring during transmission. In this case, a method of detecting an error is used. For example, Japanese Unexamined Patent Publication No. Hei 3-297236 discloses a method of improving the error detection capability of a received bit string input to a 5B4B decoding circuit by combining an original signal and an error detection code obtained by taking an exclusive OR of the original signal. Has been proposed.

[0003]

However, even if the transmission error detection capability is improved, when a transmission error frequently occurs, the processing load for error detection increases. As a result, when error handling is always performed when an error is detected,
A particularly high processing performance is required for an apparatus that performs error handling processing.

[0004] In this case, if it is possible to take measures to temporarily ignore the error detection signal, the load of the processing for detecting a transmission error as described above can be reduced.

Accordingly, the present invention has been made based on the recognition of the above technical problems, and an object of the present invention is to provide an error detection circuit capable of reducing the load and simplifying a process for detecting a transmission error. Is to do.

[0006]

In the data receiving apparatus according to the present invention which achieves the above object, the error detecting circuit always outputs the data when the received data is an undecodable bit string.
Instead of performing a symbol error notification, when a predetermined control code appears in data received thereafter, an error notification is performed for the error handling process, thereby simplifying the error handling process and reducing the load. It is intended to reduce the amount.

[0007]

Embodiments of the present invention will be described. According to a preferred embodiment of the present invention, serial / parallel conversion means (1 in FIG. 1) for converting received data in which one piece of information data is serially transmitted in n bits into an n-bit parallel signal, and the n-bit parallel signal To m bits (where n is an integer greater than m) (2 in FIG. 1), and n output from the serial / parallel conversion means.
Control code means (30 in FIG. 2) for detecting whether or not the bit parallel signal is a predetermined control code is provided, and it is determined from the decoding means (2 in FIG. 1) that the received data cannot be decoded. When a signal (14 in FIG. 1) is output,
In response to the signal, when the predetermined control code is detected in data received after the reception data, an error signal (17 in FIG. 1) indicating that a reception error has occurred is output. Detecting means (5 in FIG. 1); error countermeasure processing means (6 in FIG. 1) for performing error countermeasure processing upon receiving a signal indicating that a reception error has occurred, output from the error detecting means (5 in FIG. 1); Is provided.

According to a preferred embodiment of the present invention, the error detection circuit includes first latch means (31 in FIG. 2) for holding a signal indicating that the received data from the decoding means cannot be decoded. , Control code detecting means (2 in FIG. 2)
0) and a first logic operation means (33 in FIG. 2) for generating a signal indicating that a reception error has occurred in response to the output of the first latch means (32 in FIG. 2) and the output of the first latch means. Second latch means (32 in FIG. 2) for holding and outputting a signal indicating that the reception error has occurred from the first logical operation means.
And a signal indicating completion of the countermeasure processing (18 in FIG. 2) notified from the error countermeasure processing means (6 in FIG. 1) and a control code detection signal from the control code detection means (20 in FIG. 2). The first and second latch means (31, 3 in FIG. 2)
2) a second logical operation means (34 in FIG. 2) for generating a signal for resetting 2).

According to a preferred embodiment of the present invention, descrambling means (3 in FIG. 1) for descrambling received data scrambled and transmitted after decoding means (2 in FIG. 1), and receiving Storage means (4 in FIG. 1) for accumulating data, wherein the descrambling means and the storage means comprise the control code detecting means (FIG. 2).
Based on the control code detection signal in (20), the input bit sequence following the control code is descrambled and stored as received data.

An embodiment of the data receiving apparatus according to the present invention will be described with reference to FIG. 1. A serial / parallel conversion circuit (1), a 5B4B decoding circuit (2), and a descrambling circuit (3) , A cell buffer (4), a reception error detection circuit (5), and a reception error display device (6).

The 5-bit received code flowing on the 5-bit signal line 11 obtained by the serial / parallel conversion circuit (1) is converted into a 4-bit symbol by the 5B4B decoding circuit (2). The 5B4B decoding circuit (2) outputs a symbol error signal (14) indicating that a symbol error has occurred to the reception error detection circuit (5) when the 5-bit reception code is other than a predetermined bit string. Output to

In the reception error detection circuit (5), when the 5-bit reception code received thereafter matches a predetermined control code, a symbol error notification signal is sent to the reception error display device (6). (17) is output.

The reception error display device (6) receiving the symbol error notification signal (17) performs error handling processing,
When the error handling process is completed, an error process completion signal (1
8) is output to the reception error detection circuit (5).

The reception error detection circuit (5) continues to output the symbol error notification signal (17) until receiving the error processing completion signal (18) from the reception error display device 6.

[0015]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing the configuration of one embodiment of the present invention. Referring to FIG. 1, in one embodiment of the present invention, a serially transmitted received signal 10 is converted into a 5-bit symbol, which is parallel data, by a serial / parallel conversion circuit 1 and input to a 5B4B decoding circuit 2, The 5B4B decoding circuit 2 converts a predetermined 5-bit bit string into 4 bits.
Conversion is performed according to a one-to-one correspondence table (table) of a bit into a bit string. This correspondence table is stored in a ROM or the like in the 5B4B decoding circuit 2.

In the 5B4B decoding circuit 2, when a 5-bit bit string not included in the correspondence table is input from the serial / parallel conversion circuit 1, a symbol error signal 14 is output each time. 5 is input.

In one embodiment of the present invention, a predetermined bit string not included in the correspondence table is used as a control code.
When the bit sequence of the control code is received after the symbol error signal 14 is output, if the subsequent bit sequence satisfies the condition, the reception error detection circuit 5 outputs the cell start signal 15 or the cell start signal 16 I do. The cell start signal 15 is input to the descrambler circuit 3 and instructs its initialization.

The descrambler circuit 3 inputs the 4-bit data decoded by the 5B4B decoding circuit 2 and descrambles the scrambled bit sequence. The cell buffer 4 converts the input bit sequence following the cell start signals 15 and 16 into the scrambled bit sequence. Is stored as received cell data.

When the symbol error signal 14 is input from the 5B4B decoding circuit 2, the reception error detection circuit 5 displays a symbol error notification signal 17 when a predetermined 5-bit control code is received. Device 6
Output to

The reception error display device 6 is composed of a data processing device that operates asynchronously with the reception error detection circuit 5. After receiving the symbol error notification signal 17, the reception error display device 6 displays error occurrence information on a figurative terminal. A corresponding process is performed, and after the process is completed, an error process completion signal 18 is output to the reception error detection circuit 5.

FIG. 2 is a diagram showing an example of the configuration of the reception error detection circuit 5 according to one embodiment of the present invention. Referring to FIG. 2, the reception error detection circuit 5 includes a control code detection circuit,
It comprises flip-flops 31, 35 and AND circuits 33, 34.

When a predetermined control code is input as a received bit string, the control code detecting circuit 30 converts the immediately following received bit string into 5B4B data by a 5B4B decoding circuit, and then converts the 4-bit data into hexadecimal notation. "4"
(“0100” in binary notation), the cell start signal 16
Is output. If the bit string immediately after is a control code,
The cell start signal 15 is output, and the initialization of the descrambler 3 is also performed at the same time.

The symbol error signal 14 from the 5B4B decoding circuit 2 is supplied to a set / reset type flip-flop (F
F) The signal is held at 31, and when the cell start signal 15 is output from the control code detection circuit 30, the output signal 20 of the flip-flop 31 and the cell start signal 15 are input, and an AND circuit for obtaining the logical product of them The output of 33 becomes true (logic 1), and the symbol error notification signal 17 is output as logic 1 from the set / reset flip-flop 32 set by the output of the AND circuit 33.

An AND circuit 34 which receives the error processing completion signal 18 and the cell start signal 16 and takes a logical product of them.
Are true (logic 1), the flip-flops 31 and 32 input the output of the AND circuit 34 to the reset terminal.
Is reset.

FIG. 3 is a timing chart for explaining the operation of one embodiment of the present invention.
4, an example of timing waveforms of cell start signals 15 and 16, a symbol error notification signal 17, an error processing completion signal 18, and an output signal 20 of a set / reset type flip-flop (FF) 31.

The operation of one embodiment of the present invention will be described with reference to FIGS. When the symbol error signal 14 is output for several symbol errors starting from the time T0, the set-reset flip-flop 31
Output signal 20 becomes logic 1.

The received bit string includes a bit string having the cell start signal 15 or the cell start signal 16 as logic 1 at each head of the cell. Generally, a bit string corresponding to the cell start signal 15 appears. Infrequent.

After time T0, at time T1 when the cell start signal 15 becomes logic 1 for the first time, the symbol error notification signal 17 output from the flip-flop 32 becomes logic 1 and this value is held.

After a predetermined time has elapsed, the error processing completion signal 18 becomes logic 1, and thereafter, the cell start signal 16
At time T2 at which the flip-flop 3
1 and flip-flop 32 are reset.

The symbol error notification signal 17 is logic 0
As a result, the error processing completion signal 18 is also returned to logic 0. This makes it possible to deal with a new symbol error.

Next, another embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a diagram illustrating a configuration of a reception error detection circuit according to the second embodiment of the present invention. Referring to FIG. 4, in the second embodiment of the present invention, the output destination from cell start signal 16 is changed from AND circuit 34 shown in FIG. The output destination from 15 is changed from the logical product circuit 33 to the logical product circuit 34.

In the second embodiment of the present invention, the timing for setting and resetting the symbol error notification signal 17 is replaced with that of the above-described embodiment, and is functionally equivalent to that of the above-described embodiment. Work. That is, at the time when the cell start signal 16 becomes logic 1 for the first time, the symbol error notification signal 17
Becomes a logic 1 and this value is held, and after a predetermined time elapses, the error processing completion signal 18 becomes a logic 1, and then, when the cell start signal 15 becomes a logic 1 for the first time, the flip-flop 31 and the flip-flop 32
Is reset.

[0033]

As described above, according to the present invention,
The following effects are obtained.

A first effect of the present invention is that the load on the symbol error handling process can be reduced and simplified.

The reason is that in the present invention, even when symbol errors occur intensively in a short time, error notification is performed in synchronization with the cell start signal, and furthermore, error processing completion notification is received. Until then, a new error notification is not performed.

A second effect of the present invention is that it is possible to identify a situation in which the network is not normally connected.

The reason is that, in the present invention, since error notification is performed in synchronization with the cell start signal, error notification is not performed when a symbol error occurs even up to the cell start signal.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a receiving apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a reception error detection circuit in one embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of the reception error detection circuit in one embodiment of the present invention.

FIG. 4 is a diagram illustrating a configuration of a reception error detection circuit according to another embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 serial / parallel conversion circuit 2 5B4B decoding circuit 3 descrambler 4 cell buffer 5 reception error detection circuit 6 reception error display device 14 symbol error signal 15, 16 cell start signal 10 reception data 11 5 bit data 17 symbol error notification signal 18 error Processing completion signal 30 Control code detection circuit 31, 32 Flip-flop 33, 34 AND circuit

Claims (9)

[Claims] When a received data is determined to be undecodable by a means for decoding the received data, a predetermined control code is detected in the subsequent received data upon receiving the determination result. An error detection control system, comprising: error detection means for notifying a means for performing processing corresponding to the reception error when a reception error has occurred. 2. When the received data is a bit string that cannot be decoded, when a predetermined control code appears in the subsequently received data, the fact that a reception error has occurred corresponds to the reception error. An error detection control method, comprising: notifying a means for performing processing. 3. When the received data is determined to be undecodable by the means for decoding the received data, the error detecting means having received the result of the determination includes a predetermined predetermined value in the data received after the received data. A data reception device that, when the control code is detected, notifies a reception error handling processor that a reception error has occurred. 4. A serial / parallel conversion means for converting received data in which one piece of information data is serially transmitted in n bits into an n-bit parallel signal; and converting the n-bit parallel signal into m bits (where n is larger than m). ), And control code detection means for detecting whether or not the n-bit parallel signal output from the serial / parallel conversion means is a predetermined control code. When a signal indicating that the received data is undecodable is output from, when the signal is received and the predetermined control code is detected in the data received after the received data, Error detecting means for outputting a signal indicating that a reception error has occurred, and an error countermeasure for performing error countermeasure processing in response to a signal indicating that a reception error has occurred output from the error detecting means. Characterized by comprising a management unit, a data receiving apparatus. 5. The decoding means includes a conversion table for converting the n-bit parallel signal into the m-bit signal. If the conversion table does not include the n-bit parallel signal, the decoding is disabled. The data receiving apparatus according to claim 4, wherein the signal is output. 6. The data receiving apparatus according to claim 4, wherein the n-bit parallel signal forming the control code is a code not allocated to the conversion table. 7. After the error countermeasure processing unit completes the error countermeasure processing, a signal to the effect that the error countermeasure processing is completed is output to the error detection unit. Upon receiving this signal, the error detection unit receives a signal indicating that a reception error has occurred. The data receiving apparatus according to claim 4, wherein output is stopped. 8. An error detecting circuit comprising: first latch means for holding a signal indicating that the received data from the decoding means cannot be decoded; a control code detection signal from the control code detecting means; First logical operation means for generating a signal indicating that a reception error has occurred in response to the output of the first latch means, and holding a signal indicating that the reception error has occurred from the first logical operation means A second latch unit for outputting, a signal indicating the completion notified from the error countermeasure processing unit after the error countermeasure processing unit completes the error countermeasure processing unit, and a control code detection signal from the control code detection unit. 5. The data receiving apparatus according to claim 4, further comprising: a second logical operation means for receiving the signal and resetting an output of the first and second latch means. 9. A descrambling means for descrambling received data scrambled and transmitted at a subsequent stage of said decoding means, and a storage means for storing received data, wherein said descrambling means and said storage means comprise: Based on the control code detection signal in the control code detection means,
9. The data receiving apparatus according to claim 8, wherein an input bit sequence following the control code is descrambled and stored as received data.