JP2000077992A - Analog switch - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To be manufactured at low cost, to have low on-resistance,
Provide an analog switch with high output accuracy. An analog switch having a first N-type MOS transistor and a first P-type MOS transistor connected between a first terminal and a second terminal, further comprising a first terminal and a first N-type MOS transistor. By connecting a second N-type MOS transistor to the back gate of the MOS transistor and connecting the second P-type MOS transistor between the first terminal and the back gate of the first P-type MOS transistor To solve the above problem.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, but not limited to, an analog switch used for selectively outputting one of reference voltages in, for example, a reference voltage circuit of a DA converter. .

[0002]

2. Description of the Related Art FIG. 6 is a circuit diagram showing an example of a reference voltage circuit of a DA converter. The reference voltage circuit 32 of the illustrated example includes a ladder resistor 12 configured by connecting in series a resistance element R having an equal resistance value between a reference voltage VREFH and a reference voltage VREFL, and each of the ladder resistors 12. An analog switch (34a, 34b, 34c) is connected between each of the connection points A, B, and C of the resistance element R and the output terminal of the reference voltage circuit 32.

In the reference voltage circuit 32, first, at connection points A, B, and C of the respective resistance elements R of the ladder resistance 12,
A reference voltage obtained by equally dividing the voltage between the reference voltage VREFH and the reference voltage VREFL by the resistance element R is generated. In the analog switch 34, only one of the analog switches 34a, 34b or 34c is turned on at the same time, and the connection points A,
One of the reference voltages generated by B and C is output from the reference voltage circuit 32.

In the above-described conventional reference voltage circuit 32, for example, an enhancement-type N-type MOS transistor (hereinafter referred to as NMOS) and a P-type MOS transistor (hereinafter referred to as PMOS) are connected in parallel as the analog switch 34. Is used.

However, the ladder resistance 1 of the reference voltage circuit 32
2, different reference voltages are generated at the respective connection points A, B, and C. Since the potential difference between the source and the back gate differs for each of the analog switches 34a, 34b, and 34c, the reference voltages VREFH, VREFL are caused by the body bias effect.
, The threshold voltage of the MOS transistor increases, the on-resistance increases, the error in the output reference voltage increases, and high-speed operation cannot be performed.

As one means for solving such a problem, for example, a reference voltage circuit disclosed in Japanese Patent No. 2647970 can be cited.

FIG. 7 shows a circuit diagram of an example of the reference voltage circuit disclosed in the above publication. The reference voltage circuit 36 shown in the figure has an analog switch 38 having a different configuration from the analog switch 34 of the reference voltage circuit 32 shown in FIG. The high-potential part analog switch 38a is configured by connecting an enhancement-type PMOS in parallel, and the low-potential part analog switch 38c is configured by an enhancement-type N
MOS is connected in parallel, and the analog switch 38b at the intermediate potential portion is connected to the NMOS switch whose threshold voltage is near 0V.
Are connected in parallel.

According to this reference voltage circuit 36, the analog switches 38a, 38
It is stated that since the on-resistances of b and 38c can be sufficiently reduced, the accuracy of the reference voltage can be improved and the operation speed can be improved. However, in the means disclosed in the publication, a transistor having a low threshold voltage is required in addition to a transistor having a normal threshold voltage, which complicates the manufacturing process and increases the manufacturing cost. There was a problem.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an analog switch which can be manufactured at a low cost, has a low on-resistance, and has a high output accuracy, in view of the problems based on the prior art. is there.

[0010]

To achieve the above object, the present invention provides a first N-type MOS transistor and a first P-type MOS transistor connected between a first terminal and a second terminal.
An analog switch having a transistor, further comprising: a second N-type MOS transistor connected between the first terminal and a back gate of the first N-type MOS transistor; Second P-type MOS transistor connected to the back gate of the first P-type MOS transistor.
An analog switch characterized by having a type MOS transistor. Here, in the analog switch, further, a third N-type MOS transistor connected between the second terminal and a back gate of the first N-type MOS transistor; Preferably, a third P-type MOS transistor is connected between the first P-type MOS transistor and the back gate.

The above-mentioned analog switch, further comprising: means for fixing a potential of a back gate of the first N-type MOS transistor when the second N-type MOS transistor is turned off; It is preferable to have a means for fixing the potential of the back gate of the first P-type MOS transistor when the P-type MOS transistor is turned off. Where the analog switch is
Furthermore, a third N-type MOS connected between the second terminal and the back gate of the first N-type MOS transistor
An S transistor, the second terminal, and the first P-type MO.
A third transistor connected to the back gate of the S transistor;
And a P-type MOS transistor.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an analog switch according to the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings. FIG. 1 is a configuration conceptual diagram of an embodiment of a reference voltage circuit using an analog switch according to the present invention. The reference voltage circuit 10 in the illustrated example is used in, for example, a DA converter of a resistive voltage dividing system, and includes a ladder resistor 12 and an analog switch (SW) 14 (14a, 14b, 14
c).

In the reference voltage circuit 10, first, the ladder resistor 12 includes a reference voltage VREFH and a reference voltage VREF.
It is configured such that four resistance elements R having the same resistance value are connected in series between the FL and the FL. At the connection points A, B, and C of the resistance elements R of the ladder resistance, a reference voltage obtained by equally dividing the voltage between the reference voltage VREFH and the reference voltage VREFL by the four resistance elements R is generated. It is supplied to the corresponding analog switches 14a, 14b, 14c.

The analog switch 14 is an analog switch according to the present invention. The analog switch 14 receives a reference voltage supplied from the connection points A, B, and C of the resistance element R of the ladder resistor 12 as an analog input voltage, and receives this as an analog output voltage. Output as In the reference voltage circuit 10, only one of the analog switches 14a, 14b or 14c is turned on at the same time, and each connection point A,
One of the reference voltages generated at B and C is output.

FIG. 2 is a circuit diagram showing one embodiment of the analog switch. The illustrated analog switch 14 includes an N-type MOS transistor (hereinafter referred to as NMOS) 16 and a P-type MOS transistor (hereinafter referred to as PMOS) 1 connected between a first terminal and a second terminal.
8, the NMOS 20 connected between the first terminal and the back gate of the NMOS 16, and the first terminal and the PMOS
And a PMOS 22 connected between the back gate 18 and the back gate 18.

Here, a decode signal φ obtained by decoding an input digital signal is input to the gates of the NMOSs 16 and 20, and an inverted decode which is an inverted signal of the decode signal φ is input to the gates of the PMOSs 18 and 22. Signal φ￣ is input. NMOS20, PMO
The back gate of S22 is basically connected to a potential lower than or higher than the source (first terminal side), and in the case of the illustrated example, to the reference voltages VREFL and VREFH, respectively. In the present embodiment, the first terminal of the analog switch 14 is connected to the input side of the reference voltage circuit 10, and the second terminal is connected to the output side.

In this analog switch 14, basically, when the decode signal φ is at the high level, that is, when the inverted decode signal φ # is at the low level, the first terminal and the second terminal conduct, and the input side The potential, that is, the reference voltage supplied from each connection point A, B, C of the ladder resistor 12 is output to the output side. Conversely, when the decode signal φ is at the low level, that is, when the inverted decode signal φ # is at the high level, the first terminal and the second terminal are shut off.

First, when the decode signal φ is at a high level and the inverted decode signal φ is at a low level, one or both of the NMOS 20 and the PMOS 22 are turned on in accordance with the potential on the input side. In the case of this embodiment, only the PMOS 22 is turned on in the analog switch 14a, and only the NMOS 20 is turned on in the analog switch 14c.
In the analog switch 14b, the NMOS 20 and the PM
It is assumed that both the OS 22 are turned on.

Normally, a MOS transistor is turned on when a potential difference between a gate and a source becomes larger than a threshold voltage. Therefore, in the reference voltage circuit 10 shown in FIG. 1, the NMOS 20 of the analog switches 14b and 14c whose input potential, that is, the reference voltage supplied from the ladder resistor 12 is relatively low, is turned on, and the ladder resistor 1
The PMOS 22 of the analog switches 14a and 14b whose reference voltage supplied from the second switch 2 is relatively high is turned on.

When the NMOS 20 is turned on, NM
When the back gate and the source of the OS 16 are electrically short-circuited and the PMOS 22 is turned on, the PM
The back gate and the source of the OS 18 are short-circuited. Therefore, in the analog switch 14 of the present invention, the NMOS 1
Since no potential difference occurs between the back gate and the source of No. 6, the threshold voltage of the NMOS 16 does not increase due to the substrate bias effect, and the on-resistance does not increase.

When the NMOS 20 is turned on, the back gate of the NMOS 16 becomes stable at a potential corresponding to the potential on the input side, and the threshold voltage of the NMOS 16 is determined. Similarly, the PMOS 22 is turned on, and the back gate of the PMOS 18 is stabilized at a potential corresponding to the potential on the input side,
The threshold voltage of the NMOS 16 is determined. NMOS 16
And the PMOS 18 have a gate-source potential difference of
It turns on when it becomes higher than the threshold voltage.

At this time, for example, when the potential on the output side is higher than the potential on the input side according to the potentials on the input side and the output side,
At the same time that the charge on the output side is discharged to the input side via the channels of the NMOS 16 and the PMOS 18 having a low on-resistance, the parasitic diode 26 and the PMO formed between the back gate and the source of the PMOS 18 are simultaneously discharged.
Since the charges are discharged through the channel path of S22, the charges on the output side can be discharged to the input side at high speed.

On the other hand, when the potential on the input side is higher than that on the output side, the NMOS 16 and P
At the same time as the output side is charged up to the input side potential via the channel of the MOS 18, the output side is charged up via the channel of the NMOS 20 and the path of the parasitic diode 24 formed between the back gate and the source of the NMOS 16. Therefore, the output side can be charged up to the potential on the input side at high speed.

Subsequently, when the decode signal φ goes low and the inverted decode signal φ # goes high, NM
The OSs 16 and 18 and the PMOSs 20 and 22 are both turned off, and the input side and the output side are electrically disconnected.

It is desirable for the analog switch to have symmetrical characteristics between input and output. Therefore, FIG.
An example of the circuit configuration will be disclosed below. The analog switch 14 shown in FIG. 3 is different from the analog switch 14 shown in FIG. 2 in that an NMOS 21 connected between the second terminal and the back gate of the NMOS 16 and an NMOS 21 connected between the second terminal and the back gate of the PMOS 18 PM connected to
It has an OS 23.

These NMOS 21 and PMOS 23
, A decode signal φ and an inverted decode signal φ # are input, and their back gates are connected to reference voltages VREFL and VREFH, respectively.
The basic operation of the analog switch 14 shown in FIG. 3 is the same as that of the analog switch 14 shown in FIG. 2, and as described above, the characteristics between the input and output are symmetric.
The operation speed and output accuracy can be improved.

When the input side and the output side of the analog switch 14 are electrically disconnected, the back gates of the NMOS 16 and the PMOS 18 are in a floating state. In this state, if the back gate is in a floating state, the threshold voltage becomes unstable,
Under the influence of noise, etc., NMOS 16 and PMOS
Since a leak current may flow between the source and the drain of the NMOS 18, it is preferable to fix the potentials of the back gates of the NMOS 16 and the PMOS 18 when the NMOS 20 and the PMOS 22 are turned off.

FIG. 4 is a circuit diagram showing another embodiment of the analog switch according to the present invention. The analog switch 14 'is different from the analog switch 14 shown in FIG. 2 in that the analog switch 14' further includes an NMOS 28 and a PMOS 30. The gate of the analog switch 14 'is supplied with an inverted decode signal φ and a decode signal φ. Are connected to reference voltages VREFL and VREFH, respectively, and the drains are NMOS16 and PMOS, respectively.
18 back gates.

The basic operation of the analog switch 14 'is exactly the same as that of the analog switch 14 shown in FIG. In the NMOS 28 and the PMOS 30, the decode signal φ is at a low level, the inverted decode signal φ is at a high level,
That is, the NMOS 20 and the PMOS 22 are turned off, and the NMOS 16 and the PMOS 18 are turned on when the back gates are in a floating state, and conversely, turned off when the decode signal φ is at a high level and the inverted decode signal φ is at a low level. .

Therefore, NMOS 20 and PMOS 20
When 22 turns off, the back gate of NMOS 16
The reference voltage VREFL is fixed via the NMOS 28,
The back gate of the PMOS 18 is fixed to the reference voltage VREFH via the PMOS 30, so that the threshold voltages of the NMOS 16 and the PMOS 18 can be stabilized, and the NMOS 16 and the PMOS 18 are completely turned off. Can be prevented.

Further, the analog switch 14 shown in FIG.
FIG. 5 shows an example of a circuit configuration for making the input / output characteristics of the analog switch symmetrical as in the case of FIG. The analog switch 14 'shown in FIG. 5 is different from the analog switch 14' shown in FIG.
6 and an NMOS 21 connected between the second terminal and the back gate of the PMOS 18.

These NMOS 21 and PMOS 23
, A decode signal φ and an inverted decode signal φ # are input, and their back gates are connected to reference voltages VREFL and VREFH, respectively.
The basic operation of the analog switch 14 'shown in FIG.
This is the same as the analog switch 14 'shown in FIG. 4 and its input / output characteristics are symmetrical, so that the operation speed and output accuracy can be further improved.

The analog switch of the present invention is basically as described above. In the above embodiment, the NMO
As an example of means for fixing the potential of the back gate of S16 and PMOS 18, as shown in FIG.
Although S28 and PMOS 30 have been described, the present invention is not limited to this, and any circuit configuration may be used as long as the potential of the back gate can be fixed. Good.

Further, in the above embodiment, an example in which the analog switch of the present invention is applied to a reference voltage circuit has been described so as to be easily compared with the prior art. However, the present invention is not limited thereto. It goes without saying that the analog switch of the present invention can be used for various applications as an analog switch that requires high speed and high accuracy, such as being used as a sample switch of a sample and hold circuit.

Although the analog switch according to the present invention has been described in detail, the present invention is not limited to the above-described embodiment.
Of course, various improvements and modifications may be made without departing from the spirit of the present invention.

[0036]

As described in detail above, the analog switch of the present invention basically includes an analog switch having a first NMOS and a first PMOS connected between a first terminal and a second terminal. In the switch, further, a second NMOS is connected between the first terminal and the back gate of the first NMOS, and a second PMOS is connected between the first terminal and the back gate of the first PMOS. Things. According to the analog switch of the present invention, with the above configuration, when the first terminal and the second terminal are made conductive, no potential difference occurs between the source and the back gate of the first NMOS. The threshold voltage of the first NMOS and the first PMOS does not increase, and the ON resistance does not increase, the analog switch can be operated at high speed, and the output accuracy of the analog switch can be improved. it can. Further, since the analog switch of the present invention can be manufactured using a normal manufacturing process, it can be manufactured at low cost without increasing the cost.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram illustrating a configuration of an embodiment of a reference voltage circuit using an analog switch according to the present invention.

FIG. 2 is a configuration circuit diagram of an embodiment of an analog switch according to the present invention.

FIG. 3 is a configuration circuit diagram of another embodiment of the analog switch of the present invention.

FIG. 4 is a configuration circuit diagram of another embodiment of the analog switch of the present invention.

FIG. 5 is a configuration circuit diagram of another embodiment of the analog switch of the present invention.

FIG. 6 is a configuration circuit diagram of an example of a conventional reference voltage circuit.

FIG. 7 is a configuration circuit diagram of another example of a conventional reference voltage circuit.

[Explanation of symbols]

10, 32, 36 Reference voltage circuit 12 Ladder resistor 14, 14 ', 34, 38 Analog switch 16, 20, 21, 28 N-type MOS transistor (N
MOS) 18, 22, 23, 30 P-type MOS transistor (P
MOS) 24, 26 Parasitic diode R Resistance element VREFH, VREFL Reference voltage A, B, C Connection point

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J022 AB03 BA01 CA10 CB01 CF07 CG01 5J055 AX05 AX11 BX17 CX00 DX13 DX14 DX17 DX22 DX44 DX53 DX73 DX83 EY12 EY23 EY29 GX01 GX02

Claims (2)

[Claims] 1. An analog switch having a first N-type MOS transistor and a first P-type MOS transistor connected between a first terminal and a second terminal, wherein the analog switch further comprises: A second N-type MOS connected between the first N-type MOS transistor and the back gate;
An S transistor, the first terminal, and the first P-type MO.
A second transistor connected to the back gate of the S transistor;
An analog switch comprising: a P-type MOS transistor. 2. The analog switch according to claim 1, further comprising: means for fixing a potential of a back gate of said first N-type MOS transistor when said second N-type MOS transistor is turned off. Means for fixing the potential of the back gate of the first P-type MOS transistor when the second P-type MOS transistor is turned off.