JP2000077963A - amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform gain control to one of control voltage levels at a high frequency part of a portable terminal transmitting part over a wide range of >=70 dB and in a linear way (flatness ±1 dB). SOLUTION: A signal input part 34 is connected to a signal output part 35 via a signal line 55 consisting of at least two or more pieces of serial variable resistances 51 and 52. Parallel variable resistances 53 and 54 are connected between parts 34 and 35 and a ground line 57 respectively. A gain control line 56 is connected to these resistances 51 to 54 respectively and the reference voltage application parts 23, 27, 31 and 33 are connected to each of the resistances 51 to 54 Then, a gain control voltage application part 19 is connected to each of the resistances 51 to 54 via the line 56.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier capable of amplifying a high-frequency signal and changing a gain by a control voltage, and more particularly to an integrated circuit used in a high-frequency section of a transmission section of a mobile communication terminal. The present invention relates to an amplifier as an integrated semiconductor device.

[0002]

2. Description of the Related Art Recently, in the field of mobile communications, the CDMA system has become one of the world standards as an access means.
In such a communication system, a near-far problem that a code error rate increases and communication quality deteriorates due to an increase in leakage power to an adjacent channel with a decrease in the distance between the mobile terminal and the base station is a major problem. It has become.

In order to overcome such a problem, it is necessary to adjust an output signal corresponding to the distance between the portable terminal and the base station. Specifically, the mobile terminal transmission unit needs to perform gain control over a wide range with a gain control width of 70 dB or more due to the size of the cell range of the base station. Moreover, CDM
As a feature of the A method, extremely high-precision gain control is performed at a certain distance from a base station. Therefore, gain control excellent in flatness ± 1 dB linearity is essential.

[0004] In addition, when the gain is attenuated in the portable terminal transmitter, the noise figure is degraded.
When the gain is attenuated over a wide range of B or more, it becomes difficult to discriminate the level of the carrier signal from the level of the other noise signals, and the communication quality deteriorates. Therefore, in order to solve such a problem, it is necessary to perform gain control in a high frequency section of about 500 MHz or higher where the carrier signal level is high so that the carrier signal level can easily be distinguished from other noise signal levels. It is.

Conventionally, in order to perform gain control excellent in linearity over a wide range of gain control width of 70 dB or more and flatness of ± 1 dB in a portable terminal transmitting section, conventionally, a point at which a gain largely changes in a high frequency section is used. A semiconductor device that performs two types of gain control, that is, a mounted first semiconductor device that performs step control by means of a step, and a mounted second semiconductor device that performs continuous control using a range in which the gain changes linearly in the intermediate frequency section. The devices were manufactured separately and connected by external circuits and combined. In mobile terminals, such gain control is performed by a separate semiconductor device having a built-in microcomputer logic.

[0006] The two types of gain control are performed by a single semiconductor device constituting a high-frequency section for gain control with good linearity over a wide range such as a gain control width of 70 dB or more and a flatness of ± 1 dB. This was because it was difficult to do so.

Hereinafter, an amplifier as a typical semiconductor device for performing gain control in a conventional mobile communication terminal transmitter will be described.

FIG. 19 is a circuit diagram showing a configuration of an amplifier (semiconductor device) that performs gain control in a stepwise manner in a high frequency section of a conventional mobile communication terminal transmitting section. With such an amplifier, step control of gain is performed using a point at which the gain changes greatly.

As shown in FIG. 19, this amplifier has a signal line 74 composed of a series (series) variable resistor 71 connecting an input terminal 14 as a signal input section and an output terminal 15 as a signal output section. In addition, parallel (shunt) variable resistors 72 and 73 are connected between the input terminal 14 and the output terminal 15 and the ground line 76, respectively. The ground line 76 is connected to a ground GND which is a basic potential portion. The gain control line 75 includes variable resistors 71, 72,
73. In this amplifier, the gain control voltage application terminal 4 serving as a gain control voltage application unit includes a variable resistor 71,
72 and 73 are connected to each other via a gain control line 75.

The variable resistors 71, 72, and 73 are respectively formed by connecting the resistors 7, 5, and 13 to the gates of the field effect transistors 6, 1, and 9, respectively. The drain of the field effect transistor 6 constituting the variable resistor 71 is connected to the input terminal 14, and the source is connected to the output terminal 15. The drain of the field effect transistor 1 constituting the variable resistor 72 is connected to the input terminal 14 via the capacitor 2, and the source is connected to the capacitor 3 and the ground line 76.
Is connected to the ground GND. Further, the drain of the field effect transistor 9 forming the variable resistor 73 is connected to the output terminal 15 via the capacitor 10,
The source is connected to the ground GND via the capacitor 11 and the ground line 76.

Further, the gate of the field effect transistor 6 forming the variable resistor 71 is connected to the gain control voltage application terminal 4 via the resistor 7 and the gain control line 75, and the source of the field effect transistor 1 forming the variable resistor 72 is Are connected to the gain control voltage application terminal 4 via a gain control line 75, and the source of the field effect transistor 9 constituting the variable resistor 73 is connected to the gain control voltage application terminal 4 via the gain control line 75. A power supply voltage VDD (approximately 3 V, the battery voltage itself) provided from a lithium battery or the like is applied to the source of the field effect transistor 6 forming the variable resistor 71, and the field effect transistors forming the variable resistors 72 and 73 respectively. GND potentials are applied to the gates 1 and 9 via the resistors 5 and 13.

Here, each of the capacitors 2, 3, 10, 11
Block the application of a DC voltage, and the resistors 7, 5, 14 respectively play a role of blocking the intrusion of high frequency signals.

In this amplifier, the gain is adjusted in the form of adjusting the amount of attenuation, and the illustration of the original amplification function section for increasing the gain is omitted. Only the circuit of FIG. 19 functions as an attenuator.

FIG. 20 shows that the threshold voltage Vth of each of the field effect transistors 6, 1, 9 in the amplifier of FIG.
FIG. 9 is a characteristic diagram illustrating a state of gain control when the voltage is 1.0 V. FIG. 20A shows a gain control voltage Vc-gain (attenuation) characteristic of a field-effect transistor (Series FET) 6 constituting the variable resistor 71 in series. Also,
FIG. 20 (b) shows the gain control voltage Vc-gain (attenuation) characteristic of the field effect transistors (ShuntFETs) 1 and 9 constituting the parallel variable resistors 72 and 73, and the solid line shows the characteristic for two. The broken line is the characteristic for one. FIG.
FIG. 19C is a combination of the characteristics of FIGS. 20A and 20B.
5 shows the gain control voltage Vc-gain (attenuation) characteristic of the amplifier of FIG.

As described above, when the threshold voltage Vth of each of the field effect transistors 6, 1, 9 is -1.0 V, the gain of the field effect transistors 1, 9 of the parallel variable resistors 72, 73 is When the control voltage Vc is 0.7V to 1.V.
46d in proportion to the change of the gain control voltage Vc in the range of 0V
The gain (attenuation) changes within a range of 14 dB with a gradient of B / V, and the gain control voltage Vc of the series variable resistor 71 is set within a range of 2.0 V to 2.3 V for the field effect transistor 6. The gain (attenuation amount) changes in a range of 15 dB with a gradient of 50 dB / V in proportion to the change of Vc. When the gain control voltage Vc is in a range of 1.0 V to 2.0 V, the gain control is not performed, and the gain control is not performed. The gain (attenuation amount) maintains a constant value regardless of the change in the voltage Vc. That is, the gain control voltage section ΔV in which no gain control is performed is as large as 1.0 V.

FIG. 21 shows that in the amplifier of FIG. 19, the threshold voltage Vth of each of the field-effect transistors 6, 1, 9 is-
FIG. 9 is a characteristic diagram showing a state of gain control when the voltage is 2.0 V. FIG. 21A shows a gain control voltage Vc-gain (attenuation) characteristic of a field-effect transistor (Series FET) 6 constituting the variable resistor 71 in series. Also,
FIG. 21B shows the gain control voltage Vc-gain (attenuation) characteristic of the field effect transistors (ShuntFETs) 1 and 9 constituting the parallel variable resistors 72 and 73, and the solid line shows the characteristic for two. The broken line is the characteristic for one. FIG.
(A) and (b) are the same as FIGS. 20 (a) and (b).
FIG. 21C shows a gain control voltage Vc-gain (attenuation) characteristic of the amplifier of FIG. 19 in which the characteristics of FIGS. 21A and 21B are combined.

As described above, when the threshold voltage Vth of each of the field effect transistors 6, 1, and 9 is -2.0 V, the gain control voltage Vc of the field effect transistor 6 of the series variable resistor 71 is In the range of 1.0 V to 1.3 V, the gain (attenuation) changes in the range of 15 dB with a gradient of 50 dB / V in proportion to the change of the gain control voltage Vc. For the gains 1 and 9, the gain (attenuation) changes in a range of 14 dB with a gradient of 46 dB / V in proportion to the change of the gain control voltage Vc in a range of 1.7 V to 2.0 V, When the gain control voltage Vc is in the range of 1.3 V to 1.7 V, gain control is not performed, and the gain (attenuation amount) maintains a constant value regardless of a change in the gain control voltage Vc. That is, the gain control voltage section ΔV in which the gain control is not performed is as large as 0.4 V.

In the amplifier having the above characteristics, when performing step control, the gain control voltage Vc is switched stepwise, and the gain (attenuation amount) is switched stepwise at a constant rate.
In combination with continuous gain control at the intermediate frequency, linear (±
(1 dB or less) gain control is realized.

FIG. 22 shows an example of a step control characteristic diagram of the above-described amplifier which performs gain control in the high frequency section. Usually, the number of steps of the gain is set to about 2 to 10 steps. In FIG. 22, the gain control width of 30 dB is 15 d.
Low, Middle, Hig in ascending order of gain for each B
h is set to three steps as each mode. Symbols V _CL , V _CM , and V _CH are gain control voltages corresponding to the respective modes, and symbol P _OUT indicates the magnitude of the output signal. Although the gain control width is 29 dB in FIGS. 20 and 21, the gain control width is rounded up to 30 dB in order to simplify the calculation.

On the other hand, as an amplifier (intermediate frequency amplifier) which is used in combination with an amplifier (high frequency amplifier) which performs stepwise gain control as shown in FIG. Although illustration of a specific circuit diagram is omitted, a device using a silicon bipolar transistor is mainly used.

An amplifier that performs gain control using a bipolar transistor can perform gain control with a relatively wide range and excellent linearity at a small signal level due to the characteristics of the circuit configuration. Therefore, in an amplifier that performs gain control in the intermediate frequency section, continuous control is performed using the fact that the gain changes linearly.

FIG. 23 shows an increase in gain control in the intermediate frequency section.
It is a continuous control characteristic diagram of a breadth bin. As shown in FIG.
At signal level, gain control width is 40 dB, flat
Ness ± 1dB, a relatively wide range and excellent linearity
Control is possible, and each mode of step control in the high-frequency section is possible.
Continuous control is performed in the intermediate frequency section for the mode. Symbol V
_CFINEIs the fine gain control voltage in each mode.
No. P_OUTIndicates the magnitude of the output signal.

FIG. 24 is a gain control characteristic diagram of a transmitting section of a mobile communication terminal in which step control and continuous control are combined. By combining each mode of the step control of FIG. 22 and the continuous control of FIG. 23, a gain control width of 70 dB or more and a flatness of ± 1 dB in a wide range and excellent linearity can be achieved in the transmitting section of the mobile communication terminal. Becomes

As described above, conventionally, in a mobile communication terminal transmitting section, a gain control width of 70 dB or more and a flatness of ± 1 dB in a wide range and excellent linearity are obtained by performing step control in a high frequency section. A device to be controlled and a device to be continuously controlled in the intermediate frequency section are separately produced, and two types of amplifiers (semiconductor devices) each having a semiconductor chip mounted thereon are connected and combined by an external circuit.

The reason is that, in the above-described conventional configuration, only one stage of the series variable resistor 71 by the field effect transistor 6 is connected between the input terminal 14 and the output terminal 15, and the gain control amount with respect to the control voltage is controlled. Since the linear portion of cannot be as wide as about 15 to 18 dB and the gain control width is as narrow as about 30 dB, the gain control width is 70 dB or more and the flatness ±
This is because it is difficult to perform gain control over a wide range of 1 dB and excellent linearity with one amplifier.

[0026]

However, when two types of separate amplifiers (semiconductor devices) are used for separate gain control as described above, there are the following problems.

The first problem is that when an amplifier that performs gain control in a high frequency section is used for step control, the series variable resistor 7
A non-gain control voltage section ΔV in which gain control cannot be performed exists between a gain control voltage range in which 1 performs linear gain control operation and a gain control voltage range in which parallel variable resistors 72 and 73 perform linear gain control operation. Therefore, when the gain (attenuation) is switched in a step-like manner by switching the gain control voltage Vc in a step-like manner, even if the gain control voltage Vc is accurately switched in accordance with the gain (attenuation), a high precision is obtained. It was difficult to perform gain control. In other words, in order to accurately switch the gain (attenuation), the gain control voltage V
There was a problem that the selection of c became complicated.

The second problem is that separate gain control (step control, continuous control) is used together, that is, separate gain control (step control, continuous control) is performed by two types of separate amplifiers (semiconductor devices). As can be seen from the gain control characteristic diagram of FIG. 24, at the time of switching each mode of the step control, since the setting of the gain control voltage Vc is also changed at the same time as the continuous control, a difference occurs in the gain before and after the mode switching. As a result, desired flatness characteristics cannot be realized, and it becomes difficult to achieve high precision gain control. In addition, the setting of the control voltage in the microcomputer / logic section is required to be two types, which is complicated. Further, there is a problem that a circuit configuration becomes complicated and a space becomes large in the mobile communication terminal.

A first object of the present invention is to provide an amplifier which can perform high-precision gain control when performing step control or can easily select a control voltage.

A second object of the present invention is to provide an amplifier capable of linearly controlling the gain of one control voltage over a wide range.

[0031]

In order to achieve the first object, an amplifier according to the present invention comprises a signal line for connecting a signal input section and a signal output section, the signal line comprising, for example, a series variable resistor by a field effect transistor. A parallel variable resistor connected to each of the signal input and signal output units and the ground line, and a gain control line connected to each of the variable resistors,
A reference voltage application unit is connected to each of the variable resistors, and a gain control voltage application unit is connected to each of the variable resistors via a gain control line.

According to this configuration, by appropriately setting the reference voltage to be applied to each variable resistor, when a common gain control voltage is applied to the series variable resistor and the parallel variable resistor to perform gain control, the series It is possible to reduce the gain control voltage section where the gain control cannot be performed between the gain control voltage range where the variable resistor performs linear gain control operation and the gain control voltage range where the parallel variable resistor performs linear gain control operation. Thus, high-precision gain control can be performed when step control is performed, or the control voltage can be easily selected.

When the field effect transistors forming the series variable resistor and the parallel variable resistor are all of a single gate type, the gate width of the field effect transistor forming the serial variable resistor and the parallel variable resistor is reduced. By setting equal, the gain control characteristics of the series variable resistor and the parallel variable resistor can be made the same.

If the field-effect transistor constituting the series variable resistor is a multi-gate type, the gain control width can be increased and the distortion can be reduced.

A gain control voltage section in which gain control cannot be performed between a gain control voltage range in which a serial variable resistor performs a linear gain control operation and a gain control voltage range in which a parallel variable resistor performs a linear gain control operation. If the voltage is less than 0.15 V, gain control can be performed with high accuracy when performing step control, or control voltage can be easily selected.

Further, the voltage value applied to the reference voltage applying unit for the parallel variable resistor is a gain control voltage in which the variable resistor in parallel performs the linear gain control operation in a gain control voltage range in which the variable resistor performs the linear gain control operation. By setting the range to be smoothly continuous, high-precision gain control can be performed when performing step control, or control voltage can be easily selected.

Further, a common reference voltage may be applied to the gates of the respective field effect transistors of the parallel variable resistors via the resistors. In this case, the number of reference voltage sources can be reduced.

In order to achieve the second object, the amplifier according to the present invention includes, in the above-described amplifier configuration, at least a series variable resistor constituted by, for example, a field-effect transistor for connecting a signal input section and a signal output section. It has two or more multi-stage configurations. In some cases, a capacitor is inserted between each field-effect transistor constituting a plurality of series variable resistors.

According to this configuration, the operation of the series variable resistors by at least two or more field-effect transistors connected in multiple stages is shifted by the linear gain control operation range, and the linear operation ranges of the series variable resistors are added, respectively. Since each mode is switched with only one gain control voltage,
It is possible to eliminate a difference in gain and perform a linear gain control operation for a control voltage with extremely high precision.

A configuration in which a gain control operation of a series variable resistor by at least two or more field-effect transistors connected in series in multiple stages is shifted by a linear gain control operation range, wherein at least two or more field-effect transistors connected in series There is a configuration in which a different reference voltage is applied to each source. In such a configuration, since gain control is performed with one gain control voltage, extremely high-precision gain control is possible. Further, the setting of the gain control operation voltage can be freely changed.

As another configuration, there is a configuration in which a different voltage is applied to each gate of at least two or more field effect transistors connected in series. In such a configuration,
Since the same reference voltage is applied to each source electrode of at least two or more field effect transistors for the series variable resistor, linear gain control can be performed with high accuracy even when the reference voltage fluctuates. Further, the setting of the gain control operation voltage can be freely changed.

As still another configuration, there is a configuration in which field-effect transistors having different threshold voltages are used for at least two or more field-effect transistors connected in series. In such a configuration, since gain control is performed with one gain control voltage, extremely high-precision gain control is possible. In addition, since the same reference voltage is applied to each source electrode of at least two or more field effect transistors for the series variable resistor, linear gain control can be performed with high accuracy even when the reference voltage fluctuates. . Furthermore, since the voltage application can be reduced, the circuit configuration can be simplified.

When the field effect transistors constituting the series variable resistor and the parallel variable resistor are all of a single gate type, the gate width of the field effect transistor constituting the series variable resistor and the parallel variable resistor is reduced. By setting equal, the gain control characteristics of the series variable resistor and the parallel variable resistor can be made the same.

If the field effect transistor forming the series variable resistor is of a multi-gate type, the gain control width can be increased and the distortion can be reduced.

Further, a common reference voltage may be applied to the gates of the respective field effect transistors of the parallel variable resistors via the resistors. In this case, the number of reference voltage sources can be reduced.

Further, the voltage applied to the reference voltage applying section corresponding to the input-side series variable resistor is higher than the voltage applied to the reference voltage applying section corresponding to the output-side series variable resistor. The series variable resistor on the side is set higher by a value corresponding to the gain control voltage range for performing the linear gain control operation, or the voltage value applied to the reference voltage application unit for the parallel variable resistor is changed by the serial variable resistor. By setting the variable resistor parallel to the gain control voltage range for performing the linear gain control operation so that the gain control voltage range for performing the linear gain control operation is smoothly continuous, high-precision gain control can be performed when performing continuous control. It can be carried out.

Further, the voltage applied to the reference voltage applying section corresponding to the input-side series variable resistor is higher than the voltage applied to the reference voltage applying section corresponding to the output-side series variable resistor. By setting, each degradation point of the distortion characteristics of the series variable resistor on the input side, the series variable resistor on the output side, and the parallel variable resistor can be dispersed, and the superimposition of the deteriorated distortion power can be eliminated. In addition, the deterioration of the distortion characteristic can be prevented by using the operation in combination with the parallel variable resistor.

As described above, means for solving the problem are provided by these configurations.

According to the first configuration, an appropriate reference voltage is applied to each of the serial variable resistors and the parallel variable resistors, so that each variable resistor has a gain within a gain control voltage range in which a linear gain control operation is performed. It is possible to reduce or eliminate a gain control voltage section in which control cannot be performed.

The variable resistance composed of at least two or more field effect transistors connected in multiple stages in series by the second configuration increases the series resistance between the signal input section and the signal output section, In addition, the operation of the series variable resistor by at least two or more field-effect transistors connected in multiple stages is shifted by the linear gain control operation range, and the linear operation range of the series variable resistor is added to each other, so that a linear gain with respect to the control voltage is obtained. It is possible to extend the control range.

[0051]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic block diagram showing the configuration of an amplifier (semiconductor integrated circuit device) according to the first embodiment of the present invention, and FIG. 2 is a specific example of the amplifier according to the first embodiment of the present invention. FIG. 2 is a circuit diagram showing a simple configuration. This amplifier is integrated on a single semiconductor substrate (GaAs) and performs stepwise gain control in a high frequency section of a mobile communication terminal transmitting section. It should be noted that such a configuration can be integrated even on a silicon substrate, and especially when it is formed of silicon, the microcomputer and logic can be integrated at the same time.

With such an amplifier, gain step control is performed using a point at which the gain changes greatly, and 70 dB or more can be obtained by using the amplifier in combination with an amplifier that performs continuous (linear) gain control in the intermediate frequency section. To realize gain control over a wide range.

As shown in FIGS. 1 and 2, this amplifier has a signal line 74 composed of a series variable resistor 71 connecting an input terminal 14 as a signal input section and an output terminal 15 as a signal output section. Input terminal 14 and output terminal 1
5 and a variable resistor 7 in parallel with each other between ground line 76.
2, 73 are connected. The ground line 76 is connected to a ground GND which is a basic potential portion. The gain control line 75 is connected to the variable resistors 71, 72, 73. In this amplifier, reference voltage application terminals 8, 12A and 12B serving as reference voltage application units are connected to variable resistors 71, 72 and 7 respectively.
3 and reference voltage application terminals 8, 12A, 1
2B, the reference voltages Vref11, Vref12, V
ref13 is provided. Also, the gain control voltage application terminal 4 serving as a gain control voltage application unit is connected to the variable resistors 71, 72, 7
3 are connected to each other via a gain control line 75. Note that a configuration in which a common reference voltage is applied to the parallel variable resistors 72 and 73 may be employed. This is the same in the following embodiments.

The variable resistors 71, 72, and 73 are formed by connecting resistors 7, 5, and 13 to the gates of the field effect transistors 6, 1, and 9, respectively. The drain of the field effect transistor 6 constituting the series variable resistor 71 is connected to the input terminal 14, and the source is connected to the output terminal 15. The drain of the field effect transistor 1 constituting the parallel variable resistor 72 on the input side is connected to the input terminal 14 via the capacitor 2, and the source is connected to the capacitor 3.
And a ground line 76 to the ground GND. The drain of the field effect transistor 9 constituting the parallel variable resistor 73 on the output side is connected to the capacitor 1.
0 to the output terminal 15, and the source is connected to the ground GND via the capacitor 11 and the ground line 76.
It is connected to the.

Further, the gate of the field effect transistor 6 forming the variable resistor 71 is connected to the gain control voltage application terminal 4 via the resistor 7 and the gain control line 75, and the source of the field effect transistor 1 forming the variable resistor 72 is Are connected to the gain control voltage application terminal 4 via a gain control line 75, and the source of the field effect transistor 9 constituting the variable resistor 73 is connected to the gain control voltage application terminal 4 via the gain control line 75.

The reference voltage Vref11 is applied to the source of the field effect transistor 6 forming the variable resistor 71 from the reference voltage application terminal 8, and the gates of the field effect transistors 1 and 9 forming the variable resistors 72 and 73 are connected to the gates. Are reference voltages Vref12 and Vref13 from reference voltage application terminals 12A and 12B via resistors 5 and 13, respectively.
Is applied.

Here, each of the capacitors 2, 3, 10, 11
Block the application of a DC voltage, and the resistors 7, 5, 13 respectively play a role of blocking the intrusion of high frequency signals.

The resistors 7, 5, and 13 have their lower and upper limits set as follows, for example, in order to prevent intrusion of high-frequency signals. First, the lower limit is 1 kΩ. The reason for the setting is that if the isolation is not more than 20 dB, a high-frequency signal enters and the control characteristics are affected, such as an increase in loss. When the above value is set, an isolation of 20 dB or more is obtained.

The upper limit is 100 kΩ. The setting
The fixed reason is the gate leakage current of the field effect transistor.
For example, when a current of 1 μA flows,
When the resistance value of the resistor inserted into the gate is 100 kΩ,
The voltage drop V _DROPIs V_DROP= 1 × 10^-6× 100 × 10^Three= 0.1 (V), and when the resistance value exceeds 100 kΩ, the control voltage
This exceeds 0.1V, and cannot be ignored in gain control characteristics.
This is because

In this amplifier, the gain is adjusted in the form of adjusting the amount of attenuation, and the illustration of the original amplifying function for increasing the gain is omitted. Only the circuit in FIG. 2 functions as an attenuator. This is the same in the following embodiments.

FIG. 3 shows the amplifier of FIG. 2 in which the threshold voltage Vth of each of the field effect transistors 6, 1, 9 is -0.0.
FIG. 9 is a characteristic diagram illustrating a state of gain control when Vref11 is set to 1.8 V and Vref12 and Vref13 are both set to 1.0 V when the voltage is 7V.
FIG. 3A shows a gain control voltage V of a field-effect transistor (SeriesFET) 6 forming a serial variable resistor 71.
13 shows a c-gain (attenuation) characteristic. FIG.
(B) shows the gain control voltage Vc-gain (attenuation) characteristics of the field effect transistors (ShuntFETs) 1 and 9 constituting the parallel variable resistors 72 and 73. The solid line shows the characteristics of two, and the broken line shows the characteristics. This is the characteristic of one piece. FIG. 3C shows a gain control voltage Vc-gain (attenuation) characteristic of the amplifier of FIG. 2 in which the characteristics of FIGS. 3A and 3B are combined.

As described above, when the threshold voltage Vth of each of the field effect transistors 6, 1, 9 is -0.7 V, the gain control voltage Vc of the field effect transistor 6 of the series variable resistor 71 is The gain (attenuation) changes in a range of 15 dB with a slope of 50 dB / V in proportion to a change of the gain control voltage Vc in a range of 1.1 V to 1.4 V, and the field effect transistors of the parallel variable resistors 72 and 73 are changed. For 1, 9 the gain (attenuation) changes in a range of 14 dB with a gradient of 46 dB / V in proportion to the change of the gain control voltage Vc when the gain control voltage Vc is in the range of 1.4 V to 1.7 V, The gain control voltage section ΔV in which no gain control is performed becomes 0V. In this case, the gain control width is 15 dB with the series variable resistor 71,
Since it becomes 14 dB by the parallel variable resistors 72 and 73, it becomes 29 dB in total.

FIG. 4 is a characteristic diagram of the gain control with respect to the gain control voltage Vc of the amplifier according to the second embodiment in which the gain control is performed in the high frequency section of the mobile communication terminal transmitting section as shown in FIG.

The operation of the amplifier having the above configuration will be described. The portable terminal is driven at a voltage of up to about 3.0 V by a lithium battery or the like. The threshold voltage of the field-effect transistor indicates a bias at which the variable resistor starts the gain control operation, and the field-effect transistors 6, 1, and 2 for the series variable resistor 71 and the parallel variable resistors 72 and 73. All the threshold voltages of No. 9 are equal. In this example, the voltage is -0.7V. The reference voltages Vref11 and Vref1 as described above are respectively applied to the reference voltage application terminal 8 of the series variable resistor 71 and the reference voltage application terminals 12A and 12B of the parallel variable resistors 72 and 73.
2, Vref13 is applied.

Here, the variable resistance formed by the field effect transistor is completely turned off when the gate-source voltage VGS becomes lower than the threshold voltage Vth of the field effect transistor (VGS ≦ Vth). And the resistance value becomes maximum. The gate-source voltage VGS of each field-effect transistor is represented by the difference (VG-VS) between the gate voltage VG and the source voltage VS, and the gain control voltage Vc and the reference voltages Vref11, Vref12, and Vre.
The resistance value changes in combination with f13. Therefore, the reference voltages Vref11, Vref12, Vref
Changing the set value of 13 makes it possible to control the range of the gain control voltage Vc at which the gain of the variable resistor can be controlled.

Therefore, the reference voltage V of the series variable resistor 71 is
Reference voltage Vr of variable resistors 72 and 73 in parallel with ref11
By appropriately setting ef12 and Vref13, a gain control voltage section ΔV where gain control cannot be performed between the gain control operation range of the series variable resistor 72 and the gain control operation range of the parallel variable resistors 72 and 73 is set. To 0.1
It can be a small value of less than 5V. For the gain control voltage Vc, the series variable resistor 71 and the parallel variable resistor 7
In FIG. 3, the series variable resistor 71 is divided by a parallel variable resistor 72, 73 on the low voltage side.
Is on the high voltage side, but may be reversed.

Here, the gain control voltage section ΔV is 0.15
The reason why there is an inconvenience when V is V or more will be described.
Normally, step control of about 5 steps is often used, and control is performed 7 to 8 dB per step, and the gradient is about 50 d.
Since it is B / V, the control voltage is set in 0.15 V steps. Therefore, if the gain control voltage section ΔV in which the gain control cannot be performed is 0.15 V or more, there is a point where the gain does not change even if the control voltage is changed, so that the gain control cannot be performed with high accuracy.

The lower limit of the gain control voltage section ΔV where the gain control cannot be performed is 0V. Note that there is basically no problem even if the control characteristics overlap. However, since the gradient of the overlapped portion becomes steeper, the setting of the control voltage needs to be changed when performing the above-described five-step control.

As described above, by setting the gain control voltage section ΔV in which the gain control cannot be performed to a small value of less than 0.15 V, the gain control range of the series variable resistor 71 and the gain of the parallel variable resistors 72 and 73 are reduced. The control range can be connected so as to be smoothly continuous. In the step control, high-precision gain control is possible, or the gain control voltage V
Selection of c becomes easy.

The gain control voltage V is applied to the gain control voltage application terminal 4.
When a voltage of 0 to 1.1 V is applied as c (FIG. 4: gain control voltage range (a)), the series variable resistor 7
Since the resistance value R _ON (T-FET) of 1 indicates the maximum value and the resistance value R _ON (S-FET) of the parallel variable resistors 72 and 73 indicates the minimum value, the signal input from the input terminal 14 is attenuated. There is no increase in the gain, and the magnitude P of the output signal from the output terminal 15
_OUT is at a minimum.

When a voltage exceeding 1.1 V is applied to the gain control voltage application terminal 4 (FIG. 4: gain control voltage range (b)), the resistance values R _ON (S −FET) shows the minimum value, and the resistance value R _ON (T-FET) of the series variable resistor 71 starts to decrease, so that the magnitude P _OUT of the output signal increases. Usually, the gain control voltage range in which the variable resistor by the field effect transistor performs the linear gain control operation is about 0.2 to 0.3 V,
Until a voltage of 1.4 V is applied to the gain control voltage application terminal 4, the gain linearly increases by 15 dB.

When a voltage of 1.4 V is applied to the gain control voltage application terminal 4 (FIG. 4: gain control voltage range (c)), the resistance value R _ON (T− FE
T) indicates the minimum value, and the resistance value R _ON (S-FET) of the parallel variable resistors 72 and 73, which has indicated the minimum value, starts to increase, so that the magnitude P _OUT of the output signal increases. Until a voltage of 1.7 V is applied to the gain control voltage application terminal 4,
The gain linearly increases by 14 (= 2 × 7) dB with a sensitivity different from that in the range (b) of the gain control voltage 1.1 to 1.4 V.

When a voltage of 1.7 V is applied to the gain control voltage application terminal 4 (FIG. 4: gain control voltage range (d)), the resistance value R _ON (T-FE) of the series variable resistor 71 is set.
T) indicates the minimum value and the parallel variable resistors 72, 73
Since the resistance value R _ON (S-FET) of the output signal indicates the maximum value, the magnitude P _OUT of the output signal becomes maximum. At this time, the gain control width of this amplifier is 29 dB. Even when a voltage of 1.7 V or more is applied to the gain control voltage application terminal 4, the resistance value R _ON (T-FET) of the series variable resistor 71 is the minimum value, and the resistance value R _ON of the parallel variable resistors 72 and 73 ( S-FET) shows the maximum value, so that the magnitude P _OUT of the output signal remains maximum.

When the amplifier having the above-described characteristics performs step control, the gain control voltage Vc is switched stepwise, and the gain (attenuation amount) is switched stepwise at a constant rate.
In combination with continuous gain control at the intermediate frequency, linear (± 1 dB or less) gain control is realized over a wide range of gain control width of 70 dB or more.

According to the present embodiment, by providing appropriate reference voltages Vref11, Vref12, Vref13 to the series variable resistors 71 and the parallel variable resistors 72, 73, respectively, the respective variable resistors 71, 72, 73 are provided. Since the gain control voltage section in which the gain control cannot be performed in the gain control voltage range for performing the linear gain control operation can be reduced or eliminated, the gain control can be performed with high precision when performing the gain step control. It is possible to do.

In the above embodiment, the field effect transistors 6, 1, 9 constituting the variable resistors 71, 72, 73 are of single gate type, but have the same gate width Wg (of course, the same). By using the same gate length), the gain control characteristic by the variable resistor 71 and the gain control characteristic by the two variable resistors 72 and 73 can be matched, and the linearity of the combined characteristics can be further improved. Is possible.

Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 5 is a circuit diagram showing a specific configuration of the amplifier according to the second embodiment of the present invention. This amplifier is a multi-gate (multiple control electrode) type, in this example, a dual-gate type field effect transistor 6A instead of the single gate type field effect transistor 6 in FIG.
And each gate of the field effect transistor 6A is connected to a resistor 7
A and 7B are connected to the gain control voltage application terminal 4 via a gain control line 75, and the other configuration is the same as that of the amplifier of FIG.

FIG. 6 shows that the threshold voltage Vth of each of the field effect transistors 6A, 1, 9 in the amplifier of FIG.
In the case of 0.7V, Vref11 is set to 1.8V
Vref12 and Vref13 are both set to 1.0
FIG. 9 is a characteristic diagram showing a state of gain control when the gain is set to V; FIG. 6A shows a gain control voltage Vc-gain (attenuation) characteristic of a field-effect transistor (Series FET) 6 constituting the variable resistor 71 in series. FIG.
(B) shows the gain control voltage Vc-gain (attenuation) characteristics of the field effect transistors (ShuntFETs) 1 and 9 constituting the parallel variable resistors 72 and 73. The solid line shows the characteristics of two, and the broken line shows the characteristics. This is the characteristic of one piece. FIG. 6C shows a gain control voltage Vc-gain (attenuation) characteristic of the amplifier of FIG. 6 in which the characteristics of FIGS. 6A and 6B are combined.

As described above, when the threshold voltage Vth of each of the field effect transistors 6, 1, 9 is -0.7 V, the gain control voltage Vc of the field effect transistor 6 of the series variable resistor 71 is The gain (attenuation) changes in a range of 18 dB with a gradient of 60 dB / V in proportion to a change in the gain control voltage Vc in a range of 1.1 V to 1.4 V, and the field effect transistors of the parallel variable resistors 72 and 73 are changed. For 1, 9 the gain (attenuation) changes in a range of 14 dB with a gradient of 46 dB / V in proportion to the change of the gain control voltage Vc when the gain control voltage Vc is in the range of 1.4 V to 1.7 V, The gain control voltage section ΔV in which no gain control is performed becomes 0V. In this case, the gain control width is 18 dB with the series variable resistor 71,
Since it becomes 14 dB by the parallel variable resistors 72 and 73, it becomes 32 dB in total.

According to this embodiment, the field effect transistor 6A constituting the variable resistor 71 is of a dual gate type, so that the gain control width is increased by about 3 dB and the distortion characteristic is improved by about 3 dBc. You. As described above, the field effect transistor 6 forming the variable resistor 71
By using a multi-gate type field effect transistor as A, the gain control width can be increased and distortion can be reduced. Other effects are the same as those of the amplifier using the single-gate field effect transistor 6.

Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 7 is a schematic block diagram showing a configuration of an amplifier (semiconductor integrated circuit device) according to the third embodiment of the present invention, and FIG. 8 is a specific example of the amplifier according to the third embodiment of the present invention. FIG. 2 is a circuit diagram showing a simple configuration. This amplifier is integrated on one semiconductor substrate (GaAs). It should be noted that such a configuration can be integrated even on a silicon substrate, and especially when it is formed of silicon, the microcomputer and logic can be integrated at the same time.

With such an amplifier, by continuously controlling the gain using a region where the gain changes linearly, gain control excellent in linearity over a wide range can be performed as compared with the case where only one series variable resistor is used. Can be realized. As a result, it is possible to realize gain control excellent in linearity over a wide range independently without combining with gain control of the amplifier in the intermediate frequency section. By increasing the number of variable resistors in series, gain control with excellent linearity can be realized over a wide range of 70 dB or more.

As shown in FIGS. 7 and 8, at least two or more series variable resistors 51 and 52 for connecting an input terminal 34 serving as a signal input section and an output terminal 35 serving as a signal output section, as shown in FIGS. A variable resistor 53, 54 is connected in parallel between each of the input terminal 34 and the output terminal 35 and the ground line 57.
The ground line 57 is connected to a ground GND which is a basic potential portion. The gain control line 56 includes the variable resistor 5
1, 52, 53, 54. In this amplifier, reference voltage application terminals 23 and 2 serving as reference voltage application units are provided.
7, 31, 33 are connected to the respective variable resistors 51, 52, 53, 54, and reference voltage application terminals 23, 27, 31, 3
3 has a reference voltage Vref1, Vref2, Vref
3, Vref4. The gain control voltage application terminal 19 serving as a gain control voltage application unit is connected to the variable resistors 51 and 5.
2, 53, and 54 are connected via gain control lines 56. Note that a configuration in which a common reference voltage is applied to the parallel variable resistors 53 and 54 may be employed. This is the same in the following embodiments.

The above-described variable resistors 51, 52, 53, 54
Represent at least the field effect transistors 21 and
Resistors 22, 26, 20, 32 at the gates of 5, 16, 28
Are connected. Input side series variable resistor 51
Is connected to the input terminal 34, and the source is connected to one end of the capacitor 24. The drain of the field effect transistor 25 forming the output side series variable resistor 52 is connected to the capacitor 2.
4 is connected to the other end, and the source is connected to the output terminal 35. The drain of the field-effect transistor 16 forming the input side parallel variable resistor 53 is connected to the capacitor 17.
Is connected to the input terminal 34, and the source is connected to the ground GND via the capacitor 18 and the ground line 57. The drain of the field-effect transistor 28 constituting the parallel variable resistor 54 on the output side is connected to the output terminal 35 via the capacitor 29, and the source is connected to the ground GND via the capacitor 30 and the ground line 57. .

Further, the gate of the field effect transistor 21 forming the variable resistor 51 is connected to the gain control voltage application terminal 19 via the resistor 22 and the gain control line 56, and the field effect transistor 25 forming the variable resistor 52 is connected.
Is connected to the gain control voltage applying terminal 19 via the resistor 26 and the gain control line 56, and the source of the field effect transistor 16 forming the variable resistor 53 is connected to the gain control voltage applying terminal 19 via the gain control line 56. Field effect transistor 28 connected to form variable resistor 54
Are connected to the gain control voltage application terminal 19 via the gain control line 56.

The sources of the field effect transistors 21 and 25 forming the variable resistors 51 and 52 are connected to the reference voltages Vref1 and Vr from the reference voltage application terminals 23 and 27, respectively.
ef2 is applied to the gates of the field effect transistors 16 and 28 constituting the variable resistors 53 and 54, respectively, from the reference voltage application terminals 31 and 33 to the resistors 20 and 32, respectively.
The reference voltages Vref3 and Vref4 are applied through the terminals.

Here, each of the capacitors 17, 18, 24,
29, 30 block the application of the DC voltage, and
Reference numerals 2, 26, and 32 play a role of preventing the intrusion of the high-frequency signal.

For the resistors 20, 22, 26, and 32, the lower limit and the upper limit are set, for example, as follows in order to prevent intrusion of high-frequency signals. First, the lower limit is 1 kΩ. The setting reason is 20dB as isolation.
Otherwise, high frequency signals will invade and the loss will increase.
This is because the control characteristics are affected. When the above value is set, an isolation of 20 dB or more can be obtained.

The upper limit is 100 kΩ. The setting
The fixed reason is the gate leakage current of the field effect transistor.
For example, when a current of 1 μA flows,
When the resistance value of the resistor inserted into the gate is 100 kΩ,
The voltage drop V _DROPIs V_DROP= 1 × 10^-6× 100 × 10^Three= 0.1 (V), and when the resistance value exceeds 100 kΩ, the control voltage
This exceeds 0.1V, and cannot be ignored in gain control characteristics.
This is because

In this amplifier, the gain is adjusted in the form of adjusting the amount of attenuation, and the illustration of the original amplifying function for increasing the gain is omitted. Only the circuit of FIG. 8 functions as an attenuator. This applies to the following embodiments.

FIG. 9 shows the threshold voltage V of each of the field effect transistors 21, 25, 16, and 28 in the amplifier of FIG.
When th is −0.7 V, Vref1 is set to 1.9 V, Vref2 is set to 1.6 V, and V
FIG. 9 is a characteristic diagram showing a state of gain control when both ref3 and Vref4 are set to 1.1V. FIG. 9A shows a gain control voltage Vc1−gain (attenuation) characteristic of a field effect transistor (Series FET) 25 included in the series variable resistor 52. FIG. 9B shows a field-effect transistor (S) constituting the series variable resistor 51.
4 shows a gain control voltage Vc1−gain (attenuation amount) characteristic of the MISFET 21). FIG. 9C shows the gain control voltage Vc1 of the field effect transistors (ShuntFETs) 16 and 28 constituting the parallel variable resistors 53 and 54.
-A gain (attenuation) characteristic is shown, a solid line is a characteristic for two, and a broken line is a characteristic for one. FIG. 9D shows FIG.
9 shows a gain control voltage Vc1-gain (attenuation) characteristic of the amplifier of FIG. 8 in which the characteristics of (a), (b), and (c) are combined.

As described above, each field effect transistor 2
The threshold voltage Vth of 1,25,16,28 is -0.7
In the case of V, the gain control voltage Vc1 of the field-effect transistor 25 of the series variable resistor 52 is 0.9 V to
Gain (attenuation) in a range of 15 dB with a gradient of 50 dB / V in proportion to a change in gain control voltage Vc1 in a range of 1.2 V
Is changed, and for the field effect transistor 21 of the series variable resistor 51, the gain control voltage Vc1 is 1.2 V to 1..
In the range of 5V, 50 in proportion to the change of the gain control voltage Vc1.
The gain (attenuation amount) changes within a range of 15 dB with a gradient of dB / V, and the gain control voltage Vc1 of the field effect transistors 16 and 28 of the parallel variable resistors 53 and 54 becomes 1.5
In the range of V to 1.8 V, the change in gain control voltage Vc1 is 46
The gain (attenuation) changes proportionally in the range of 14 dB with the slope of dB / V, and the gain control voltage section in which the gain control is not performed is substantially eliminated. In this case, the gain control width is 15 dB for the serial variable resistor 51 and 1 for the serial variable resistor 52.
Since 5 dB and 14 dB are provided by the parallel variable resistors 53 and 54, the total is 44 dB, so that a gain control characteristic of a wider variable width can be obtained as compared with the case of one series variable resistor, and the number of serial variable resistors can be reduced. By increasing the gain, it is possible to perform gain control in a range of 70 dB or more.

FIG. 10 is a characteristic diagram of the gain control with respect to the gain control voltage Vc1 of the amplifier according to the third embodiment in which the gain control is performed in the high frequency section of the mobile communication terminal transmitting section as shown in FIG.

The operation of the amplifier having the above configuration will be described. The portable terminal is driven at a voltage of up to about 3.0 V by a lithium battery or the like. The threshold voltage of the field-effect transistor indicates a bias at which the variable resistor starts the gain control operation. The threshold voltage of the field-effect transistor for the series variable resistors 51 and 52 and the parallel variable resistors 53 and 54 is determined. All threshold voltages are equal. In this example, the voltage is -0.7V.

Different reference voltages Vref are applied to the reference voltage application terminals 23 and 27 of the series variable resistors 51 and 52, respectively.
1, Vref2, and the parallel variable resistors 53, 5
4, the same reference voltage Vr is applied to the reference voltage application terminals 31 and 33.
ef3 and Vref4 are applied. Series variable resistor 5
The reference voltages Vref1 and Vref2 applied to the reference voltage application terminals 23 and 27 of the reference voltage Vref1 applied to the reference voltage application terminal 23 on the input side are higher than the reference voltage Vref1 applied to the reference voltage application terminal 27 on the output side. Compared to the voltage Vref2, a gain control voltage range (0.
2 to 0.3 V).

Each of the above-mentioned reference voltages Vref1, Vref
2, Vref3 and Vref4 are serial variable resistors 51,
What is necessary is just to set a state in which the linear gain control operation range by 52, 53, 54 can be regarded as substantially continuous. The same applies to the following embodiments.

Here, the variable resistor formed by the field effect transistor is completely turned off when the gate-source voltage VGS becomes lower than the threshold voltage Vth of the field effect transistor (VGS ≦ Vth). And the resistance value becomes maximum. The gate-source voltage VGS of each field-effect transistor is represented by the difference (VG-VS) between the gate voltage VG and the source voltage VS, and the gain control voltage Vc1 and the reference voltages Vref1, Vref2, and Vref.
3 and Vref4, the resistance value changes. Therefore, the reference voltages Vref1, Vref2, Vr
By changing the set values of ef3 and Vref4, it becomes possible to control the range of the gain control voltage Vc1 at which the gain of the variable resistor can be controlled.

Therefore, the reference voltages Vref1 and Vref2 of the series variable resistors 51 and 52 and the variable resistors 53 and 5 in parallel are connected.
4 by appropriately setting the reference voltages Vref3 and Vref4, the gain control between the gain control operation ranges of the series variable resistors 51 and 52 and the parallel variable resistors 53 and 54 is performed. Can be reduced to a small value of less than 0.15 V. With respect to the gain control voltage Vc1, the range of the gain control voltage Vc1 that the series variable resistors 51, 52 and the parallel variable resistors 53, 54 respectively share is the low voltage side of the series variable resistor 52 in FIG. The variable resistor 51 is on the intermediate voltage side, and the parallel variable resistors 53 and 54 are on the high voltage side.
The order may be reversed, and can be set arbitrarily.

Here, the gain control voltage section ΔV is 0.15
The reason why there is an inconvenience when V is V or more will be described.
Normally, step control of about 5 steps is often used, and control is performed 7 to 8 dB per step, and the gradient is about 50 d.
Since it is B / V, the control voltage is set in 0.15 V steps. Therefore, if the gain control voltage section ΔV in which the gain control cannot be performed is 0.15 V or more, there is a point where the gain does not change even if the control voltage is changed, so that the gain control cannot be performed with high accuracy.

The lower limit of the gain control voltage section ΔV in which the gain control cannot be performed is 0V. Note that there is basically no problem even if the control characteristics overlap. However, since the gradient of the overlapped portion becomes steeper, the setting of the control voltage needs to be changed when performing the above-described five-step control.

As described above, when the gain is continuously controlled, the reference voltage Vref1 of the serial variable resistor 51 is controlled.
And the reference voltage Vref2 of the series variable resistor 52 and the reference voltages Vref3 and Vref of the parallel variable resistors 53 and 54.
4 are appropriately set, the gain control operation ranges of the series variable resistors 51 and 52 and the parallel variable resistors 53 and 54 are connected so as to be smoothly continuous, and a single gain control voltage linearly extends over a wide range. It is possible to perform excellent gain control. Therefore, in the high-frequency section of the portable terminal, gain control of 70 dB or more can be performed with a flatness of ± 1 dB linearity by one semiconductor device. As a result, the gain control can be easily performed with high accuracy, and the circuit configuration can be simplified and space can be saved.

Here, assuming that the threshold voltages Vth of the field effect transistors are all -0.7 V, reference voltage Vref1 is set to 1.9 V, and reference voltage Vref is set to 1.9 V.
2 is set to 1.6 V and the reference voltages Vref3 and Vre
f4 are both set to 1.1V.

A voltage between 0 and 0.9 V is applied to the gain control voltage application terminal 19.
(FIG. 10: gain control voltage range (a)), the resistance value R _ON of the series variable resistors 51 and 52 is applied.
(T-FET 21) and R _ON (T-FET 25) are maximum values, and the resistance values R _ON (S-FE) of the parallel variable resistors 53 and 54 are
T16, 28) shows the minimum value, so that the signal input from the input terminal 34 is attenuated and the gain does not increase.
At 5, the magnitude P _OUT of the output signal is minimized.

When a voltage exceeding 0.9 V is applied to the gain control voltage application terminal 19 (FIG. 10: gain control voltage range (b)), the resistance values R _ON of the parallel variable resistors 53 and 54 are set.
(S-FETs 16 and 28) show the minimum value, and the resistance value R _ON of the input side series variable resistor 51 (T-FET 21) shows the maximum value while the resistance value R of the output side series variable resistor 52 remains the same. _{Since ON} (T-FET 25) starts to decrease, the magnitude P _OUT of the output signal increases. Normally, the gain control voltage range in which the variable resistor by the field effect transistor performs the linear gain control operation is about 0.2 to 0.3 V. Until a voltage of 1.2 V is applied to the gain control voltage application terminal 19,
The gain increases linearly by 15 dB.

When a voltage of 1.2 V is applied to the gain control voltage application terminal 19 (FIG. 10: gain control voltage range (c)), the reduced resistance value R _ON of the series variable resistor 52 on the output side is reduced. (T-FET 25) indicates the minimum value, and the resistance value R _{ON of} the input-side series variable resistor 51 indicating the maximum value.
Since (T-FET 21) starts to decrease, the magnitude P _OUT of the output signal increases with the same sensitivity. Here, the resistance value R _ON of the parallel variable resistors 53 and 54 (S-FET 16,
28) still show the minimum values, respectively.

When a voltage of 1.5 V is applied to the gain control voltage application terminal 19 (FIG. 10: gain control voltage range (d)), the resistance R _ON of the series variable resistor 51 on the input side, which has been reduced, is reduced. The (T-FET 21) shows the minimum value in the same manner as the resistance value R _ON (T-FET 25) of the output-side series variable resistor 52, and the parallel variable resistors 53 and 54 which showed the minimum value.
Since the resistance value R _ON (S-FETs 16 and 28) starts increasing, the magnitude P _OUT of the output signal linearly increases by 14 dB with a sensitivity different from the voltage range from 0.9 to 1.5 V.

When a voltage of 1.8 V is applied to the gain control voltage application terminal 19 (FIG. 10: gain control voltage range (e))
Has a resistance value R _ON (T−F) of the series variable resistors 51 and 52.
ET21), R _ON (T-FET 25) show the minimum value and the resistance value R _ON (S-F) of the parallel variable resistors 53, 54
ET16, 28) indicate the maximum value, so that the magnitude P _OUT of the output signal becomes maximum. At this time, the gain control width of this amplifier is 44 dB. Gain control voltage application terminal 1
Even if a voltage of 1.8 V or more is applied to 9, a serial variable resistor 5
The resistance values R _ON (T-FET 21) and R _ON (T−
FET 25) shows the minimum value, and the resistance value R _ON (S-FETs 16, 28) of the parallel variable resistors 53 and 54 shows the maximum value, so that the magnitude P _OUT of the output signal remains at the maximum.

As described above, according to this embodiment,
Series variable resistors 51 and 52 using field effect transistors
Are connected in multiple stages via the capacitor 24 and the operation of the series variable resistors 51 and 52 is shifted by the linear gain control operation range, whereby the linear operation ranges of the series variable resistors 51 and 52 can be added respectively. Therefore, the gain control amount with respect to the control voltage can be made linear over a wide range. The shift of the series variable resistors 51 and 52 by the linear gain control operation range can be performed by adjusting the reference voltage from an external microcomputer.

In the CDMA system, a code is attached to each signal and these signals are handled at the same time and on the same frequency.
The distortion characteristics of the device become extremely important. In particular, as in this embodiment, in the shift operation of the series variable resistors 51 and 52 by the field effect transistor by the linear gain control operation range, the output series variable resistor 52 is replaced by the input series variable resistor 51. By performing the preceding operation on the gain control voltage Vc1, the series variable resistor 5
Since the deterioration points of the distortion characteristics of the series variable resistor 52 and the parallel variable resistors 53 and 54 on the output side can be dispersed and the superimposition of the degraded distortion power can be eliminated, the parallel variable resistor 53 can be eliminated. , 54 can be used to prevent the deterioration of distortion characteristics. As shown in FIG. 11, as compared with the case where the series variable resistors 51 and 52 are simultaneously operated in the same configuration, the distortion characteristic is the adjacent channel leakage power (ACP 900 kHz) in the case of 900 kHz detuning.
In z), a low distortion operation of about 4 dBc is possible.

In the above embodiment, in the shifting operation of the series variable resistors 51 and 52 by the field effect transistor, the output side series variable resistor 52 is changed from the input side series variable resistor 51 to the gain control voltage Vc1. Although the preceding operation is performed on the contrary, the same characteristic can be obtained by operating the input-side series variable resistor 51 on the contrary. This increases the degree of freedom in setting the control voltage by the microcomputer logic.

In the above embodiment, the reference voltage application terminal 23 of the input-side series variable resistor 51, the reference voltage application terminal 27 of the output-side series variable resistor 52, and the reference voltage of the parallel variable resistors 53 and 54 are used. Although the application terminals 31 and 33 are provided, respectively, as shown in FIG.
Reference voltage application may be performed according to steps 9 and 40. In this case, since only one reference voltage application terminal is used, the circuit can be simplified. The bias resistors 38, 39, and 40 play a role of blocking the intrusion of high-frequency signals. The bias resistors 38, 39, and 40 are set to have a resistance value of about 5 kΩ or more and 100 kΩ or less in order to prevent intrusion of high frequency signals.

The reason why the bias resistors 38, 39, and 40 are set to a resistance value of about 5 kΩ or more and 100 kΩ or less will be described below.

First, the fact that the lower limit is about 5 kΩ is as follows. The bias resistor 38 and the field effect transistor 25 are connected in parallel, and the gain is controlled by the variable resistance value of the field effect transistor 25. now,
When the bias resistor 38 is smaller than 5 kΩ, the resistance between both terminals of the parallel circuit of the bias resistor 38 and the field effect transistor 25 is about 5 kΩ and does not become larger even if the resistance value of the field effect transistor 25 is increased. However, the gain control width becomes small, and the gain cannot be controlled with high accuracy. That is, the intrusion of the high-frequency signal cannot be prevented. Also, if the bias resistors 39 and 40 have a small value, a high-frequency signal passes to the ground, so that 5 kΩ or more (isolation 40 dB or more) is required. Also, the reference voltage Vr
When ef1 is 3V, each of the bias resistors 38, 39, 40
Is more than I = 3V / 15 kΩ = 200 μA, and the power consumption is increased.

On the other hand, the fact that the upper limit is 100 kΩ is as follows. Reference voltage Vref1 is 3V
In this case, the current flowing through each of the bias resistors 38, 39 and 40 is I = 3V / 300 kΩ = 10 μA. Now, the voltage across the bias resistor 38 is V = 10 μA × 100 kΩ = 1 V. At this time, if the leak current of the field effect transistor flows into 1 μA, 1 μA × 100 kΩ =
A bias fluctuation of 0.1 V occurs, and the gain control characteristic deviates, so that gain control cannot be performed accurately.

Further, in the third embodiment, reference voltage application terminals 23 and 27 are provided respectively so that different voltages can be applied to the respective source electrodes of the field effect transistors for the series variable resistors 51 and 52. Instead, as shown in FIGS. 13 and 14, the series variable resistors 51,
The gain control voltages Vc1 and Vc differing by the linear gain control operation range are applied to each gate of the field effect transistor for 52.
2 so that the gain control voltage application units 4 can be applied.
2 and 19 may be provided (fourth embodiment). In addition,
In FIG. 13, 58 is a first gain control line, and 59 is a second gain control line.

In this case, the gain control voltages Vc1 and Vc2 may be applied to the gain control voltage application unit 42 with a voltage difference higher than the gain control voltage application unit 19 by the linear gain control operation range. Eliminates the need for complicated voltage setting as in the case of using a plurality of control devices. A field effect transistor 2 for the series variable resistors 51 and 52
Since the same reference voltage Vref1 is applied to each of the source electrodes 1 and 25, linear gain control can be performed with high accuracy even when the reference voltage Vref1 fluctuates. The resistance 41 connected between the source electrodes of the field effect transistors 21 and 25 for the variable resistances 51 and 52 in series with the reference voltage application terminal 23 serves as a high-frequency signal block, and is about 5 kΩ or more and 100 kΩ or less. Resistance value.

The reason that the resistance 41 is set to a resistance value of about 5 kΩ or more and 100 kΩ or less will be described below.

First, the fact that the lower limit is about 5 kΩ is as follows. The resistor 41 and the field effect transistor 25 are connected in parallel, and the gain is controlled by the variable resistance value of the field effect transistor 25. Now, resistance 41
Is smaller than 5 kΩ, the resistance between the two terminals of the parallel circuit of the resistor 41 and the field effect transistor 25 is about 5 kΩ even if the resistance value of the field effect transistor 25 is increased. And the gain cannot be controlled with high accuracy. That is, the intrusion of the high-frequency signal cannot be prevented.

On the other hand, the fact that the upper limit value is 100 kΩ is as follows. When the leak current of the field effect transistor flows in (about 1 μA), the potential difference between both ends of the resistor 41 exceeds V = 1 μA × 100 kΩ = 0.1 V, a bias change occurs, and gain control cannot be performed accurately.

Similarly, as shown in FIG. 15, field effect transistors 21, 25 for series variable resistors 51, 52 are provided.
Bias resistors 36 and 37 may be provided so that different voltages can be applied to the respective gates by the amount of the linear gain control operation range. In this case, since only one gain control voltage Vc1 is used, the setting of the microcomputer logic is simplified, and the same reference voltage is applied to each source electrode of the field effect transistors 21 and 25 for the series variable resistors 51 and 52. Since the voltage is applied, linear gain control can be performed with high accuracy even when the reference voltage fluctuates. Further, the reference voltage may be applied by the bias resistors 41, 39, and 40. In this case, since only one reference voltage application terminal is used, the circuit can be simplified. The bias resistors 41, 39, and 40 play a role of blocking the intrusion of high-frequency signals. The above bias resistor 4
1, 39, and 40 are 5 to prevent intrusion of high-frequency signals.
The resistance value is set to about kΩ or more and 100 kΩ or less.
The reason for setting the resistance value range is the same as that described with reference to FIG.

Similarly, in the third embodiment,
Reference voltage application terminals 23 and 27 are provided respectively so that different voltages can be applied to the respective source electrodes of the field effect transistors 21 and 25 for the series variable resistors 51 and 52, as shown in FIG. 16 or FIG. As described above, each of the field effect transistors 21 and 22 for the series variable resistors 51 and 52
5, the same reference voltage and the same gain control voltage are applied, and the field effect transistors 21 and 25 are shifted using threshold voltage different field effect transistors corresponding to a gain control voltage range for performing a linear gain control operation. The operation may be performed (fifth embodiment). In this case, although the number of process steps is increased, the circuit configuration is as shown in FIGS. 16 and 17, and the number of voltage application terminals can be reduced and simplification can be achieved. In addition, since the same reference voltage is applied to each source electrode of the field effect transistors 21 and 25 for the series variable resistors 51 and 52, linear gain control is possible with high accuracy even when the reference voltage fluctuates. It is. The resistance 41 connected between the source electrodes of the field effect transistors 21 and 25 for the variable resistances 51 and 52 in series with the reference voltage application terminal 23 serves to prevent the intrusion of high frequency signals.

Further, as shown in FIG. 18, the reference voltage may be applied by the bias resistors 41, 39 and 40 at the reference voltage. In this case, since only one reference voltage application terminal is used, the circuit can be further simplified.
The bias resistors 41, 39, and 40 respectively play a role of preventing a reference voltage bias resistor and a high-frequency signal from entering.

In the above-described embodiment, a configuration is used in which two variable resistors, that is, an input-side series variable resistor 51 and an output-side series variable resistor 52 of a field-effect transistor are connected in multiple stages. May be connected in multiple stages.The more the number of variable resistors connected in series and multiple stages is increased, the more the linear operation range of the series variable resistors can be added. It is possible to expand the signal control range.

In the above embodiment, each variable resistor 5
Nothing is connected in parallel between the drain and source electrodes of the field effect transistors 21, 25, 16, and 28 for the field effect transistors 21, 25, 53, and 54. , 28, and to control the variable resistance range,
A resistor or the like may be connected in parallel between the drain and source electrodes of the field effect transistors 21, 25, 16, and 28. As a result, the gain control amount of each variable resistor is stabilized, and extremely high-precision gain control becomes possible.

In the above embodiment, each variable resistor 5
Although the number of gates of each of the field effect transistors 21, 25, 16, and 28 for 1, 52, 53, and 54 is configured by one, a plurality of more gates (multi-gate type) are used. The higher the number of gates used, the higher the gain, and even with a high input signal, it becomes possible to perform gain control while suppressing deterioration of distortion characteristics.

Further, the field effect transistors 21, 25, 16, and 28 constituting the variable resistors 51, 52, 53 and 54 are provided.
Are all single-gate types, it is not necessary to set the gate widths of the field effect transistors 21, 25, 16, and 28 to be the same.
It is possible to match the combined gain control characteristic of the plurality of parallel variable resistors 53 and 54 with the respective gain control characteristics of the series variable resistors 51 and 52, and to make the linearity of the gain control extremely good. be able to.

Further, in the above embodiment, the case where the respective field effect transistors 21, 25, 16, and 28 are used for the respective variable resistors 51, 52, 53, 54 has been described, but the present invention is not limited to this. Instead, an element such as a diode may be used.

Further, according to the circuit configuration such as the amplifier according to each of the third and subsequent embodiments having two or more series variable resistors, not only continuous control of gain but also step control of gain can be performed. This is also possible, and in this case, as in the first or second embodiment, it can be combined with continuous control of the intermediate frequency section. By doing so, the gain control range of the step control is expanded as compared with the first or second embodiment, so that the gain control range as a whole can be further expanded.

These amplifiers can be used not only in the CDMA system but also in various mobile communication systems (PDG, GSM, PDM).
CS, Wideband-CDMA, DCS, PHS, etc.).

[0133]

According to the amplifier of the present invention, an appropriate reference voltage is applied to each of a serial variable resistor and a parallel variable resistor in a high-frequency section of a mobile communication terminal transmitting section, etc. Since the gain control voltage section in which the gain control cannot be performed in the gain control voltage range for performing the linear gain control operation can be reduced or eliminated, the gain control can be performed with high precision when performing the gain step control. It is possible to do.

Further, according to another amplifier of the present invention, in a high-frequency section of a mobile communication terminal transmitting section or the like, a series variable resistor composed of at least two or more field effect transistors is connected in multiple stages and connected in multiple stages. The operation of the series variable resistor is shifted by the linear gain control operation range, and the linear operation range of the series variable resistor with respect to the gain control voltage is added, and each mode is switched by only one gain control voltage. And it is possible to realize an excellent amplifier that can perform a linear (flatness ± 1 dB) gain control operation with respect to the control voltage with extremely high accuracy over a wide range. Then, by increasing the number of connection stages of the series variable resistors, a linear (flatness ± 1 dB) gain control operation with respect to the control voltage is performed.
It is also possible to perform the processing with extremely high precision over a wide range of dB or more.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an amplifier according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of the amplifier according to the first embodiment of the present invention.

FIG. 3 sets Vref11 to 1.8V and Vr11 when the threshold voltage Vth of each of the field-effect transistors 6, 1, and 9 is -0.7V in the amplifier of FIG.
FIG. 11 is a characteristic diagram showing a state of gain control when both ef12 and Vref13 are set to 1.0V.

FIG. 4 is a characteristic diagram of gain control with respect to a gain control voltage in the amplifier of FIG. 2;

FIG. 5 is a block diagram showing a specific configuration of an amplifier according to a second embodiment of the present invention.

FIG. 6 sets Vref11 to 1.8V and Vr11 when the threshold voltage Vth of each of the field-effect transistors 6, 1, and 9 is -0.7V in the amplifier of FIG.
FIG. 11 is a characteristic diagram showing a state of gain control when both ef12 and Vref13 are set to 1.0V.

FIG. 7 is a block diagram illustrating a configuration of an amplifier according to a third embodiment of the present invention.

FIG. 8 shows a third embodiment of the present invention, in which reference voltage application terminals 23 and 27 are respectively applied so that different voltages can be applied to respective source electrodes of field effect transistors 21 and 25 for a series variable resistor. FIG. 3 is a circuit diagram showing a specific configuration of an amplifier provided with.

9 is a circuit diagram of the amplifier of FIG. 8 in which the threshold voltage Vth of each of the field-effect transistors 21, 25, 16, and 28 is-
In the case of 0.7V, Vref1 is set to 1.9V, Vref2 is set to 1.6V, and Vref3 is set.
FIG. 11 is a characteristic diagram showing a state of gain control when both Vref4 are set to 1.1V.

FIG. 10 is a characteristic diagram of gain control with respect to a gain control voltage according to the third embodiment of the present invention.

FIG. 11 is a characteristic diagram of adjacent channel leakage power at 900 kHz detuning with respect to a gain control voltage according to the third embodiment of the present invention.

FIG. 12 is a circuit diagram showing a specific configuration of an amplifier in which bias resistors 38, 39, and 40 are provided so that a reference voltage can be applied to each variable resistor in the third embodiment of the present invention. is there.

FIG. 13 is a block diagram illustrating a configuration of an amplifier according to a fourth embodiment of the present invention.

FIG. 14 shows gain control voltage application terminals 42 and 19 provided in the fourth embodiment of the present invention so that different voltages can be applied to the respective gates of the field effect transistors 21 and 25 for a series variable resistor. FIG. 3 is a circuit diagram showing a specific configuration of the amplifier.

FIG. 15 shows a fourth embodiment of the present invention, in which bias resistors 36 and 37 are provided so that different voltages can be applied to the respective gates of the field effect transistors 21 and 25 for a series variable resistor; Bias resistors 41, 39, and 4 are respectively provided so that a reference voltage can be applied to the variable resistors.
FIG. 4 is a circuit diagram showing a specific configuration of an amplifier provided with 0.

FIG. 16 is a block diagram illustrating a configuration of an amplifier according to a fifth embodiment of the present invention.

FIG. 17 shows a fifth embodiment of the present invention.
FIG. 11 is a circuit diagram showing a specific configuration of an amplifier using field-effect transistors 21 and 25 having different threshold voltages in series variable resistors so as to perform a shift operation by applying the same reference voltage and the same gain control voltage. is there.

FIG. 18 is a circuit diagram showing a specific configuration of an amplifier in which bias resistors 41, 39, and 40 are respectively provided so that a reference voltage can be applied to each variable resistor in the fifth embodiment of the present invention. is there.

FIG. 19 is a circuit diagram showing a configuration of a conventional amplifier.

FIG. 20 is a characteristic diagram showing how the gain control is performed when the threshold voltage Vth of each of the field effect transistors 6, 1, and 9 is -1.0 V in the amplifier of FIG.

FIG. 21 is a characteristic diagram showing a state of gain control when the threshold voltage Vth of each of the field effect transistors 6, 1, and 9 is −2.0 V in the amplifier of FIG.

FIG. 22 is a characteristic diagram of step control with respect to a gain control voltage in a conventional amplifier used in a high-frequency unit.

FIG. 23 is a characteristic diagram of continuous control for a gain control voltage in a conventional amplifier used for an intermediate frequency section.

FIG. 24 is a characteristic diagram of gain control when two types of amplifiers are combined in a conventional mobile communication terminal transmission unit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 field effect transistor 2 capacitor 3 capacitor 4 gain control voltage applying terminal 5 resistor 6 field effect transistor 7 resistor 8 reference voltage applying terminal 9 field effect transistor 10 capacitor 11 capacitor 12A reference voltage applying terminal 12B reference voltage applying terminal 13 resistor 14 input terminal Reference Signs List 15 output terminal 16 variable resistor 17 capacitor 18 capacitor 19 gain control voltage input terminal 20 resistor 21 variable resistor 22 resistor 23 reference voltage application terminal 24 capacitor 25 variable resistor 26 resistor 27 reference voltage application terminal 28 variable resistor 29 capacitor 30 capacitor 31 reference voltage Application terminal 32 Resistance 33 Reference voltage application terminal 34 Input terminal 35 Output terminal 36 Resistance 37 Resistance 38 Resistance 39 Resistance 40 Resistance 41 Resistance 51 Variable resistance 52 Variable resistance 53 Variable resistance 54 a variable resistor 71 a variable resistor 72 a variable resistor 73 a variable resistor

Claims (59)

[Claims] 1. A signal input section (14) and a signal output section (1).
5) and a signal line (74) composed of a series variable resistor (71) connected to each of the signal input section (14) and the signal output section (15) and a ground line (76). Parallel variable resistors (72) and (73), a gain control line (75) connected to the variable resistors (71), (72) and (73), and the variable resistors (71) and (73).
Reference voltage application units (8), (12A), (12B) connected to each of (72) and (73), and the variable resistor (7
1), (72), and (73), a gain control voltage application unit (4) connected via the gain control line (75).
And an amplifier comprising: 2. The variable resistors (71), (72), (7)
3) is at least a field effect transistor (6),
Resistors (7), (5), (1) are connected to the gates of (1) and (9).
3), wherein the gate of the field effect transistor (6) of the variable resistor (71) is connected to the resistor (7).
2. The amplifier according to claim 1, wherein the amplifier is connected to the gain control voltage applying unit via the gain control line. 3. The variable resistors (71), (72), (7)
3) The field effect transistors (6), (1),
3. The amplifier according to claim 2, wherein (9) is a single-gate type. 4. The variable resistors (71), (72), (7)
3) The field effect transistors (6), (1),
4. The amplifier according to claim 3, wherein the gate width of (9) is set equal. 5. The amplifier according to claim 2, wherein said field effect transistor (6A) of said variable resistor (71) is of a multi-gate type. 6. A gain control voltage range in which said variable resistor (71) performs a linear gain control operation and said variable resistor (72),
2. The amplifier according to claim 1, wherein the gain control voltage section in which the gain control cannot be performed between the gain control voltage range and the gain control voltage range in which the linear gain control operation is performed is less than 0.15V. 7. The reference voltage applying unit (12A), (12
The voltage value applied to B) is within a gain control voltage range in which the variable resistor (71) performs a linear gain control operation, and a gain control voltage range in which the variable resistors (72) and (73) perform a linear gain control operation. 2. The amplifier according to claim 1, wherein the amplifier is set to be continuous. 8. A common reference voltage is applied to the gates of the field effect transistors (1) and (9) of the variable resistors (72) and (73) via the resistors (5) and (13). An amplifier according to claim 2, wherein 9. A signal input section (34) and a signal output section (3).
5), a signal line (55) composed of at least two or more serial variable resistors (51) and (52), the signal input section (34) and the signal output section (35), and a ground line ( 57) and the parallel variable resistors (53) and (54) connected to each other between the variable resistors (51) and (51).
(52), (53), a gain control line (56) connected to (54), and the variable resistors (51), (52),
Reference voltage applying sections (23), (27), (31), (33) connected to each of (53), (54), and the variable resistors (51), (52), (53), (53). 54) A gain control voltage applying section (19) connected to each of the above (54) via the gain control line (56). 10. The variable resistors (51), (52),
In (53) and (54), resistors (22), (26), (20) and (32) are connected to at least the gates of the field effect transistors (21), (25), (16) and (28). In the configuration, the gates of the field effect transistors (21) and (25) of each of the variable resistors (51) and (52) are connected to the resistors (22) and (26) and the gain control line (5).
10. The amplifier according to claim 9, wherein said amplifier is connected to said gain control voltage applying section via said control circuit. 11. A gate of each of the field-effect transistors (16) and (28) of each of the variable resistors (53) and (54) is connected to the reference voltage applying unit via the resistor (20) or (32). An amplifier according to claim 10, connected to (31), (33). 12. The reference voltage applying sections (23) and (27) are connected to the sources of the field effect transistors (21) and (25) of the variable resistors (51) and (52), respectively. The amplifier according to claim 11, wherein the variable resistors (51) and (52) are connected in series via a capacitor (24). 13. The source of the field effect transistors (16) and (28) of each of the variable resistors (53) and (54) is connected to the gain control voltage applying section (19) via the gain control line (56). 13. The amplifier of claim 12, wherein the amplifier is connected to: 14. The drains of the field effect transistors (16) and (28) of the variable resistors (53) and (54) are connected to the signal line (55) via capacitors (17) and (29). 14. The amplifier of claim 13 connected. 15. A source of each of said field effect transistors (16), (28) of said variable resistors (53), (54) is connected to a capacitor (18), (30) and said ground line (5).
14. The amplifier according to claim 13, which is connected to the basic potential section (GND) via 7). 16. The amplifier according to claim 9, wherein a voltage applied to said reference voltage applying unit (23) is higher than a voltage applied to said reference voltage applying unit (27). 17. The gain at which the variable resistor (52) performs a linear gain control operation with a voltage applied to the reference voltage application unit (23), compared to a voltage applied to the reference voltage application unit (27). 10. The method according to claim 9, wherein the value is higher by a value corresponding to the control voltage range.
An amplifier as described. 18. The reference voltage application section (31), (3)
3) the voltage value applied to the variable resistor (51),
10. The gain control voltage range in which the variable resistors (53) and (54) perform the linear gain control operation is set to be continuous with the gain control voltage range in which (52) performs the linear gain control operation. amplifier. 19. A common reference voltage is applied to the gates of the field effect transistors (16) and (28) of the variable resistors (53) and (54) via the resistors (20) and (32). An amplifier according to claim 10, wherein 20. A resistor (38) is inserted and connected between the sources of the field effect transistors (21) and (25) of each of the variable resistors (51) and (52). The source of the field effect transistor (25) is connected to the gates of the field effect transistors (16) and (28) of the variable resistors (53) and (54) via the resistors (20) and (32). A resistor (39) is inserted and connected between the variable resistor (5) and the variable resistor (5).
3) and (54).
6) and (28) are connected to the resistors (20) and (32)
(61) and a basic potential portion (G
The amplifier according to claim 10, wherein a resistor (40) is inserted and connected between the variable resistor (ND) and the source of the field effect transistor (21) of the variable resistor (51). . 21. The variable resistor (52) inserted between the sources of the field effect transistors (21) and (25) of the variable resistors (51) and (52). The source of the field effect transistor (25) is connected to the gates of the field effect transistors (16) and (28) of the variable resistors (53) and (54) via the resistors (20) and (32). Said part (6
1), the resistance (20), the resistance (20), and the gate of each of the field effect transistors (16), (28) of the variable resistances (53), (54). The part (6) connected via (32)
The resistor (40) inserted and connected between (1) and the basic potential section (GND) has a resistance value capable of preventing intrusion of a high-frequency signal from each connected section. Item 21. The amplifier according to item 20, wherein 22. The variable resistor (52) inserted between the sources of the field effect transistors (21) and (25) of the variable resistors (51) and (52). The source of the field effect transistor (25) is connected to the gates of the field effect transistors (16) and (28) of the variable resistors (53) and (54) via the resistors (20) and (32). Said part (6
1), the resistance (20), the resistance (20), and the gate of each of the field effect transistors (16), (28) of the variable resistances (53), (54). The part (6) connected via (32)
21. The amplifier according to claim 20, wherein the resistor (40) inserted and connected between (1) and the basic potential section (GND) has a resistance value of about 5 kΩ or more. 23. The variable resistors (51), (52),
(53) and (54) the field effect transistor (2)
11. The amplifier according to claim 10, wherein (1), (25), (16), and (28) are all of a single gate type and have equal gate widths. 24. The amplifier according to claim 10, wherein said field effect transistors (21) and (25) of said variable resistors (51) and (52) are of a multi-gate type. 25. A signal input section (34) and a signal output section (3).
5), a signal line (55) composed of at least two or more serial variable resistors (51) and (52), the signal input section (34) and the signal output section (35), and a ground line ( 57) connected in parallel with each other, a first gain control line (58) connected to the variable resistor (51), and the variable resistor (51). And a second gain control line (42) connected to the variable resistors (52), (53), and (54) via the first gain control line (58). 59) and the variable resistors (52), (5)
3) and (54), a gain control voltage application section (19) connected via the second gain control line (59), and a reference voltage application section connected to the variable resistors (51) and (52). An amplifier comprising (23) and reference voltage applying sections (31), (33) connected to the variable resistors (53), (54), respectively. 26. The variable resistor (51), (52),
In (53) and (54), resistors (22), (26), (20) and (32) are connected to at least the gates of the field effect transistors (21), (25), (16) and (28). In the configuration, the gate of the field effect transistor (21) of the variable resistor (51) is connected to the resistor (22) and the first resistor.
It is connected to the gain control voltage application section (42) via a gain control line (58), and the gate of the field effect transistor (25) of the variable resistor (52) is connected to the resistor (2).
26. The amplifier according to claim 25, wherein the amplifier is connected to the gain control voltage applying section (6) via the second gain control line (6) and the second gain control line (59). 27. The gates of the field effect transistors (16) and (28) of the variable resistors (53) and (54) are respectively connected to the reference voltage applying unit via the resistors (20) and (32). 27. The amplifier according to claim 26, connected to (31), (33). 28. A resistor (41) is inserted and connected between the sources of the field effect transistors (21) and (25) of each of the variable resistors (51) and (52), and a source of the variable resistor (52). Is connected to the reference voltage applying unit (23), and a capacitor (2) is connected between the variable resistors (51) and (52).
28. The amplifier according to claim 27, connected in series via 4). 29. The source of the field effect transistors (16) and (28) of each of the variable resistors (53) and (54) is connected to the gain control voltage applying unit via the second gain control line (59). 29. The amplifier according to claim 28, connected to (19). 30. The drains of the field effect transistors (16) and (28) of the variable resistors (53) and (54) are connected to the signal line (55) via capacitors (17) and (29). 30. The amplifier of claim 29 connected. 31. The sources of the field effect transistors (16) and (28) of the variable resistors (53) and (54) are connected to capacitors (18) and (30) and the ground line (5).
30. The amplifier according to claim 29, which is connected to the basic potential section (GND) via 7). 32. The amplifier according to claim 25, wherein a voltage applied to said gain control voltage applying unit (19) is higher than a voltage applied to said gain control voltage applying unit (42). 33. The variable resistor (52) performs a linear gain control operation with a voltage applied to the gain control voltage application unit (19) more than a voltage applied to the gain control voltage application unit (42). 26. The amplifier of claim 25, which is higher by a value corresponding to a gain control voltage range to be performed. 34. The reference voltage applying section (31), (3)
3) the voltage value applied to the variable resistor (51),
26. The gain control voltage range in which the variable resistors (53) and (54) perform the linear gain control operation is set to be continuous with the gain control voltage range in which (52) performs the linear gain control operation. amplifier. 35. A common reference voltage is applied to the gates of the field effect transistors (16) and (28) of the variable resistors (53) and (54) via the resistors (20) and (32). 27. The amplifier of claim 26, wherein 36. A resistor (41) is inserted and connected between the sources of the field effect transistors (21) and (25) of the variable resistors (51) and (52), respectively. The source of the field effect transistor (25) is connected to the gates of the field effect transistors (16) and (28) of the variable resistors (53) and (54) via the resistors (20) and (32). A resistor (39) is inserted and connected between the variable resistor (5) and the variable resistor (5).
3) and (54).
6) and (28) are connected to the resistors (20) and (32)
(61) and a basic potential portion (G
27. An amplifier according to claim 26, wherein a resistor (40) is inserted and connected between the variable resistor (ND) and the source of the field effect transistor (25) of the variable resistor (52). . 37. The variable resistor (52) which is inserted and connected between the sources of the field effect transistors (21) and (25) of the variable resistors (51) and (52), respectively. The source of the field effect transistor (25) is connected to the gates of the field effect transistors (16) and (28) of the variable resistors (53) and (54) via the resistors (20) and (32). Said part (6
1), the resistance (20), the resistance (20), and the gate of each of the field effect transistors (16), (28) of the variable resistances (53), (54). The part (6) connected via (32)
The resistor (40) inserted and connected between (1) and the basic potential section (GND) has a resistance value capable of preventing intrusion of a high-frequency signal from each connected section. Item 37. The amplifier according to Item 36. 38. The variable resistor (52) which is inserted and connected between the sources of the field effect transistors (21) and (25) of the variable resistors (51) and (52), respectively. The source of the field effect transistor (25) is connected to the gates of the field effect transistors (16) and (28) of the variable resistors (53) and (54) via the resistors (20) and (32). Said part (6
1), the resistance (20), the resistance (20), and the gate of each of the field effect transistors (16), (28) of the variable resistances (53), (54). The part (6) connected via (32)
37. The amplifier according to claim 36, wherein the resistor (40) inserted and connected between (1) and the basic potential section (GND) has a resistance value of about 5 kΩ or more. 39. The variable resistors (51), (52),
In (53) and (54), resistors (22), (26), (20) and (32) are connected to at least the gates of the field effect transistors (21), (25), (16) and (28). The resistor (26) connected to the gate of the field effect transistor (25) of the variable resistor (52).
And the second gain control line (59) connected to the sources of the field effect transistors (16) and (28) of each of the variable resistors (53) and (54); A resistor (36) is inserted and connected between the gate of the field effect transistor (21) and the first gain control line (58) connected through the resistor (22), and the variable resistor (51) The first gain control line (58) connected to the gate of the field effect transistor (21) via the resistor (22) and a basic potential section (GN)
D), a resistor (37) is inserted and connected, and the gain control voltage applying unit (1) is connected to the second gain control line (59).
26. The amplifier according to claim 25, wherein 9) is connected. 40. The field effect transistor (16) of each of the variable resistor (53) and the variable resistor (53) connected to the gate of the field effect transistor (25) of the variable resistor (52). ), (28), the second gain control line (59) connected to the field effect transistor (2) of the variable resistor (51).
The resistor (36) inserted between the gate of (1) and the first gain control line (58) connected via the resistor (22), and the field effect transistor of the variable resistor (51). The resistor (37) inserted and connected between the first gain control line (58) connected to the gate of (21) via the resistor (22) and the basic potential section (GND) is connected to 40. A resistor having a resistance value capable of preventing intrusion of a high-frequency signal from each component.
An amplifier as described. 41. The field effect transistor (16) of each of the variable resistor (53) and the variable resistor (53) connected to the gate of the field effect transistor (25) of the variable resistor (52). ), (28), the second gain control line (59) connected to the field effect transistor (2) of the variable resistor (51).
The resistor (36) inserted between the gate of (1) and the first gain control line (58) connected via the resistor (22), and the field effect transistor of the variable resistor (51). The resistor (37) inserted and connected between the first gain control line (58) connected to the gate of (21) via the resistor (22) and the basic potential section (GND) has a resistance of 5 kΩ. 40. The amplifier according to claim 39, wherein the amplifier has a resistance value on the order of or greater. 42. The variable resistors (51), (52),
(53) and (54) the field effect transistor (2)
27. The amplifier according to claim 26, wherein all of 1), (25), (16), and (28) are of a single gate type and have equal gate widths. 43. The amplifier according to claim 26, wherein said field effect transistors (21) and (25) of said variable resistors (51) and (52) are of a multi-gate type. 44. A signal input section (34) and a signal output section (3).
5), a signal line (55) composed of at least two or more serial variable resistors (51) and (52), the signal input section (34) and the signal output section (35), and a ground line ( 57) and the parallel variable resistors (53) and (54) connected to each other between the variable resistors (51) and (51).
(52), a gain control line (56) connecting the (53) and (54), and the variable resistors (51), (52) and (5).
3) and (54) via a gain control line (56) via a gain control voltage application section (19); and a reference voltage application section (2) connected to the variable resistors (51) and (52).
3) and an amplifier including reference voltage applying sections (31) and (33) connected to the variable resistors (53) and (54), respectively. 45. The variable resistors (51), (52),
In (53) and (54), resistors (22), (26), (20) and (32) are connected to at least the gates of the field effect transistors (21), (25), (16) and (28). In the configuration, the gates of the field effect transistors (21) and (25) of each of the variable resistors (51) and (52) are connected to the resistors (22) and (26) and the gain control line (5).
45. The amplifier according to claim 44, wherein said amplifier is connected to said gain control voltage application section via (6). 46. The gates of the field effect transistors (16) and (28) of the variable resistors (53) and (54) are respectively connected to the reference voltage applying section via the resistors (20) and (32). The amplifier according to claim 45, connected to (31), (33). 47. A resistor (41) is inserted and connected between the sources of the field effect transistors (21) and (25) of each of the variable resistors (51) and (52), and the source of the variable resistor (52) is connected. Is connected to the reference voltage applying unit (23), and a capacitor (2) is connected between the variable resistors (51) and (52).
47. The amplifier of claim 46, connected in series via 4). 48. The sources of the field effect transistors (16) and (28) of the variable resistors (53) and (54) are connected to the gain control voltage applying section (19) via the gain control line (56). 48. The amplifier of claim 47 connected to 49. The drains of the field effect transistors (16) and (28) of the variable resistors (53) and (54) are connected to the signal line (55) via capacitors (17) and (29). 49. The amplifier of claim 48 connected. 50. The sources of the field effect transistors (16) and (28) of the variable resistors (53) and (54) are connected to capacitors (18) and (30) and the ground line (5).
49. The amplifier according to claim 48, wherein the amplifier is connected to the basic potential section (GND) via 7). 51. The threshold voltage of the field effect transistor (21) of the variable resistor (51) is higher than the threshold voltage of the field effect transistor (25) of the variable resistor (52). 44. The amplifier according to 44. 52. The threshold voltage of the field effect transistor (21) of the variable resistor (51) is greater than the threshold voltage of the field effect transistor (25) of the variable resistor (52). 5. The method according to claim 4, wherein (52) is higher by a value corresponding to a gain control voltage range in which a linear gain control operation is performed.
5. The amplifier according to 4. 53. The reference voltage applying sections (31), (3)
3) the voltage value applied to the variable resistor (51),
45. The gain control voltage range in which the variable resistors (53) and (54) perform the linear gain control operation is set to be continuous with the gain control voltage range in which (52) performs the linear gain control operation. amplifier. 54. A common reference via said resistors (20) and (32) connected to the gates of said field effect transistors (16) and (28) of each of said variable resistors (53) and (54). 46. The amplifier of claim 45, wherein a voltage is applied. 55. A resistor (41) is inserted and connected between the sources of the field effect transistors (21) and (25) of the variable resistors (51) and (52), respectively. The source of the field effect transistor (25) is connected to the gates of the field effect transistors (16) and (28) of the variable resistors (53) and (54) via the resistors (20) and (32). A resistor (39) is inserted and connected between the variable resistor (5) and the variable resistor (5).
3) and (54).
6) and (28) are connected to the resistors (20) and (32)
(61) and a basic potential portion (G
The amplifier according to claim 45, wherein a resistor (40) is inserted and connected between the variable resistor (ND) and the source of the field effect transistor (25) of the variable resistor (52). . 56. The variable resistor (52) which is inserted and connected between the sources of the field effect transistors (21) and (25) of the variable resistors (51) and (52). The source of the field effect transistor (25) is connected to the gates of the field effect transistors (16) and (28) of the variable resistors (53) and (54) via the resistors (20) and (32). Said part (6
1), the resistance (20), the resistance (20), and the gate of each of the field effect transistors (16), (28) of the variable resistances (53), (54). The part (6) connected via (32)
The resistor (40) inserted and connected between (1) and the basic potential section (GND) has a resistance value capable of preventing intrusion of a high-frequency signal from each connected section. Item 55. The amplifier according to Item 55. 57. The variable resistor (52) inserted between the sources of the field effect transistors (21) and (25) of the variable resistors (51) and (52). The source of the field effect transistor (25) is connected to the gates of the field effect transistors (16) and (28) of the variable resistors (53) and (54) via the resistors (20) and (32). Said part (6
1), the resistance (20), the resistance (20), and the gate of each of the field effect transistors (16), (28) of the variable resistances (53), (54). The part (6) connected via (32)
The amplifier according to claim 55, wherein the resistor (40) inserted and connected between 1) and the basic potential section (GND) has a resistance value of about 5 kΩ or more. 58. The variable resistors (51), (52),
(53) and (54) the field effect transistor (2)
46. The amplifier according to claim 45, wherein 1), (25), (16), and (28) are all of a single-gate type and have equal gate widths. 59. The amplifier according to claim 45, wherein said field effect transistors (21) and (25) of said variable resistors (51) and (52) are of a multi-gate type.