JP2000077531A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Problem] To provide a phase pattern in which there is no inconsistency in the Levenson arrangement of a phase shifter even in a portion where an island-shaped wiring electrode pattern and a linear wiring electrode pattern are mixed in a mask for forming the same wiring electrode layer. Provided is a semiconductor integrated circuit device capable of being arranged. SOLUTION: A plurality of common gate electrodes 2 of the selection transistors are provided, and each selection is performed such that the patterns of wiring electrodes 4 and 5 of a plurality of signal lines connected to the source / drain of each selection transistor are in a Levenson arrangement. Adjacent active regions 1 forming transistors are alternately shifted in pairs. [Effect] Since the Levenson arrangement becomes possible and the pattern density can be improved, a highly integrated semiconductor integrated circuit device can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device for forming a pattern by using a phase shift mask, and more particularly to a semiconductor integrated circuit device capable of highly arranging an electrode wiring.

[0002]

2. Description of the Related Art In a method of forming an integrated circuit pattern using a phase shift mask, a phase shifter is arranged in an opening of a photomask so that a phase difference between exposure and transmission lights of adjacent patterns becomes 180 degrees. Fine pattern formation with high density (Levenson arrangement) becomes possible. The principle of the pattern formation method using this Levenson arrangement is as follows.
1982 IEE Transformer Electron Devices, ED-29, pp. 1828-1
836 (IEEE Trans. Electron Devices, ED-29, pp.1
828-1836, 1982).
It has become possible to form a pattern having a fine dimension smaller than the wavelength of the exposure light source.

Next, a conventional example using this technique for forming a pattern of a sensing circuit of a dynamic random access memory (hereinafter referred to as a dynamic RAM) will be described in more detail with reference to FIGS.

A memory array in a dynamic RAM includes a memory cell group including one transfer transistor and one charge storage capacitor, a word line group including a common gate of a transfer transistor extending in the X direction, and an orthogonal array. And a data line group electrically connected to the source or drain of the transfer transistor extending in the Y direction. The memory cell is arranged at the intersection of the data line and the word line.

More specifically, as shown by data lines D1, / D1, D1 ', / D1'... In the sense system circuit of FIG. A so-called folded data line type sense amplifier in which lines are folded has come to be used. Here, the symbol “/” represents inverse. References SA1 and S
A2 is a CMOS sense amplifier, PR is a precharge line,
I / O and YSW are column select gates, YS is a column select line,
SHR1 and SHR2 are select gates (S
HR gate). Here, these circuits are referred to as sense circuits. Y-DEC is a column decoder for driving such a sense circuit.

Further, in the case of such a folded data line type sense amplifier, the memory cells are arranged in a so-called "two-intersection" arrangement as shown in FIG. 11 and are connected to data pairs (for example, D1, / D1). Memory cells are arranged so that they are not selected by the same word line. Here, MC is a memory cell, WL1 and WL2 are word lines,
SAC1, SAC2,..., SACn are sense circuits, X
-DEC represents a row decoder, respectively, and the directions of the word lines and the data lines are different from those in FIG. 10 by 90 °.

Further, as shown in FIG. 10, since the left and right data pair lines can be selected by the right and left selection transistors of the sense amplifier, that is, the SHR gate, one sense amplifier is commonly used for the left and right memory cell arrays. Can be used. This type of sense amplifier is described in the Advanced Electronics Series published by Baifukan, Category I, I-9 on Electronics Materials, Properties, and Devices, “Ultra LSI Memory”, page 162.

FIG. 12 is a plan view showing a connection portion between a selection transistor of a sense circuit and a data pair line in such a dynamic RAM. In FIG.
1, / D1, D2, / D2 and the wiring electrodes in the sense amplifier for transmitting the read / write information of the memory cell to the data lines are formed by the wiring electrodes 104 and 105 of the same layer. Here, the wiring electrode 104 and the wiring electrode 105
Although formed in the same layer, in the photomask used at the time of pattern transfer, the wiring electrode 104 is provided with a pattern having a phase φ of 0, and the wiring electrode 105 is provided with a phase shifter such that the phase φ is 180 ° (φ = π). ing. That is, a fine and high-density pattern is formed on the wiring electrode pattern having the same pitch as the arrangement pitch of the memory cells, such as the data pair lines D1, / D1, D2, / D2, by using the phase shift method of the Levenson arrangement. Has formed.

In FIG. 12, reference numeral 102 denotes a common gate of the MOSFET formed on the active layer 101, and corresponds to the SHR gate of the equivalent circuit shown in FIG. Further, the wiring electrodes 104 and 105 are connected to the active region 101 of the silicon substrate via the opening 103.

[0010]

As described above,
By using the phase shift method of the Levenson arrangement, for example, the interval a of the wiring electrodes in the portion indicated by the line X1-X1 ′ in FIG. 12 can be made the minimum interval, and a high-density wiring electrode pattern can be formed. However, for example, in FIG.
In the portion indicated by the line X2 ′, an island-shaped wiring electrode 104s is provided.
A portion where the phase φ of the photomask pattern of the adjacent wiring electrodes 104 and 105 connected to the source of the selection transistor becomes the same is generated. Since the interval between the wiring electrodes in this portion is an interval b larger than the minimum interval a, there is a problem that the length of the sense amplifier in the lateral direction becomes longer.

Since the sense amplifier needs to connect one sense amplifier for every two data lines as described above, the pitch of the sense amplifier should be less than twice the data line pitch. This is desirable for reducing the chip area of the dynamic RAM.

As a result of a specific study with the arrangement shown in FIG. 12, when a krypton fluoride light source (KrF) having a wavelength of 246 nm is used, the minimum distance a is about 0.16 μm.
The distance b was 0.25 μm.

As described above, in the pattern used in the semiconductor integrated circuit device, the phase arrangement of 0, π, 0, π... In accordance with the phase shift method of the Levenson arrangement is not always possible.

An object of the present invention is to provide a semiconductor integrated circuit device to which the phase shift method of the Levenson arrangement can be applied. More specifically, the present invention provides a highly integrated semiconductor integrated circuit device having a layout pattern that does not cause inconsistency in the phase arrangement even if the pattern is a mixture of an island pattern and a linear pattern as shown in FIG. Is to do.

[0015]

To achieve the above object, a semiconductor integrated circuit device according to the present invention comprises at least a first and a second common gate extending linearly in a first direction, that is, an X direction. A plurality of select transistors, a first signal line group parallel to each other extending in a second direction orthogonal to the first direction, that is, the Y direction, connected to the drains of the plurality of select transistors; And a second parallel signal line group extending in the second direction and connected to the source of the select transistor, the drain of the select transistor related to the first common gate and the second The source of the selection transistor related to the common gate is arranged between the first common gate and the second common gate.

In this case, at least the drain of the selection transistor related to the first common gate and the source of the selection transistor related to the second common gate, which are arranged between the first common gate and the second common gate, are at least. It is preferable that one ends face each other.

In the above-described semiconductor integrated circuit device, the first signal line is a data line of a dynamic RAM in which a plurality of memory cells each including one transfer transistor and one charge storage capacitor are regularly arranged. Yes, first
Preferably, the selection transistor including the second common gate is a selection transistor that switches between the data line and a sense amplifier group having a folded data line configuration.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of a semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device having a plurality of parallel signal lines arranged via selection transistors. A plurality of common gate electrodes are used, and adjacent active regions forming each selection transistor are paired so that the wiring electrode pattern of a plurality of signal lines connected to the source / drain of each selection transistor has a Levenson arrangement. And the active regions of adjacent select transistors are alternately shifted.

By providing a plurality of selection transistor gates in this manner, the Levenson arrangement of the wiring electrode pattern becomes possible. Therefore, even in the part where the island pattern and the linear pattern are mixed, the phase shift method of the Levenson arrangement can be applied without contradiction, so that the pattern density of the semiconductor integrated circuit device can be improved, and the highly integrated semiconductor integrated circuit can be improved. The device can be realized.

[0020]

Next, a more specific embodiment of a semiconductor integrated circuit device according to the present invention will be described in detail with reference to the accompanying drawings.

<Embodiment 1> FIG. 1 is a plan view showing a first embodiment of a semiconductor integrated circuit device according to the present invention, showing a connection portion between a selection transistor of a sense amplifier and a data pair line in a dynamic RAM. I have. FIG. 2 is an equivalent circuit diagram of the sense system circuit portion of the present embodiment. FIG. 3 is a cross-sectional view of a portion along a line YY ′ shown in FIG. 1 and a cross-sectional view of a memory cell portion of a dynamic RAM connected to the portion.

In FIG. 1, data pairs D1, / D1,
D2 and / D2 and the wiring in the sense amplifier for transmitting the read / write information of the memory cell to the data line are formed by the wiring electrodes 4 and 5 in the same layer. Here, the wiring electrode 4 and the wiring electrode 5 are formed in the same layer. However, in a photomask used at the time of pattern transfer, the wiring electrode 4 has a pattern having a phase φ of 0, and the wiring electrode 5 has a phase shifter provided with a phase φ. Is 180 ° (φ = π). That is, by using the phase shift method of the Levenson arrangement for the wiring electrode pattern having the same pitch as the arrangement pitch of the memory cells such as the data pair lines D1, / D1, D2, / D2, Was formed.

More specifically, in this embodiment, if the minimum pattern width or the minimum pattern interval defined by the resolution of the pattern transfer is defined as the minimum dimension a, the pattern interval between the wiring electrodes 4 and 5 becomes The XX ′ line portion where the island-shaped wiring electrode 4s exists between the wiring electrodes also has the minimum dimension a unlike the conventional example shown in FIG.

Data pair lines D1, / D1 and D2,
/ D2 extends in the Y direction, and is connected to the active region 1 of the MOSFET which is a plurality of selection transistors arranged in the X direction via a plug electrode provided in the opening 3. This MOSFET has an active region 1 formed on a silicon substrate and a common gate (SH) of a selection transistor.
(R gate).

Here, two gate electrodes 2 extend in the X direction, and the source or drain of the MOSFET is
It is arranged between two gate electrodes 2. Further, the data pair lines D1, / D1 and D2, / D2 are arranged so as to share the same gate electrode. As a result, each active layer 1 is arranged side by side for each data pair line. That is, the active regions 1 are arranged so as to be alternately shifted in the Y direction in pairs of data pairs.

As shown in FIG. 2, an equivalent circuit of the sense system circuit according to this embodiment is a selection gate SH of a sense amplifier.
R1 is a sense amplifier S of a pair of data lines D1 and / D1.
It is composed of two select transistors connected to A1 and two select gates respectively connected to two select transistors connected to the sense amplifier SA2 of the pair of data lines D2 and / D2. In FIG. 2, reference numeral PR is a precharge line, I / O and YSW are column selection gates, YS is a column selection line, SHR1 and SH.
R2 indicates a data pair line selection gate.

As shown in the sectional view of FIG. 3, a wiring electrode to a selection transistor of a sense amplifier and a data line of a memory cell are formed by wiring electrodes 5 in the same layer. Further, two gate electrodes 2 of the selection transistor of the sense amplifier extend in a direction perpendicular to the plane of the drawing.

In FIG. 2, the pass transistor of the memory cell includes a gate oxide film 8 and a gate electrode 9;
Made of high-concentration n-type impurities serving as a source / drain,
The element is isolated by the field oxide film 7 on the p-type silicon substrate 6 (or, instead of the p-type silicon substrate, a p-type well formed on the silicon substrate for controlling the impurity concentration). It is formed in the active region. Here, the gate electrode 9 of the pass transistor has a thickness of 50 nm.
A composite film (polycide film) of tungsten and an n-type polycrystalline silicon film having a thickness of 30 nm was used. It is desirable to form a barrier metal such as a tungsten nitride film or a titanium nitride film between these films to prevent a reaction.

The silicon nitride films 10, 12
Is an etching stopper film for preventing the gate electrode and the plug electrode from being short-circuited due to process variations when forming the plug electrode in the opening on the n-type high-concentration impurity region 11. The wiring electrode 5 may be a refractory metal such as tungsten having a thickness of 50 nm, a composite film of the refractory metal and a polycrystalline silicon film, or a composite film of a silicide film of the refractory metal and a polycrystalline silicon film. .

Further, the high-concentration impurity region 11 of the pass transistor of the memory cell and the wiring electrode 5 of the data line are electrically connected by a polycrystalline silicon plug 14 formed through the interlayer insulating film 13.

The wiring electrode 5 is formed of an interlayer insulating film 13.
Tungsten plug 1 provided in an opening formed through
5 is electrically connected to the n-type high-concentration impurity region 11 of the select transistor of the peripheral circuit. Although not shown in the figure, a barrier metal such as titanium nitride is desirably formed below the tungsten plug 15 in order to prevent a reaction with the silicon substrate.

Further, a storage electrode 17 of a memory cell capacitor is provided above the word line (gate electrode 9) and the data line (wiring electrode 5). The shape of the storage electrode 17 is a so-called crown shape using the inner and outer side walls of the electrode in order to obtain a capacitance value necessary for stable operation even in a fine memory cell. A capacitor insulating film 18 is formed on the storage electrode 17, and a plate electrode 19 is further provided thereon.
Here, the storage electrode 17 is made of polycrystalline silicon having a thickness of 50 nm doped with phosphorus at a high concentration, and the capacitor insulating film 18 is made of tantalum pentoxide (Ta) having a thickness of 10 nm.
₂ O ₅ ), the upper plate electrode 19 having a thickness of 100 n
m titanium nitride film was used. Although not shown, the plate electrode 19 is fixed at a predetermined potential outside the memory cell.

Next, the chip configuration of the dynamic RAM according to this embodiment will be described with reference to FIGS. First, the mat configuration of the dynamic RAM will be described with reference to FIG. In the figure, reference numeral MA indicates a memory array unit which is the minimum unit of the memory array, and 1
In a G-bit class dynamic RAM, the memory array unit MA is about 256 Kbits. Also, S
AC is a sense-related circuit group having the above-described selection transistors, and the number of data pairs is equal to the number of data pairs in one row in the X direction. SWD is a sub-word driver constituting a row decoder. Further, these mats are arranged in the chip 21 for each block as shown in FIG. In FIG. 5, reference numeral 22 denotes a memory block, 23 denotes a peripheral circuit, and BP denotes a bonding pad.

According to this embodiment, by providing two SHR gates, the selection transistors can be arranged alternately shifted in the Y direction for each pair of data pairs in the peripheral circuit. Even if the phase of the pattern is switched so that adjacent wiring electrodes have the same phase pattern, the interval between the wiring electrodes of the peripheral circuit can be increased to b. Therefore, the resolution of the transfer pattern does not deteriorate. Here, the interval b is the minimum interval in the case of the in-phase pattern.

Therefore, in the portion where the wiring electrode 4s of the island pattern shown by the line XX 'in FIG. 1 is present, the phase φ of the wiring electrode pattern is set to the Levenson arrangement according to 0, π, 0, π. Each wiring electrode could be laid out with the minimum pattern interval a. As a result,
Peripheral circuits of the dynamic RAM, especially X of the sense circuit
The dimension in the direction can be reduced, and a dynamic RAM with a small chip area can be provided. This is because, as shown in FIG. 4, in the sense system circuit SAC, the number corresponding to the number of data pairs is arranged in a line in the X direction, and the number is 512 in a 1 Gbit class memory capacity.
Since the number of sense circuits SAC is 512 in the X direction and one in the Y direction for one memory array unit MA, the size reduction in the X direction greatly contributes to the chip area. This is because a slight increase in size has little effect on the increase in chip area and can be ignored.

<Embodiment 2> FIG. 6 is a view showing a second embodiment of the semiconductor integrated circuit device according to the present invention, and is a plan view of a select transistor portion of a sense circuit. In the figure, the same components as those of the first embodiment shown in FIG. 1 are denoted by the same reference numerals. Also in this embodiment, a plurality of selection transistors are arranged in the X direction, including the gate electrode 2, the active region 1, the opening 3, and the wiring electrodes 4 and 5 of the data pair line, as in the first embodiment. Further, the gate electrode 2 of the select transistor has two SHRs extending in the X direction.
It is a gate.

This embodiment is different from Embodiment 1 in the method of arranging the select transistors. That is, the active regions 1 of the adjacent select transistors are alternately shifted in the Y direction, and the wiring electrodes 4 and 5 of the adjacent portion connected by the active region 1 and the plug electrode provided in the opening 3 have the minimum size. They are arranged at an interval a. Also, the X1-X1 ′ line, X2-
As shown by the line X2 ', the wiring electrode 4s having an island pattern
In portions where the wiring electrodes 4 and 5 have a linear pattern, the phase φ of the mask pattern is in a Levenson arrangement.

According to this embodiment, one island pattern can be arranged in the peripheral circuit for each data pair line.
Layout flexibility can be increased. Therefore, the required area of the peripheral circuit of the dynamic RAM, particularly the required area of the sense circuit can be reduced, and a dynamic RAM having a small chip area can be provided.

<Embodiment 3> FIG. 7 is a diagram showing a third embodiment of the semiconductor integrated circuit device according to the present invention, and is an equivalent circuit diagram of a sense system circuit of a dynamic RAM. The present embodiment relates to the configuration of the control unit of the selection transistor in the first embodiment. In this figure, the same parts as those of the first embodiment shown in FIG. 2 are denoted by the same reference numerals.

In the present embodiment, as in the first embodiment, the SHR gates of the select transistors connected to the sense amplifiers SA1, SA2,. The active layer of the select transistor to which the pair lines D1 and / D1 are connected is connected to the data pair lines D2 and / D1.
The active layers of the select transistors to which D2 is connected are alternately shifted in the Y direction for each data line pair.

Further, in adjacent sense amplifiers to which different data pairs are connected, each SHR gate is independently controlled by circuits SEL1 and SEL2 of different drive systems.

According to the configuration of the present embodiment, the number of selection transistors activated when selecting a data line is reduced to half, and the load on the SHR gate is reduced. Thereby, the time required for reading / writing is reduced. Although the present embodiment is applied to the select transistor having the arrangement of FIG. 1, the present embodiment can be similarly applied to the select transistor of FIG. 6 shown in the second embodiment. In this case, different SHR gates may be connected to each data pair line, and each data pair line may be driven by a different driving system circuit.

<Embodiment 4> FIG. 8 is a view showing a fourth embodiment of the semiconductor integrated circuit device according to the present invention, and is a plan view of a selection transistor portion in a sense system circuit of a dynamic RAM. FIG. 9 is a cross-sectional view of a portion along the line YY ′ shown in FIG. The present embodiment uses a plurality of wiring electrodes in the memory cell portion of the dynamic RAM described in the first embodiment and the selection transistor of the sense amplifier.

The configuration of the sense circuit is described in the first embodiment.
The SHR gates of the selection transistors connected to the sense amplifiers SA1 and SA2
This is a pair. Also, as in FIG. 1, the active layer 1 of the select transistor to which the data pair lines D1 and / D1 are connected.
And the active layer 1 of the select transistor to which the data pair lines D2 and / D2 are connected are alternately shifted in the Y direction for each data pair line.

In FIGS. 8 and 9, the data pair line is the first line.
The wiring in the sense amplifier is formed by the wiring electrode of the second layer, and the wiring in the sense amplifier is formed by the wiring electrode of the second layer. Further, the phases φ of the mask patterns of the wiring electrodes 4 and 5 serving as the data lines are 0 and π, respectively, and the phases are alternately 0, π, 0, π.

Although the phase φ of the mask pattern of the wiring electrodes 204 and 205 of the sense amplifier is also 0 and π, the wiring electrode 204s of the island pattern alternately has 0 even in the portion along the line XX ′. , Π, 0, π, 0...

Here, it is desirable to use a high melting point metal for the first layer wiring electrodes 4 and 5 as in the first embodiment.
This is because a heat treatment for forming a capacitor at about 800 ° C. is required after forming the first layer wiring. As shown in FIG. 9, the first-layer wiring electrode 5 and the high-concentration n-type impurity region 11 of the selection transistor are connected by a tungsten plug 15 provided in the opening 3. The first-layer wiring 5 serving as a data pair line is connected to the high-concentration n-type impurity region 11 via an n-type polycrystalline silicon plug 14.

On the other hand, the second-layer wiring electrodes 204 and 205
Can be made of a low-resistance metal such as aluminum. Also, as shown in FIG.
5 and the high-concentration impurity region 11 of the select transistor are formed in the openings 20 formed through the interlayer insulating films 13, 16 and 20.
3 are connected by a metal plug 215 provided.

The dynamic RA shown in this embodiment is
The memory cell structure of M is the same as the structure of the first embodiment shown in FIG. This embodiment can also be applied to a case where a selection transistor is arranged as described in the second embodiment.

According to the present embodiment, since the wiring electrodes of the peripheral circuit are formed after the capacitors of the dynamic RAM cell are formed, defects in the wiring electrodes such as an increase in the contact resistance due to a heating step applied during the formation of the capacitors. Generation can be prevented.

The preferred embodiment of the present invention has been described above. However, the present invention is not limited to the above-described embodiment, and various design changes can be made without departing from the spirit of the present invention. It is. For example, although a dynamic RAM has been described as an example in the embodiment, the present invention can be applied to a so-called on-chip LSI (logic-mounted memory) in which a plurality of LSIs such as a memory circuit and a logic circuit are mixed in the same chip. Thereby, the function and performance of the LSI are improved.

[0052]

As is clear from the above-described embodiments, according to the present invention, the pattern density of the semiconductor integrated circuit, particularly the wiring electrodes, can be increased, and a highly integrated semiconductor integrated circuit device can be realized. it can.

[Brief description of the drawings]

FIG. 1 is a plan view showing a first embodiment of a semiconductor integrated circuit device according to the present invention.

FIG. 2 is an equivalent circuit diagram of a sense system circuit portion of the first embodiment.

FIG. 3 is a cross-sectional view of a main part of the semiconductor integrated circuit device including a portion along a line YY ′ shown in FIG. 1;

FIG. 4 is a block diagram showing a mat configuration of a dynamic RAM to which the present invention is applied;

FIG. 5 is a chip configuration diagram of the dynamic RAM shown in FIG. 4;

FIG. 6 is a plan view showing a second embodiment of the semiconductor integrated circuit device according to the present invention.

FIG. 7 is an equivalent circuit diagram of a sense system circuit portion of a dynamic RAM according to a third embodiment of the semiconductor integrated circuit device according to the present invention.

FIG. 8 is a plan view showing a fourth embodiment of the semiconductor integrated circuit device according to the present invention.

FIG. 9 is a cross-sectional view of a main part of the semiconductor integrated circuit device including a portion along the line YY ′ shown in FIG. 8;

FIG. 10 is an equivalent circuit diagram of a sense circuit portion of a conventional dynamic RAM.

11 is a block diagram showing an arrangement of memory cells of the dynamic RAM shown in FIG.

FIG. 12 is a plan view showing a connection portion between a selection transistor of a sense amplifier and a data pair line in a conventional dynamic RAM.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Active area, 2, 9 ... Gate electrode, 3, 203 ... Opening, 4, 5 ... Wiring electrode, 4s, 104s, 204s ... Island electrode, 6 ... Silicon substrate, 7 ... Field oxide film, 8
... Gate insulating film, 10, 12 silicon nitride film, 11 high-concentration impurity region, 13, 16, 20 interlayer insulating film, 14 polycrystalline silicon plug, 15 tungsten plug, 17 storage electrode, 18 Capacitor insulating film, 19: plate electrode, 22: memory block, 23
... peripheral circuits, 204, 205 ... second-layer wiring electrodes, 2
15 Metal plug.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Ken Sakata 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. Central Research Laboratory (72) Inventor Hideyuki Matsuoka 1-280 Higashi-Koigakubo, Kokubunji-shi, Tokyo F-term in Central Research Laboratory, Hitachi, Ltd.F-term (reference)

Claims (3)

[Claims] 1. A plurality of select transistors each including at least a first and a second common gate extending linearly in a first direction, and a first select transistor connected to a drain of the plurality of select transistors.
A first signal line group extending in a second direction orthogonal to the first direction, and a second signal extending in a second direction connected to the sources of the plurality of selection transistors; In the semiconductor integrated circuit device including the line group, the drain of the select transistor related to the first common gate and the source of the select transistor related to the second common gate are:
A semiconductor integrated circuit device disposed between a first common gate and a second common gate. 2. A drain of a select transistor according to a first common gate and a source of a select transistor according to a second common gate disposed between the first common gate and the second common gate, at least. 2. The semiconductor integrated circuit device according to claim 1, wherein one ends face each other. 3. The dynamic random access memory according to claim 1, wherein the first signal line is a data line of a dynamic random access memory in which a plurality of memory cells each including one transfer transistor and one charge storage capacitor are regularly arranged. 2. The selection transistor comprising the first and second common gates, the selection transistor switching between the data line and a sense amplifier group having a folded data line configuration.
Alternatively, the semiconductor integrated circuit device according to claim 2.