JP2000077419A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: Provided are a semiconductor device capable of reducing an element region and increasing an operation speed, and a method for manufacturing the same. SOLUTION: An element region (N-type high-concentration impurity region) 104 corresponding to a collector layer, a P-type silicon layer 105 corresponding to a base region, and an N-type silicon layer 107 corresponding to an emitter region are formed in a self-aligned manner. Therefore, there is no need to provide an allowance between them, and the element area can be reduced. Further, unlike the conventional device, there is almost no parasitic capacitance between the emitter electrode 112 and the base electrode 113, so that the operation speed is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device including a bipolar transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, bipolar transistor devices have been used in various application fields such as computers, optical communications, and various analog circuits. In the following literatures and the like, a bipolar transistor incorporating an epitaxial technique is proposed, and the cutoff frequency of a prototyped bipolar transistor is about to reach 60 GHz. (1) IEEE Trans on Electron Device, vol. ED-38,
Feb. 1991, p. 378 (2) IEDM'90, p. 13 (3) JP-A-05-175222 The structure of a conventional device and a method of manufacturing the same will be described below with reference to FIG. As shown in FIG.
N ⁺ type buried layer 302 on the surface of type semiconductor substrate 301
, An N-type epitaxial layer 303 is formed in a state where the elements are separated by a silicon oxide film 304.
This N-type epitaxial layer 303 corresponds to an element region for forming a collector, and the P-type with boron introduced on its surface.
Type silicon layer 305 is formed by epitaxial growth.

[0003] A silicon oxide film 306 is formed on a silicon layer 305 on a region where an emitter / base is to be formed by a thermal oxidation method. Polysilicon layer 307 is formed on the surfaces of silicon oxide film 306 and silicon layer 305. Boron ions are implanted into the polycrystalline silicon layer 307, and the entire surface is subjected to CVD (Chemical Vapor Dep.
The silicon oxide film 308 and the silicon nitride film 309 are sequentially formed by the osition method. A photo-etching method and a photo-etching technique are used to form a polycrystalline silicon layer 307,
A hole 310 is opened in the silicon oxide film 308 and the silicon nitride film 309.

[0004] A silicon nitride film is deposited on the entire surface, and is etched back by anisotropic etching. As a result, the silicon nitride film 311 is left only on the side wall of the hole 310 as shown in FIG. The silicon oxide film 306 on the bottom surface of the hole 310 is removed by etching using an NH ₄ F solution or the like.
The surface of is exposed. A polycrystalline silicon layer 312 into which arsenic is introduced at a high concentration is deposited, arsenic is diffused through a heat treatment step, and an N-type emitter layer 313 is formed. here,
The polycrystalline silicon layer 307 is used as a base electrode,
The polycrystalline silicon layer 312 is used as an emitter electrode.

[0005] A conventional device is manufactured through the above-described steps and has a cross-sectional structure as shown in FIG.

[0006]

However, the conventional semiconductor device has the following problems. The N-type epitaxial layer 303 as a collector region and the emitter region 313 are not formed in a self-aligned manner, but are combined by photolithography. In addition, the silicon layer 305 as the base region requires a silicon oxide film 306 as a protective film, but the silicon oxide film 306 and the epitaxial layer 303 are not formed in a self-aligned manner.

Therefore, conventionally, a margin is required between the silicon oxide film 306 and the epitaxial layer 303 as a collector region, and further, between the silicon oxide film 306 and the emitter region 313, so that the element region is increased. . Further, as shown in FIG. 3D, a silicon oxide film 30 is provided between the emitter electrode 312 and the base electrode 307.
8 and the silicon nitride film 309 or the silicon nitride film 311, the capacitances C1 and C2 between the base and the emitter increase, which hinders high-speed operation.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device capable of reducing an element region and increasing an operation speed, and a method of manufacturing the same.

[0009]

According to the present invention, there is provided a semiconductor device comprising:
A first insulating film formed in an element isolation region on a semiconductor substrate, and a first insulating film formed in an element region on the semiconductor substrate;
A collector layer of a first conductivity type having a surface height higher than that of the first insulation film; a first semiconductor layer of a second conductivity type formed on the surfaces of the first insulation film and the collector layer; A second insulating film formed on the surface of the first semiconductor layer located on the first insulating layer; and a first conductive film formed on the surface of the first semiconductor layer located on the collector layer. And a second semiconductor layer of a mold type.

Here, the first semiconductor layer is formed using single crystal silicon containing a hetero material having a band gap smaller than silicon, and the second semiconductor layer is formed using a single crystal silicon containing a hetero material having a band gap larger than silicon. When formed using crystalline silicon, a heterojunction transistor is formed.

In a method of manufacturing a semiconductor device according to the present invention, a step of forming a collector layer of a first conductivity type in an element region on a semiconductor substrate; Forming a first insulating film so that the height of the surface is reduced, and forming a first semiconductor layer of the second conductivity type on the surfaces of the collector layer and the first insulating film by non-selective epitaxial growth. And depositing a second insulating film on the surface of the first semiconductor layer, etching the second insulating film to remove a portion corresponding to the collector region, and removing the first semiconductor layer. Exposing the surface of the first semiconductor layer and selectively growing the first semiconductor layer on the exposed surface of the first semiconductor layer by selective epitaxial growth.
Forming a conductive type second semiconductor layer.

Further, a method of manufacturing a semiconductor device according to the present invention
Forming a first insulating film on a semiconductor substrate, opening a hole in a collector formation region, and depositing a semiconductor layer of a first conductivity type so as to fill the hole; Forming a collector layer having a high height, forming a first semiconductor layer of a second conductivity type on a surface of the collector layer and the surface of the first insulating film by non-selective epitaxial growth, Depositing a second insulating film on the surface of the semiconductor layer, etching the second insulating film to remove a portion corresponding to the collector region, and exposing the surface of the first semiconductor layer; Selectively forming a second semiconductor layer of the first conductivity type by selective epitaxial growth on a region of the first semiconductor layer where the surface is exposed.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a cross-sectional structure of a semiconductor device according to a first embodiment of the present invention and a method of manufacturing the same. FIG.
As shown in (a), the P-type semiconductor substrate 101 has N ⁺
N-type low-concentration impurity layer 104 having an impurity concentration of about 1 × 10 ¹⁶ cm ⁻³ is formed on the surface thereof.
Is formed by epitaxial growth. further,
A trench is formed in the element isolation region for the impurity layer 104 using a trench technique, and the trench is filled with the silicon oxide film 103 using a selective filling technique. Here, since the impurity layer 102 is connected to a not-shown collector contact portion, the impurity layer 10
4 constitutes a part of the collector.

As shown in FIG. 1B, the exposed surface of the silicon oxide film 103 is removed by an etching technique, and the side surface of the impurity layer 104 is exposed. Further, etching is continued for about 1000 angstroms using an NH ₄ F solution or the like, and a step is provided between the impurity layer 104 and the silicon oxide film 103.

As shown in FIG. 1C, a non-selective epitaxial growth method is used to form a film having a thickness of 700 over the entire surface.
Approximately angstrom and boron impurity concentration of about 4 × 1
A P-type silicon layer 105 of 0 ¹⁸ cm ^-3 is formed. This silicon layer 105 corresponds to a base region. A silicon oxide film 10 is formed on the surface of the silicon layer 105 by CVD.
6 is formed to a thickness of about 5000 angstroms, and etch back is performed until the surface of the silicon layer 105 located on the impurity layer 104 is exposed.

As shown in FIG. 1D, an N-type silicon layer 107 is selectively formed only on the exposed surface of the silicon layer 105 by using a selective epitaxial growth method.
The silicon layer 107 has a thickness of about 2000 angstroms, and arsenic is introduced at a high concentration so as to have an impurity concentration of about 1 × 10 ²⁰ cm ^−3, and corresponds to an emitter layer.

A silicon nitride film 108 is coated on the entire surface by about 2
Deposited by CVD with a thickness of 000 Å. Etchback is performed by anisotropic etching, and the silicon nitride film 108 is left on the side wall of the silicon layer 107. Silicon layer 107 and silicon nitride film 108
Is used as a mask to etch silicon oxide film 106, exposing the surface of silicon layer 105 located on silicon oxide film 103. Next, the silicon layer 105
And 107 are exposed to metal silicide to form, for example, titanium silicide (TiSi ₂ ) films 109 and 110. Thereby, the resistance of the surfaces of the silicon layer 105 and the emitter layer 107 that become the base region is reduced.

As shown in FIG. 1E, a silicon oxide film is deposited on the entire surface by the CVD method, and a contact is made between the surface of the silicon layer 107 as an emitter region and the silicon layer 105 as a base region. A hole is opened. Aluminum is deposited on the entire surface by a sputtering method, patterning is performed using a photolithography method and an etching method, and an emitter electrode wiring 112 and a base electrode wiring 113 are formed, thereby forming a bipolar transistor.

As described above, according to the present embodiment, the silicon layer 105 serving as the base region is formed by non-selective epitaxial growth including the surface of the impurity layer 104 serving as the element region.
Is formed, and a silicon layer 107 to be an emitter region is formed by selective epitaxial growth. As a result, the base region and the emitter region can be formed in a self-aligned manner with respect to the element region, and the area of the element can be reduced since no alignment margin is required. Further, FIG.
The emitter electrode 312 and the base electrode 30 shown in FIG.
Unlike the conventional device in which the capacitances C1 and C2 are parasitic between the first and second capacitors 7, such a parasitic capacitance hardly exists in the present embodiment, which can contribute to an increase in operation speed.

Next, a second embodiment of the present invention will be described with reference to FIG. In the first embodiment, N ⁺
N-type low concentration impurity layer 104 on N-type high concentration impurity layer 102
Is formed, a trench is formed in the element isolation region, and the silicon oxide film 103 is buried. Then, the silicon oxide film 103 is etched, so that a step is formed between the impurity layer 104 and the silicon oxide film 103.

On the other hand, in the second embodiment, FIG.
As shown in (a), the N ⁺ type high concentration impurity layer 102
A silicon oxide film 201 is deposited thereon by a CVD method. A hole 202 is formed in the silicon oxide film 201 by using a photolithography method and an etching method.

As shown in FIG. 2B, an N-type low-concentration impurity layer 203 is selectively formed only on the surface of the impurity layer 102 exposed at the bottom of the hole 202 by using a selective epitaxial growth method. You. In this step, impurity layer 203 is formed such that impurity layer 203 is thicker than silicon oxide film 201 and has a step. The subsequent steps from FIG. 2 (c) to FIG. 2 (e) are the same as in the above-described first embodiment, and a description thereof will be omitted.

In order to form the base region and the emitter region in a self-aligned manner with respect to the element region, it is important to provide a step between the N-type low concentration impurity layer 104 and the silicon oxide film 103. In the first embodiment, it is necessary to control the amount of etching of the silicon oxide film 103 with time, and it is somewhat difficult to form a step having a desired height. On the other hand, in the second embodiment, a step may be formed by controlling the film thickness of the silicon layer 202 deposited by performing non-selective epitaxial growth on the bottom surface of the hole 202. Excellent in nature.

The above-described embodiments are merely examples, and do not limit the present invention. For example, the material, thickness, forming method, and the like of each film in the above embodiment can be modified as needed.

When it is not necessary to reduce the resistance of the surfaces of the silicon layers 105 and 107, it is not necessary to form the side wall of the insulating layer on the side surface of the silicon layer 107.

Further, a silicon layer 105 formed as a base region is formed using a material having a smaller band gap than silicon, for example, single crystal silicon containing Ge, and a silicon layer 107 formed as an emitter region is formed.
Is formed using a material having a larger band gap than silicon, for example, silicon containing C, it is also possible to obtain a heterojunction transistor having excellent high-frequency characteristics.

[0028]

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, the first and second semiconductor layers are formed in a self-aligned manner with respect to the collector layer, and no alignment margin is required. As a result, the element area can be reduced.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a sectional structure of a semiconductor device according to a first embodiment of the present invention and a method for fabricating the same, in each step.

FIGS. 2A and 2B are longitudinal sectional views illustrating a sectional structure of a semiconductor device according to a second embodiment of the present invention and a method of manufacturing the same; FIGS.

FIG. 3 is a longitudinal sectional view showing a sectional structure of a conventional semiconductor device and a method of manufacturing the same, showing steps by process.

[Explanation of symbols]

Reference Signs List 101 P-type semiconductor substrate 102 N ⁺ type high concentration impurity layer 103, 111, 201 Silicon oxide film 104, 203 N-type low concentration impurity layer 105 P-type silicon layer (base region) 106 Silicon oxide film 107 N-type silicon layer (emitter Region) 108 Silicon nitride film (sidewall) 109, 110 Titanium silicide film 112 Emitter electrode wiring 113 Base electrode wiring 202 Hole

Claims (4)

[Claims] A first insulating film formed in an element isolation region on a semiconductor substrate; and a first conductive film formed in an element region on the semiconductor substrate and having a surface height higher than that of the first insulating film. Type collector layer; a second conductive type first semiconductor layer formed on the surface of the first insulating film and the collector layer; and the first semiconductor layer located on the first insulating film A second insulating film formed on the surface of the first semiconductor layer, and a second semiconductor layer of the first conductivity type formed on the surface of the first semiconductor layer located on the collector layer. A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein the first semiconductor layer is formed using single crystal silicon including a hetero material having a band gap smaller than that of silicon, and the second semiconductor layer is formed using a single crystal silicon including a hetero material having a band gap larger than silicon. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed using silicon. 3. A step of forming a first conductivity type collector layer in an element region on a semiconductor substrate, wherein a surface height is lower than that of the collector layer in a region other than the collector layer on the semiconductor substrate. Forming a first insulating film, forming a first semiconductor layer of a second conductivity type on the surfaces of the collector layer and the first insulating film by non-selective epitaxial growth, Depositing a second insulating film on the surface of the semiconductor layer;
Etching the second insulating film to remove a portion corresponding to the collector region to expose the surface of the first semiconductor layer; and selecting a portion on the surface of the first semiconductor layer where the surface is exposed. The second of the first conductivity type is selectively formed by epitaxial growth.
Forming a semiconductor layer according to claim 1. A method for manufacturing a semiconductor device, comprising: 4. A step of forming a first insulating film on a semiconductor substrate and opening a hole in a collector formation region; depositing a first conductivity type semiconductor layer so as to fill the hole; A step of forming a collector layer having a surface height higher than that of an insulating film; and a step of forming a first semiconductor layer of a second conductivity type on the surfaces of the collector layer and the first insulating film by non-selective epitaxial growth. Depositing a second insulating film on a surface of the first semiconductor layer;
Etching the second insulating film to remove a portion corresponding to the collector region to expose the surface of the first semiconductor layer; and selecting a portion on the surface of the first semiconductor layer where the surface is exposed. The second of the first conductivity type is selectively formed by epitaxial growth.
Forming a semiconductor layer according to claim 1. A method for manufacturing a semiconductor device, comprising: