JP2000076888A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need for the selection of a WL to be replaced with a redundant address, to select a redundant WL directly and to ensure the high- speed properties of an access to a memory cell. SOLUTION: The semiconductor memory has a redundant address generating circuit 2, a plurality of decoders 5A-5D decoding address data from the redundant address generating circuit 2, a plurality of latch means 8A-8D latching decoding values from a plurality of the decoders respectively, and gate circuits 10A-10D electrically conducting or interrupting the decoding values from a plurality of the decoders in response to the output signals of a plurality of the latch means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM, an SRA
The present invention relates to a semiconductor memory in which a redundancy circuit used in a semiconductor device memory such as a nonvolatile memory or a nonvolatile memory is improved.

[0002]

2. Description of the Related Art When a memory cell or the like has a defect and cannot be used, a technique of using a redundant memory cell previously formed in a semiconductor memory instead of the memory cell is known. The address of the defective memory cell is known when the semiconductor memory is manufactured. The address of the defective memory cell is stored in the redundant address generation circuit. Then, it is always monitored whether or not there is a defective address in the address generated from the normal address generation circuit, and if there is a defect, the switching is performed so as to designate the redundant memory cell. That is, the address line of the defective memory cell is
Try not to use it.

FIG. 2 shows a part of an addressing circuit of a semiconductor memory having such a redundancy function. Address data for address designation is added to the address generation circuit (1) in FIG. The redundant address generation circuit (2) stores address data of a defective memory cell found by a test at the time of manufacturing a semiconductor memory. The comparator (3) compares the output signal of the address generation circuit (1) with the output signal of the redundant address generation circuit (2), and when the address data of the defective memory cell is generated from the address generation circuit (1). An "H" level signal is generated, and otherwise an "L" level signal is generated. The first switching means (4) selectively switches and outputs an output signal of the address generation circuit (1) and an output signal of the redundant address generation circuit (2) in accordance with an output signal of the comparator (3). I do. Decoder (5
A) to (5D) decode the address data from the first switching means (4). This decoding includes decoding for specifying a normal memory cell and decoding for specifying a defective memory cell, that is, decoding for a redundant address. The decoders (5A) to (5D) are connected to WL (word lines) 0 to WL3. Although omitted in the drawing, a large number of decoders and WLs are actually connected.

When a normal address which is not a redundant address is generated, the output signal of the address generating circuit (1) is set to the first signal.
(5A) through (5A)
D), and the output of the decoder corresponding to the selected WL becomes “H” level. Thereby, the designation of the memory cell is performed.

Next, when a redundant address is generated from the address generating circuit (1), an "H" level is generated from the comparator (3), and "L" is applied to each AND gate constituting the first switching means (4). Level. Therefore, the address from the address generation circuit (1) is supplied to the decoders (5A) to (5A).
D) will not be added.

On the other hand, the "H" level from the comparator (3) is applied to the AND gate (6) to make the AND gate (6) conductive. Then, an address designation signal is transmitted from the redundancy address generation circuit (2) to the redundancy WL via the AND gate (6), and the redundancy memory cell can be addressed.

Therefore, according to the apparatus shown in FIG. 2, a redundant address can be specified.

[0008]

However, in the apparatus shown in FIG. 2, it takes time to select a redundant WL, and there is a problem in terms of high-speed operation.

In the apparatus shown in FIG. 2, when a redundant address is generated from the address generating circuit (1), the decoder (5)
In A) to (5D), a signal is applied and WL is selected. After that, the comparator (3) operates and the prohibition operation is performed. At the same time, the AND gate (6) becomes conductive, and the redundant WL is selected.

[0010] Therefore, a multiple selection period occurs in which two WLs are simultaneously selected, which is not suitable for high-speed operation.

Further, when the memory is a nonvolatile flash memory and all WLs need to be selected simultaneously at the time of erasing, if a defective cell having a leak property is selected, a high voltage required for erasing is generated. I can no longer do it. In a flash memory, it is necessary to apply a high voltage of about 14 V to all WLs at the time of erasing. At the time of erasure, the decoder (5
A) to (5D) are all selected. The high voltage from the high voltage generation circuit (7) is supplied to the decoders (5A) to (5A).
D) through WL0 to WL3. here,
If any of the memory cells (redundancy target cells) to which WL0 to WL3 is connected has a leak failure, the voltage of WL0 to WL3 cannot rise to about 14V. Then, all the memory cells connected to WL0 to WL3 cannot be erased normally.

Further, as another method, there is a method of cutting off the output terminal of the decoder to which the defective memory cell is connected by inserting a physical fuse. But the physical fuse is
This leads to an increase in the area of the semiconductor chip, and the reliability is not high.

[0013]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and comprises a redundant address generating circuit, a plurality of decoders for decoding address data from the redundant address generating circuit, and A plurality of latch means for latching decode values from the plurality of decoders, and a gate circuit for conducting or blocking the decode values from the plurality of decoders in accordance with output signals of the plurality of latch means, respectively. Before the addressing operation, redundant information is latched by the plurality of latch means so that an address signal is not transmitted to a specific address line during a normal addressing operation. Further, the present invention provides an address generating circuit, a redundant address generating circuit, a comparator for comparing an output signal of the address generating circuit and an output signal of the redundant address generating circuit, and according to an output signal of the comparator. Switching means for selectively switching and outputting an output signal of the address generating circuit and an output signal of the redundant address generating circuit; a plurality of decoders for decoding address data from the switching means; and a decoding from the plurality of decoders A plurality of latch units each latching a value, and a gate circuit that conducts or cuts off a decoded value from the plurality of decoders according to an output signal of the plurality of latch units,
Redundant information is latched by the plurality of latch means before a normal addressing operation, so that an address signal is not transmitted to a specific address line during a normal addressing operation.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory according to the present invention will be described with reference to FIG. (8A) to (8D) are decoders (5
(A) to (5D), latch circuits for latching the decode values from (5D), and (9A) to (9D) are the latch circuits (5).
A) to (5D) and the latch circuits (8A) to (8A).
(D) transistors connected to each other,
Reference numerals (10D) to (10D) denote gate circuits that conduct or cut off the decoded values from the decoders (5A) to (5D) according to the output signals of the latch circuits (8A) to (8D).

In FIG. 1, the same components as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted.

First, the operation when the power of a DRAM or the like is turned on will be described. When the power is turned on, there is a period called a power-on period or the like where access to an address cannot be performed yet. Utilizing the period, the redundant address is written in the latch circuits (8A) to (8D) in advance to control the opening and closing of the gate circuits (10A) to (10D). The writing is performed by turning on the transistors (9A) to (9D).

That is, the gate of the WL to be replaced with the redundant address is closed so that the output of the decoder is not added to the WL. This eliminates the need to select a WL to be replaced with a redundant address, allows direct selection of a redundant WL, and ensures high speed.

A case where the memory is a non-volatile flash memory, which is at the time of erasing, and all WLs are simultaneously selected will be described. Also in this case, the transistors (9A) to (9D) are turned on immediately before the batch erase command, and the redundant address is written to the latch circuits (8A) to (8D). In this state, an address for batch erasure is specified by the block erase selection circuit (11). That is, switching is performed so that a high voltage is generated from all of the decoders (5A) to (5D). At this time, for example, assuming that WL3 is a target for redundancy, an "L" level signal is generated from the latch circuit (8D). Therefore, even if a high voltage is generated from the decoder (5D), it is not transmitted to WL3.

Since an "H" level is output from the latch circuits (8A) to (8C), a high voltage is applied to the other WLs of the WL3 to enable erasing.

At this time, even if there is a leak defect in WL3, the influence does not affect other WLs by the function of the gate circuit (10D).

Incidentally, since the redundant WL operates in the same manner as in the prior art instead of the WL3, the flash memory can be erased at once.

FIG. 3 shows another embodiment of the transistor and latch circuit of FIG. The transistor (20) in FIG. 3 corresponds to the function of the transistors (9A) to (9D) in FIG. 1, and the latch circuit (21) in FIG.
These correspond to the functions A) to (8D). When the power is turned on, an “L” level signal is applied to the reset terminal (22) and the set terminal (23). The power supply voltage rises, and FIG.
At time t1. FIG. 4A shows the height of the power supply voltage VDD of the power supply terminal (23) in FIG. FIG.
(B) is a reset signal re applied to the reset terminal (22).
FIG. 4 (c) shows a set signal set applied to the set terminal (23). At time t1, since the power supply voltage VDD is applied to the latch circuit (21) via the transistor 24, the output signal of the latch circuit (21) becomes "H" level. Then, the gate circuit 27 composed of the NAND and the inverter is turned on, and the output signal of the decoder 25 remains at W
L.

Next, when the reset signal rises at time t2, the transistor 24 is turned off. Immediately after the reset signal rises, the set signal rises at time t3. The set signal turns on the transistor 20 and enables the latch circuit (21) to capture redundant information. If "H" indicating redundancy is output from the decoder 25 while the transistor 20 is on, the transistor 2
6 is turned on to apply the "L" level to the latch circuit (21). Then, the “L” level is applied to the gate circuit 27 from the latch circuit (21). After that, transistor 2
0 turns off, and a normal decoder output is generated. In this case, if the WL in FIG.
Since 1) applies the "L" level to the gate circuit 27, the output signal of the decoder 25 is not transmitted to WL.

[0024]

According to the present invention, the gate of the WL to be replaced with the redundant address is closed so that the output of the decoder is not added to the WL, so that the WL to be replaced with the redundant address is not selected. , It is possible to directly select a redundant WL, and high-speed access to a memory cell is ensured.

According to the present invention, since a latch circuit and a gate circuit are provided for each WL, a state in which a high voltage is not applied due to a leak does not occur even when the flash memory is collectively erased.

Further, according to the present invention, since redundancy is performed only by a circuit method, there is no increase in the area of the semiconductor chip and the reliability is high.

[Brief description of the drawings]

FIG. 1 is a semiconductor memory of the present invention.

FIG. 2 is a conventional semiconductor memory.

FIG. 3 is a specific circuit diagram of the present invention.

FIG. 4 is a waveform chart for explaining the operation of FIG. 3;

[Explanation of symbols]

Claims (3)

[Claims] 1. A redundant address generating circuit, a plurality of decoders for decoding address data from the redundant address generating circuit, a plurality of latch means for respectively latching decode values from the plurality of decoders, and the plurality of decoders A gate circuit that conducts or cuts off a decode value from the plurality of latch means in accordance with output signals of the plurality of latch means, and causes the plurality of latch means to latch redundant information before a normal addressing operation to perform normal address designation. A semiconductor memory wherein an address signal is not transmitted to a specific address line during operation. 2. An address generating circuit, a redundant address generating circuit, a comparator for comparing an output signal of the address generating circuit with an output signal of the redundant address generating circuit, and Switching means for selectively switching and outputting an output signal of an address generation circuit and an output signal of the redundant address generation circuit; a plurality of decoders for decoding address data from the switching means; and a decode value from the plurality of decoders A plurality of latch units each of which latches, and a gate circuit that conducts or cuts off the decode values from the plurality of decoders in accordance with the output signals of the plurality of latch units, and the redundant information is provided before the normal addressing operation. Are latched by the plurality of latch means so that an address signal is not transmitted to a specific address line during a normal addressing operation. Semiconductor memory is characterized in that as. 3. An address generating circuit, a redundant address generating circuit, a comparator for comparing an output signal of the address generating circuit with an output signal of the redundant address generating circuit, and First switching means for selectively switching and outputting an output signal of an address generation circuit and an output signal of the redundant address generation circuit; a plurality of decoders for decoding address data from the switching means; A plurality of latch units each of which latches a decoded value of the plurality of decoders; a second switching unit respectively connected between the plurality of decoders and the plurality of latch units; A gate circuit that conducts or cuts off in accordance with an output signal of the latch means, wherein the redundant information is stored in the plurality of latch means before a normal addressing operation. Wherein the address signal is not transmitted to a specific address line during a normal addressing operation.