JP2000076852A - Synchronous semiconductor memory device - Google Patents

Abstract

(57) Abstract: Provided is a synchronous semiconductor memory device including an internal synchronous signal generation circuit capable of switching between a DLL circuit operation and a PLL circuit operation. SOLUTION: In a DLL operation mode, a variable delay circuit 1 is provided.
10, a phase comparison circuit 120, and a shift logic circuit 180
, The delay control value holding circuit 170 and the variable constant current circuit 14
0 and the voltage generation circuit 150 form a delay locked loop circuit. In the PLL operation mode, a signal from the central portion of the variable delay
Is supplied to the input of the variable delay circuit 110 to form a ring oscillator.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a synchronous semiconductor memory device that operates in synchronization with an external clock signal. More specifically, the present invention relates to a semiconductor memory device having an internal synchronization signal generation circuit such as a DLL (Delay Locked Loop) circuit that receives an external clock signal and generates a synchronized internal clock signal.

[0002]

2. Description of the Related Art Recent microprocessors (hereinafter referred to as MPs)
U), a synchronous DRAM that operates in synchronization with a clock signal to realize high-speed access to a dynamic random access memory (hereinafter, referred to as DRAM) used as a main storage device, etc.
(Synchronous DRAM; hereinafter, referred to as SDRAM) and the like. In such a semiconductor memory device operating in synchronization with an external clock signal, a PLL circuit, a DLL circuit, and the like for generating an internal clock signal synchronized with the external clock signal are mounted inside the semiconductor memory device. That is common.

FIG. 45 is a schematic block diagram showing a configuration of a conventional internal synchronization signal generating circuit 5000 disclosed in Japanese Patent Application Laid-Open No. 9-293374.

Referring to FIG. 45, synchronization signal generating circuit 30
00 is the external clock signal Ext. And a delay circuit 5110 that receives the external clock signal Ext. CLK and an output of delay circuit 5110, and a phase comparator 512 for detecting a phase difference between the two.
0 and a switch decoder 51 for outputting a constant current source switch signal CS in accordance with the detection result of the phase comparator 5120.
30, a variable constant current source circuit 5140 for receiving a signal CS and supplying a corresponding constant current value, and a variable constant current source circuit 51
A delay control circuit 51 that outputs a control signal for controlling the delay amount of the delay circuit 5110 in accordance with the constant current value output from the delay circuit 5110
50.

The delay circuit 5110 includes an n-stage cascaded inverter circuit Inv. 1 to Inv. n. Each inverter circuit Inv. i (i = 1, 2,... n)
Are coupled to power supply potential Vcc via p-channel MOS transistor P1i and to ground potential GND via n-channel MOS transistor N1i. The gate potential level of each p-channel MOS transistor P1i and the gate potential level of n-channel MOS transistor N1i are controlled by delay control circuit 5150.

That is, the inverter circuit Inv. 1 to Inv. The current value supplied to n is controlled by the delay control circuit 5150. In other words, each inverter circuit Inv. i (i = 1, 2,...)
The delay time in n) changes according to the control signal from the delay control circuit 5150.

The variable constant current source circuit 5140 includes m internal constant current source circuits CS11, CS21,... CSm1 and m internal constant current source circuits CS12, CS22,. One end of the constant current source circuit CS11 has a power supply potential Vc.
c and connected to the output node 514 via a switch circuit SW11 which is opened and closed by the other end constant current source switch signal CS.
0a.

Other constant current source circuits CS21,... CSm
1, one end is connected to the power supply potential Vcc,
The other end is connected to the output node 5140a via each of the switch circuits SW21,..., SWm1.

On the other hand, internal constant current source circuits CS12 and CS2
,..., CSm2 also have one ends each controlled by a constant current source switch signal CS to open and close the switch circuit SW.
, SW22,..., SWm2, output node 51
The other end is connected to the power supply potential GND.

Therefore, the constant current value supplied to output node 5140a is equal to the value of switch circuits SW11, SW21,.
... SWm2 are increased when the switch SWm1 is turned on, and decreased when the switch circuits SW12, SW22,.

Therefore, according to the value of the constant current source switch signal CS, the switch circuits SW11, SW21,.
m1, and switch circuits SW12, SW22,..., SW
By opening and closing m2, the corresponding constant current value is 5140
a, and the delay control circuit 5150 operates according to the constant current value as described later.

Variable constant current source circuit 5140 further includes a free-running current source 144 for supplying a predetermined constant current value to constant output node 5140a. That is, the switch circuits SW11 to SWm1 and SW12 to SWm
Even when all 2 are in a non-conductive state, a constant free-run current is always supplied to the output node.

The delay control circuit 5150 is connected to the output node 51
40a and an n-channel MOS transistor N31 having a drain connected to the ground potential GND and a source, an n-channel MOS transistor N32 having a source connected to the ground potential GND, and a gate connected to the gate of the n-channel MOS transistor N31. n-channel MOS transistor N
The drain and gate of the transistor 31 are connected, and a current mirror circuit is formed by the n-channel MOS transistors N31 and N32.

Delay control circuit 5150 further includes a p-channel MOS transistor having a source connected to power supply potential Vcc and a drain connected to the drain of n-channel MOS transistor N32.
Includes transistor P31. The gate of n-channel MOS transistor N32 is connected to the gates of n-channel MOS transistors N11 to N1n of delay circuit 5110, and these n-channel MOS transistors N11 to N1 are connected.
n channel MOS transistors N31 and N32 whose drain current flowing through n forms a current mirror circuit
Is controlled by the value of the current flowing through.

On the other hand, p-channel MOS transistor P3
1 is connected to the gates of the p-channel MOS transistors P11 to P1n in the delay circuit 5110.
Here, since the gate and the drain of the p-channel MOS transistor P31 are connected, the p-channel MOS
The transistors P31 and P11 form a current mirror circuit. Therefore, the drain current flowing through each of p-channel MOS transistors P11 to P1n is equal to the drain current flowing through p-channel MOS transistor P31, that is, n forming a current mirror circuit.
The drain current flowing through the channel MOS transistors N31 and N32 has the same value as the drain current.

Therefore, the inverter circuit Inv. 1 to Inv. n supplied to each output node 14 of the variable constant current source circuit 140.
It is controlled by the current value supplied to Oa.

Next, the operation of internal synchronization signal generation circuit 3000 will be briefly described. First, the external clock signal E
xt. Delay circuit 511 for one cycle time of CLK
Consider a case where the delay time of 0 is small. in this case,
External clock signal Ext. CLK and the delay circuit 5
The signal output from 110 is an external clock signal Ex
t. This means that the phase is advanced as compared with CLK. In accordance with the phase difference detected by the phase comparator 5120, the switch decoder 5130 controls the delay circuit 5110
The constant current source switch signal CS causes the variable constant current source circuit 51 to delay the advance of the phase of the signal output from the
40 is controlled to reduce the constant current value output to the output node 5140a. Accordingly, an n-channel MOS
The value of the drain current flowing through the current mirror circuit composed of transistors N31 and N32 decreases, and each inverter circuit Inv. i (i
= 1, 2, ... n) also decreases.

Therefore, the inverter circuit Inv. 1 to
Inv. n, the external clock signal Ex
t. Receiving CLK, the phase of the signal output from delay circuit 5110 is delayed.

That is, the external clock signal Ext. CL
The phase difference between the phase of K and the signal output from the delay circuit 5110 changes in a direction in which both are synchronized.

On the other hand, the delay time of delay circuit 5110 is equal to external clock signal Ext. When the period is longer than the time of one cycle of external clock signal Ext. CLK and internal clock signal int. CLK is synchronized.

[0021]

However, since the conventional internal synchronizing signal generation circuit 5000 is configured as described above, there are the following problems.

That is, the DLL circuit and the like can be used only after the external clock signal and the internal clock signal start to be synchronized. However, if the range that the delay control value can take is increased in order to increase the accuracy of the phase adjustment, there is a problem that the time until the synchronization operation is completed becomes longer.

In controlling the delay time of the DLL circuit or the like, the number of bits increases when the delay control value is held in, for example, a shift register, and the number of bits decreases when held in binary notation. However, there has been a problem that the number of decoding circuit elements increases and the speed decreases.

In the above, the DLL circuit has been described as an example, but as described above, the synchronous DRAM (SDRAM)
In a semiconductor memory device that operates in synchronization with an external clock signal as described above, a PLL circuit or a DLL circuit for generating an internal clock signal synchronized with the external clock signal may be mounted inside the semiconductor memory device. General.

In the DLL circuit, the phase of the external clock signal is made equal to the phase of the clock signal passed through the delay stage (hereinafter referred to as the internal clock signal). For that, DL
The L circuit uses a delay stage circuit and a delay stage control circuit whose delay amount can be controlled, and a phase comparator compares the phases of an external clock signal and an internal clock signal, and the result is given to the delay stage control circuit. It has become.

That is, the delay amount control circuit holds the current delay amount, and according to the comparison result of the phase comparator,
By increasing or decreasing the set value of the delay amount from the current delay amount, the phase of the internal clock signal is made closer to the external clock signal. With such a configuration, when the phases of the external clock signal and the internal clock signal become equal, no signal for increasing or decreasing the delay amount is output from the phase comparator. It becomes a so-called locked state.

On the other hand, in the PLL circuit, the phase of the external clock signal is made equal to the phase of the self-oscillating internal clock signal. In other words, a voltage-controlled oscillation circuit is used to generate the clock signal, the phase comparator compares the phases of the internal clock signal and the external clock signal, and adjusts the oscillation frequency of the voltage-controlled oscillation circuit according to the comparison result. by doing,
The configuration is such that both phases are matched.

Here, as the memory capacity of a chip becomes larger, the skew of a signal transmitted inside the chip, particularly, a clock signal for controlling the operation of the entire chip becomes larger, thereby limiting the operating frequency of the chip. .

In particular, when an externally input reference clock signal is received by a clock buffer and then address, data and command are received based on the clock signal, the received clock signal is transmitted to each address. , Data, and command input ends, and the delay required thereby limits chip performance.

At the same time, if the output buffer is controlled based on the clock at the time of data output, the output will be delayed by the amount of the clock skew, thus impairing the output data margin. In order to reduce the influence of such clock skew, DLL as described above is used.
A circuit is used.

Further, for example, in a chip test operation or the like, it is necessary to use a relatively low frequency external clock signal input to perform a high frequency operation inside the chip. For that purpose, a circuit for internally generating a high frequency is required. A circuit for generating such a high-frequency internal clock signal generally includes a PL
An L circuit is used. However, as described above, if the PLL circuit is further mounted on a chip on which the DLL circuit is mounted in order to reduce clock skew, there is a problem in that the area penalty increases accordingly.

The present invention has been made to solve the above problems, and an object of the present invention is to reduce the time until the completion of the synchronization operation even when the accuracy of the phase adjustment is increased. An object of the present invention is to provide a synchronous semiconductor memory device including a possible internal synchronous signal generating circuit.

Another object of the present invention is to provide an internal synchronization signal capable of suppressing an increase in the number of circuit elements and performing high-speed delay time control even when a delay control value expressed in a binary number is used for controlling a delay amount of a delay circuit. An object of the present invention is to provide a synchronous semiconductor memory device including a generating circuit.

Still another object of the present invention is to provide an internal clock capable of generating an internal clock signal synchronized with an external clock signal and an internal clock signal having a higher frequency than the external clock signal while suppressing an increase in chip area. An object of the present invention is to provide a synchronous semiconductor memory device including a synchronous signal generating circuit.

[0035]

According to a first aspect of the present invention, a synchronous semiconductor memory device receives an address signal and a control signal from outside in synchronization with an external clock signal, and sends and receives storage data to and from the outside. A synchronous semiconductor memory device,
A memory cell array having a plurality of memory cells arranged in a matrix, a control circuit controlling operation of the synchronous semiconductor memory device in accordance with a control signal, and selecting a memory cell in accordance with an address signal; A cell selection circuit that exchanges storage data with the memory cell; and an internal synchronization signal generation circuit that outputs an internal clock signal synchronized with the external clock signal. A variable delay circuit having a plurality of serially connected internal delay circuits for delaying, selectively receiving an inverted signal of an output from a predetermined internal delay circuit of the plurality of internal delay circuits and an external clock signal, and selectively receiving A first switching circuit provided to a variable delay circuit, an output signal from a predetermined internal delay circuit and an output from the variable delay circuit are received and selectively output as an internal clock signal. A second switching circuit, a phase comparison circuit that compares the phase of a signal corresponding to the signal transmitted through the variable delay circuit with an external clock signal, and a phase variable circuit that synchronizes the phases according to the comparison result of the phase comparison circuit. And a phase control circuit for controlling a delay amount of the delay circuit, and the cell selection circuit operates in synchronization with the internal clock signal.

According to a second aspect of the present invention, there is provided a synchronous semiconductor memory device comprising:
In addition to the configuration of the synchronous semiconductor memory device according to claim 1,
A frequency divider that receives an output of a predetermined internal delay circuit and divides the frequency by a predetermined frequency division ratio; and receives an output signal of the frequency divider and an output signal of the variable delay circuit, and selectively outputs one of them. A third switching circuit, wherein the phase comparison circuit compares the phase of the output signal of the third switching circuit with the phase of the external clock signal.

The synchronous semiconductor memory device according to claim 3 is
In addition to the configuration of the synchronous semiconductor memory device according to claim 1 or 2, the variable delay circuits are connected in series with each other.
It includes m (m: natural number) internal delay circuits, and the predetermined internal delay circuit is the m-th internal delay circuit.

The synchronous semiconductor memory device according to claim 4 is
In addition to the configuration of the synchronous semiconductor memory device according to claim 1,
The phase control circuit is configured to update a delay amount held in accordance with an output from the phase comparison circuit, and to control a delay time of the variable delay circuit in accordance with the delay amount held in the storage circuit. And a control circuit.

The synchronous semiconductor memory device according to claim 5 is
In addition to the configuration of the synchronous semiconductor memory device according to claim 1,
The phase control circuit further includes a delay detection circuit that detects a delay amount of the external clock signal in the variable delay circuit, determines an initial value of the delay amount, and provides the delay value to the storage circuit. And a first selection circuit that receives the external clock signal and selectively supplies a test signal for one cycle of the external clock signal to the variable delay circuit under the control of the detection control circuit; A delay measuring circuit that detects which of the plurality of internal delay circuits has propagated during a predetermined time and determines an initial value of the delay amount, and is provided between the comparing circuit and the storage circuit; A second selection circuit which receives the output and the output of the delay detection circuit and selectively supplies any one of them to the storage circuit under the control of the detection control circuit.

The synchronous semiconductor memory device according to claim 6 is
In addition to the configuration of the synchronous semiconductor memory device according to claim 4,
The delay control circuit includes a variable constant current circuit that generates a control current according to the delay amount held in the storage circuit, and the variable constant current circuit sets a predetermined current value to I and sets j and k to natural numbers. , A plurality of first constant current sources, and a j-th first constant current source among the first constant current sources generates a current of 2 ^j−1 × I, and a plurality of second constant current sources. A current source, wherein a k-th second constant current source among the second constant current sources generates a current of I / 2 ^k , and according to a delay amount held in the storage circuit,
A current synthesizing circuit for selectively synthesizing a current from the first constant current source and a current from the second constant current source to generate a control current, wherein a delay time of the variable delay circuit is a control current value It is controlled according to.

The synchronous semiconductor memory device according to claim 7 is
In addition to the configuration of the synchronous semiconductor memory device according to claim 6,
Each internal delay circuit includes a plurality of serially connected buffer circuits whose signal delay time changes according to the operating current value,
The delay control circuit further includes a voltage generation circuit that converts the control current value to a reference voltage that controls an operation current value of the buffer circuit.

The synchronous semiconductor memory device according to claim 8 is
In addition to the configuration of the synchronous semiconductor memory device according to claim 6,
The phase comparison circuit includes a first internal node to which a reference clock signal is applied, a second internal node to which a clock signal to be compared is applied, and a comparison circuit that compares signals from the first and second internal nodes. Receiving an output signal of the third switching circuit and an external clock signal, applying a signal of a predetermined level to a first internal node, and applying an external clock signal to a second internal node; And an input control means for switching between a second state in which an external clock signal is supplied to the internal node and an output signal of the third switching circuit is supplied to the second internal node.

[0043]

FIG. 1 is a schematic block diagram showing a configuration of a synchronous semiconductor memory device 1000 according to an embodiment of the present invention.

Referring to FIG. 1, synchronous semiconductor memory device 1
000 is an external clock signal Ext. A control circuit 20 generates internal control signals in response to CLK and external control signals / RAS, / CAS, / W, / CS, and the like, and a memory cell array 100 in which memory cells are arranged in a matrix.

As shown in FIG. 1, the memory cell array 100 has a total of 16 memory cell blocks 100a to 100a.
00p. For example, when the storage capacity of the synchronous semiconductor memory device 1000 is 1 Gbit,
Each memory cell block has a capacity of 64 Mbits.
Each block is configured to operate independently as a bank.

External address signals A0 to Ai applied through address signal input terminal group 12 are supplied to address buses 50a and 50a under the control of control circuit 20.
b to the address driver 52. The address signal is transmitted from the address driver 52 to each memory cell block via the address bus 50c.

Synchronous semiconductor memory device 1000 is further provided for each pair of memory cell blocks, and under the control of control circuit 20, latches and predecodes a row address transmitted by address bus 50c. A row predecoder 36, a row decoder 44 for selecting a corresponding row (word line) of a memory cell block selected based on an output from the row predecoder 36, and a control circuit 20 provided for each memory cell block Under the control of the predecoder 3 which latches and predecodes the column address transmitted by the address bus 50c.
4 and a column predecoder 40 for further predecoding the column address based on the output from the predecoder 34.
And a column decoder 42 for selecting a corresponding column (bit line pair) of the selected memory cell block based on an output from column predecoder 40.

Synchronous semiconductor memory device 1000 further includes a region along the long side of the central portion of the chip, outside the region where external control signal input terminal group 10 and address signal input terminal group 12 are provided. Data input / output terminals DQ0 to DQ15 and DQ16 to DQ
31 and input / output buffer circuits 14a to 14f provided corresponding to data input / output terminals DQ0 to DQ31, respectively.
And a data bus 54 for transmitting data between the input / output buffer and the corresponding memory cell block, and a data bus 54 and a selected memory cell column provided corresponding to the memory cell blocks 100a to 100p, respectively. And a read / write amplifier 38 for exchanging data between them.

Signal / RAS applied to external control signal input terminal group 10 is a row address strobe signal for starting an internal operation of the semiconductor memory device and determining an active period of the internal operation. In response to activation of signal / RAS, circuits related to the operation of selecting a row of memory cell array 100, such as row decoder 44, are activated. Signal / CAS applied to external control signal input terminal group 10
Is a column address strobe signal, which activates a circuit for selecting a column in the memory cell array 100.

Signal / CS applied to external control signal input terminal group 10 is a chip select signal indicating that synchronous semiconductor memory device 1000 is selected.
W is a signal instructing a write operation of the synchronous semiconductor memory device 1000.

Synchronous semiconductor memory device 1000 further includes an external clock signal Ext. CLK, the synchronous operation is started under the control of the control circuit 20, and the internal clock signal i
nt. CLK1 and the internal clock signal int. CLK
2 to output an internal synchronization signal 2018.

Signal / CS, signal / RAS, signal / CAS
And the operation of taking in signal / W is performed according to internal clock signal in.
t. This is performed in synchronization with CLK1.

The operation of taking in an address signal applied to the address signal input terminal group 12 and the data input / output terminal D
Data transmission and reception via the internal clock signal int. This is performed in synchronization with CLK1.

The internal circuits of the synchronous semiconductor memory device 1000, for example, the row decoder 44 and the column decoder 42
The operation of internal clock signal int. This is performed in synchronization with CLK2.

When the address signal corresponds to the defective bit column address held in advance, the redundant column selection circuit 30 selects a redundant column, and the redundant row selection circuit 32 selects the defective column address stored in the address signal in advance. If so, a redundant row is selected.

[Details of Configuration of Internal Synchronization Signal Generation Circuit 2018] FIG. 2 is a schematic block diagram showing a configuration of internal synchronization signal generation circuit 2018 according to the first embodiment of the present invention.

The clock generation circuit 2100 outputs the control signal T
According to MDLPL, external clock signal Ext. CLK
Receiving the external clock signal Ext. CLK, which operates as a DLL circuit that generates an internal clock signal synchronized with the external clock signal ext. CLK and the external clock signal ext. An operation mode for generating an internal clock signal having a frequency obtained by multiplying CLK is switched.

That is, the clock generation circuit 2100 outputs the external clock signal Ext. A clock signal RFCKO having the same cycle as CLK is output. In the operation mode as the DLL circuit, the clock generation circuit 2100 outputs the external clock signal Ext. CL
A signal DPC having the same period as K and synchronized therewith
Outputs KO.

Further, the clock generation circuit 2100
In the mode operating as the L circuit, the signal RFCK
O is the external clock signal ext. CLK is the same as that of the mode that operates as the DLL circuit in that the signal has the same cycle as CLK and is synchronized with the signal.
Is the external clock signal ext. A signal having a frequency obtained by multiplying CLK is output.

The multiplexer 2186 outputs the external clock signal ext. CLK and signal DPCKO, and receives either one of them as an internal clock signal int. For controlling an internal circuit of the SDRAM, for example, a circuit operation for performing a row selecting operation or a column selecting operation. CLK2.

On the other hand, the multiplexer 2220 outputs the signal R
FCKO and the external clock signal Ext. CLK, and selectively outputs one of them.

Clock tree 168 receives an output from multiplexer 2190 and receives, for example, an internal clock signal int. For controlling the operation of an address input buffer provided corresponding to an address signal input terminal. C
LK1 is output.

As will be described later, the output signal from clock tree 168 is applied to clock generation circuit 2100. Clock generation circuit 2100 receives input signal RFCK from clock tree 168 and external clock signal Ext. A synchronous operation with CLK is performed.

Here, for example, SDRAM 1000
In the case where the chip operates at such a low frequency that the skew of the clock signal in the chip does not matter, for example, the second internal clock signal i for controlling the operation of the internal circuit is provided.
nt. CLK2 as the external clock signal Ext. CL
K is supplied to the internal circuit as it is via multiplexer 2186, while clock signal int.K supplied to an input / output buffer provided corresponding to control signal input terminal group 10 for receiving a control signal. CLK1 as the external clock signal Ext. CLK is output as it is via the multiplexer 2220.

On the other hand, as will be described later, the SDRAM 1
000 is high and the skew of the internal clock signal inside the chip becomes a problem, the first internal clock signal int. CLK1 and the second internal clock signal int. CLK2, the clock generation circuit 2100
From the external clock signal Ext. A signal synchronized with CLK is used.

FIG. 3 shows the first internal clock signal int.
CLK1 to input terminals in the external control signal input terminal group 10 (hereinafter referred to as a clock tree 16).
FIG. 8).

Referring to FIG. 3, an external clock signal Ext. CLK and its complementary signal / ext. CLK corresponds to the buffer circuit 15
0 and 152, the internal synchronization signal generation circuit 201
8 given.

Internal clock signal int. CLK1 is first supplied to the buffer circuit 70.

The output of the buffer circuit 70 is sequentially divided into two, and finally divided into eight clock signals. This 8
The two clock signals are applied to wirings 78a to 78h, respectively. External control signals are taken in from external control signal input terminal group 10 in synchronization with clock signals supplied from respective ends of wirings 78a to 78h. Here, each of the buffer circuits 70 to 78h is configured by, for example, a two-stage inverter.

The clock signal from the end of the wiring 78h is
It is provided to external synchronization signal generation circuit 2018 via replica buffer circuit 62 and delay adjustment circuit 64.

Internal synchronization signal generation circuit 2018 outputs an output from delay adjustment circuit 64 and an external clock signal Ext. CLK in synchronization with the first internal clock signal int. CLK1 is generated.

Here, assuming that delay adjustment circuit 64 does not exist, buffer circuit 150 and replica buffer circuit 62 have the same configuration, so that external clock signal ext. CLK
And wiring 78h provided to replica buffer circuit 62
It will be adjusted so that the phase with the clock signal above becomes equal. Here, the phases of the clock signal on the wiring 78h and the clock signals on the other wirings 78a to 78g are also equal.

That is, the operation of taking in the external control signal is performed by the external clock signal ext. This is performed in synchronization with CLK.

Further, in FIG. 3, internal clock signal int. CLK
Although the configuration of the distribution of 1 is described, a similar configuration is provided corresponding to, for example, the address signal input terminal group 12. With such a configuration, the capture of the address signal can be performed by the external clock signal ext. This is performed in synchronization with CLK.

FIG. 4 is a schematic block diagram for describing in more detail the configuration of internal synchronization signal generation circuit 2018 and clock tree 168 shown in FIG.

The synchronization signal generation circuit 2018 receives the output from the differential amplifier 150 and the output from the delay adjustment circuit 64, and compares the output from the phase adjustment circuit 120 with the output from the phase adjustment circuit 120. Variable delay circuit 1
And a phase control circuit 2800 that controls ten delay amounts.

Here, variable delay circuit 110 includes a plurality of stages of delay circuits connected in series with each other, each delay time being controlled by a delay control signal from phase control circuit 2800.

When the internal synchronization signal generation circuit 2018 operates as a DLL circuit, the internal synchronization signal generation circuit 2018 further provides the output from the differential amplifier 150 to the variable delay circuit 110, and the internal synchronization signal generation circuit 2018
Operates as a PLL circuit, the variable delay circuit 1
A multiplexer 2310 for providing an inverted signal of an output signal from an intermediate point of a plurality of stages of delay circuits included in the variable delay circuit 110 as an input to the variable delay circuit 110, and a multiplexer 210 for operating as a DLL circuit.
186, and when operating as a PLL circuit, a multiplexer 2320 that provides an output from a central delay circuit to a multiplexer 2186 among a plurality of delay circuits included in the variable delay circuit 110.

Frequency dividing section 2300 receives an output from a central delay circuit among a plurality of delay circuits included in variable delay circuit 110, and outputs a signal divided by a predetermined frequency dividing ratio.

The multiplexer 2410 includes a frequency divider 230
In response to the output of 0 and the output of the variable delay circuit 110, one of them is selectively output.

The multiplexer 2220 is connected to the differential amplifier 1
50 and the output from multiplexer 2410, and selectively receives one of internal clock signals int. CLK1.

The multiplexer 2186 is connected to the differential amplifier 1
50 and the output of the multiplexer 2320, one of the clock drivers 2154 is selectively selected.
Give to.

That is, in the configuration shown in FIG. 4, internal synchronizing signal generation circuit 2018 generates internal clock signal int. CLK
1 and a second internal clock signal int. CLK2 is supplied.

In a high-speed operation mode (eg, a test operation mode), the internal synchronization signal generation circuit 20
18 changes from the DLL operation mode to the PLL operation mode, the internal synchronization signal generation circuit 2018 is hereinafter referred to as a DPLL circuit.

In the high-speed operation mode, the magnification of multiplying the frequency of the clock input from the outside by an integer is not particularly limited, but is, for example, 2 or 4 times.

The operation of taking in the address signal and the external control signal is performed according to the internal clock signal int. It is assumed to be performed at the rising edge of CLK1.

Note that the internal synchronizing signal generation circuit 2018
In a mode operating as a DLL circuit, the output signal int. CLK1 may be used to control the input / output of data. In the high-speed operation mode, the multiplication factor for multiplying the frequency of the clock input from the outside by an integer is:
It is also possible to make it 8 times, 16 times or more.

In the following, the internal synchronizing signal generation circuit 2018
Will be briefly described.

The output of variable delay circuit 110 is distributed to internal circuits by clock driver 2154. Alternatively, the external clock signal Ext. CLK is output to multiplexer 218
6 and the driving force is increased by the clock driver 2154 and distributed to the internal circuit system as a reference signal for the control signal.

The output of the differential amplifier 150 is selected by the multiplexer 2310, and
0 is input as a trigger signal.

In normal operation, variable delay circuit 110
Are preferentially provided to clock tree 168 by multiplexers 2410 and 2220.

The clock signal whose driving force has been increased by the driver circuit 191 via the multiplexer 2220 is distributed to the external control signal input terminal group 10 via the clock tree 168. The internal clock signal int. The phase of CLK1 is controlled to be substantially the same for any external control signal input terminal.

The clock signal that has passed through the clock tree 168 is input to the phase comparator 120 via the replica buffer 62 of the input buffer for the clock signal.

In phase comparator 120, internal clock signal int. CLK1 is compared with the phase of the external clock signal from differential amplifier 150.

Next, the operation in the high-speed operation mode will be described. In this case, the variable delay circuit 110 has an output from the delay circuit having a half of the total delay amount selected by the multiplexer 2310 and supplied to the input of the variable delay circuit 110 instead of the external clock signal. Therefore, the variable delay circuit 110 forms a closed loop.

Here, the multiplexer 2310 includes a circuit for one stage of the inverter in the path selected in the high-speed operation mode.
Due to the presence of 2, the delay stage included in the loop constituted by the variable delay circuit and the inverter circuit 2202 is configured to be an odd number stage. Therefore, this loop forms a ring oscillator and starts free-running oscillation.

In the above configuration, the variable delay circuit 110
The reason why the output from the half of the total delay amount is taken out is to make the delay amount for one cycle of the ring oscillator equal to the delay amount of the variable delay circuit 110. The output of this ring oscillator passes through the frequency divider 2300 and is reduced to a quarter frequency, and then selected by the multiplexers 2410 and 2220. Is distributed to The internal clock signal i supplied to the address signal input terminal group or the external control signal input terminal group
nt. Phase comparator 120 and phase control circuit 280 such that the phases of the cycles of CLK1 and the external clock signal match.
0 controls the delay amount of the variable delay circuit 110.

Therefore, in the state where the phases are matched, the output of the ring oscillator becomes the external clock signal ex.
t. It is four times the frequency of CLK.

This quadruple frequency internal clock signal in
t. CLK2 is selected by the multiplexer 2320 and the multiplexer 2186, and the clock driver 2
The driving force is increased by 154 and distributed as a control signal to the internal circuit system.

That is, in such an operation mode, external clock signal Ext. Even when the frequency of CLK is not high, the internal circuit itself can operate at high speed.

FIG. 5 shows the phase control circuit 280 shown in FIG.
0, multiplexer 2310 and variable delay circuit 110
FIG. 2 is a schematic block diagram for explaining the configuration of the first embodiment in more detail.

Second delay circuit 1 in variable delay circuit 110
The output of 10b is provided to multiplexer 2310,
In the operation mode for determining the initial delay control value, switching circuit 2200 in multiplexer 2310 outputs external clock signal Ext. Either CLK or the ground potential is controlled by the control circuit 2190 and selectively output. On the other hand, in the PLL operation mode, switching circuit 2200 selectively provides the output of inverter 2202 receiving the output from delay circuit 100b to delay circuit 110a in variable delay 110.

The multiplexer circuit 2320 is controlled by the control circuit 2190 to output the output from the variable delay circuit 110 in the DLL operation mode and the output from the delay circuit 110b in the variable delay circuit 110 in the PLL operation mode. Outputs each selectively.

In the PLL operation mode, the output signal from the frequency divider having a predetermined frequency division ratio among the frequency dividers 2302 and 2304 in the frequency divider 2300 is
The signal is selected and output by the multiplexer 2310.
Here, in FIG. 5, the frequency divider 2302 has a frequency division ratio of 2
The frequency divider 2304 is a frequency divider having a frequency division ratio of 4.

In the DLL operation mode, multiplexer 2410 outputs the output from variable delay circuit 110 to internal clock signal int. CLK1. In the PLL operation mode, the multiplexer 2410 outputs the divided signal output from the multiplexer 2310 to the internal clock signal int. CLK1.

That is, even in the DLL operation mode,
Also in the PLL operation mode, the external clock signal ext. CLK compared with the internal clock signal int. CLK1 is the external clock signal ext. CLK has the same cycle as CLK. In the PLL operation mode, the clock signal output from the delay circuit 110b and not divided is supplied to the multiplexer 2320.
And the second internal clock signal int. C
It will be output as LK2.

FIG. 6 is a flow chart for explaining the operation of internal synchronization signal generating circuit 2018 shown in FIG.

Referring to FIG. 6, first, the operation of internal synchronization signal generation circuit 2018 is started (step S20).
0), the delay control value held in the delay control value holding circuit 170 is controlled by the control circuit 2190 to set the delay control value to a maximum value, that is, a value that minimizes the delay amount. Subsequently, the control circuit 2190 controls the multiplexer 2310 to supply a signal of the ground potential level to the variable delay circuit 110, and clears the signal level in the variable delay circuit 110 (Step S202).

Next, the delay control value held in the delay control value holding circuit 170 is controlled by the control circuit 2190 to set the delay control value to a minimum value, that is, a value for maximizing the delay amount (step). S204).

The control circuit 2190 includes the multiplexer 23
10 to the variable delay circuit 110 to control the external clock signal Ext. CLK is input as a test signal for one pulse (step S206).

The initial delay control value determination circuit 160 receives the external clock signal Ext. During one cycle of CLK, it is detected which of the delay circuits 110a to 110d the test signal has been transmitted to (step S208).

Subsequently, the initial delay control value determination circuit 160
Determines the initial value of the delay control value from the value detected in step S208 during the DLL operation. On the other hand, PL
During the L operation, the initial value of the delay control value is determined to be a predetermined fixed value (step S210).

Subsequently, the control circuit 2190 controls the multiplexer 210 to cause the delay control value holding circuit 170 to store the determined initial value during delay control (step S).
212).

After that, the control circuit 2190 controls the multiplexer 210 and the multiplexer 2310,
An external clock signal is supplied to the variable delay circuit 110 during the DLL operation, and a signal obtained by inverting a signal fed back from the center of the variable delay circuit 110 is supplied to the input section of the variable delay circuit 110 during the PLL operation.

After the above settings are made, control circuit 2190 gives the output of shift logic circuit 180 to delay control value holding circuit 170. Thus, in the DLL operation mode, the variable delay circuit 110 and the phase comparator 12
0, the shift logic circuit 180, and the delay control value holding circuit 1
70, a variable constant current circuit 140, and a voltage generation circuit 150
The internal clock signal int. CLK1 and the external clock signal Ext. Phase matching control with CLK is performed (step S214).

On the other hand, in the PLL operation mode, a ring oscillator constituted by delay circuits 110a and 110b in variable delay circuit 110 and an inverter 2202 in multiplexer 2310, and a phase comparator 120
, Shift logic circuit 180, delay control value holding circuit 17
0, the variable constant current circuit 140, and the voltage generation circuit 150
And a frequency-divided unit 2300, and a phase-locked loop circuit configured by the frequency-divider 2300 and the external clock signal Ext. Phase matching control with CLK is performed (step S214).

FIG. 7 is a timing chart for explaining the DLL operation of internal synchronization signal generation circuit 2018 shown in FIG. 5 in more detail.

Referring to FIGS. 5, 6 and 7, first, at time t0, signal TMDLPL applied from control circuit 20 to internal synchronizing signal generation circuit 2018 changes to "
When the signal goes low, the DLL operation is designated.
This signal indicates which of the L operations is to be selected.

Subsequently, at time t1, reset signal MRSTC from control circuit 20 is activated ("").
L ”level), and accordingly, the signal FDRST output from the control circuit 2190 becomes“ H ”level, and the signal FT
RSTC attains an active state ("L" level). Signal FT
In response to the RSTC being in the active state, bit0 to bit7 of the bit data in the binary notation of the delay control value held in the delay control value holding circuit 170 are all “H” levels corresponding to the level of the signal FDRST. Becomes That is, the delay control value is reset to the maximum value. At this time, the multiplexer 2310 has selected the signal of the ground potential level, and the signal level in the variable delay circuit 110 is reset.

Subsequently, at time t2, external clock signal Ext. In response to the rise of CLK, the signal FD
RST becomes “L” level. In response, the signal FT
Since the RSTC level maintains the “L” level, the delay control values bit0 to bit7 are all “L”.
Reset to level. That is, the delay control value is reset to the minimum value. At time t3, signal FTRS
TC returns to "H" level.

During a period from time t3 to time t4, internal synchronization signal generating circuit 2018 is in a standby state. External clock signal Ext. At time t4. In response to the fall of CLK, the signal FFRSTC becomes “H”, and the state of the initial delay control value determination circuit 160 is reset. At the same time, the signal FDLS
TP attains an active state (“H” level), and the multiplexer 2310 outputs the external clock signal Ext. CLK is passed.

External clock signal Ex at time t5
t. In response to the rise of the external clock signal Ext.CLK, the initial delay control value determination circuit 160 detects the propagation of the test signal in the variable delay circuit 110. The time corresponding to one cycle of CLK starts.

External clock signal Ex at time t6
t. In response to the fall of CLK, signal FDLSTP attains an inactive state ("L" level), and multiplexer 23
Reference numeral 10 indicates a state in which a signal of the ground level is selected again. That is, the external clock signal Ex during the period from time t5 to t6
t. CLK is used as a test signal by the multiplexer 23
10, and is provided to the variable delay circuit 110.

External clock signal Ex at time t7
t. At the time of falling of CLK, initial delay control value determination circuit 160 controls delay circuits 110 a to 110 a in variable delay circuit 110.
To which of 110d the test signal has been transmitted is detected.

At time t7, as signal FTLAT attains an active state ("H" level), the initial value of the delay control value determined by initial delay control value determination circuit 160 is delayed by multiplexer 210 via multiplexer 210. Control value holding circuit 17
0 is stored.

When signal FDLSTP is activated, switching circuit 2200 outputs external clock signal Ext. CLK at the time of selecting and passing external clock signal Ext. In response to the rise of CLK, signal FPFD attains an active state (“H” level).
It is in a state to select the output from 80.

That is, a delay locked loop composed of the variable delay circuit 110, the phase comparison circuit 120, the shift logic circuit 180, the delay control value holding circuit 170, the variable constant current circuit 140, and the voltage generation circuit 150 The internal clock signal int. CLK and the external clock signal Ext. Phase adjustment control with CLK is performed.

FIG. 8 is a timing chart for explaining the PLL operation of internal synchronization signal generation circuit 2018 shown in FIG. 5 in more detail.

Referring to FIGS. 5, 6 and 8, first, at time t0, signal TMDLPL applied from control circuit 20 to internal synchronizing signal generating circuit 2018 changes to "".
When the level becomes “H” level, the PLL operation is specified.

Subsequently, at time t1, reset signal MRSTC from control circuit 20 is activated ("").
L ”level), and accordingly, the signal FDRST output from the control circuit 2190 becomes“ H ”level, and the signal FT
RSTC attains an active state ("L" level). Signal FT
In response to the RSTC being in the active state, bit0 to bit7 of the bit data in the binary notation of the delay control value held in the delay control value holding circuit 170 are all “H” levels corresponding to the level of the signal FDRST. Becomes That is, the delay control value is reset to the maximum value. At this time, the multiplexer 2310 has selected the signal of the ground potential level, and the signal level in the variable delay circuit 110 is reset.

Subsequently, the operation during the period from time t2 to time t8 is the same as during the DLL operation. However. In the PLL operation, fixed data is substituted into the delay control value holding circuit 170 as initial data.
It has nothing to do with L operation.

At time t7 to t8, signal FTLAT is
Becomes active ("H" level), the initial value of the delay control value is stored in the delay control value holding circuit 170.

When signal FDLSTP is activated, switching circuit 2200 outputs external clock signal Ext. CLK at the time of selecting and passing external clock signal Ext. In response to the rise of CLK, signal FPFD attains an active state (“H” level).
It is in a state to select the output from 80.

That is, the variable delay circuits 110a and 110b
, A multiplexer 2310, a frequency divider 2300, a phase comparator circuit 120, a shift logic circuit 180, a delay control value holding circuit 170, a variable constant current circuit 140, and a voltage generation circuit 150. The internal clock signal int. CLK and the external clock signal Ext. Phase adjustment control with CLK is performed.

[Principle of Switching Between DLL Operation and PLL Operation] Hereinafter, clock generation circuit 2100 shown in FIG.
However, the principle of operating by switching between the DLL operation mode and the PLL operation mode will be briefly described.

FIG. 9 is a conceptual diagram schematically showing the operation of the variable delay circuit 110 in the clock generation circuit 2100.
In FIG. 9, the signal SRCCLK is
0, and is output as a signal DSTCLK after being delayed by a predetermined delay time τd.

FIG. 10 is a timing chart showing the relationship between input signal SRCCLK and output signal DSTCLK described in FIG. That is, at time t0, the rising edge of signal SRCCLK input to variable delay circuit 110 is output as the rising edge of signal DSTCLK at time t1 delayed by time τd from time t0.

At this time, the variable delay circuit 11 is controlled so that the time of one cycle of the signal SRCCLK matches the delay time τd.
0 is controlled, the signal SRCCLK and the signal DST
CLK, and a circuit including the variable delay circuit 110 is
It will operate as a DLL circuit.

FIG. 11 is a schematic block diagram showing an example of the configuration of a ring oscillator including variable delay circuit 110.

That is, the output signal DSTCLK of the variable delay circuit 110 is inverted by the inverter 2201.
It is provided to variable delay circuit 110 as input signal SRCCLK.

With this configuration, a ring oscillator that performs free-running oscillation is formed. FIG. 12 is a timing chart for explaining the operation of such a ring oscillator. It is assumed that variable delay circuit 110 is set to have the same delay time τd as described with reference to FIG. Further, assuming that the delay time of the signal in the inverter 2201 is ignored compared to the delay time τd in the variable delay circuit 110, at time t0, the signal S
In response to the rise of RCCLK, at time t1 after elapse of time τd from time t0, signal DST
CLK rises, and a signal obtained by inverting the rising signal DSTCLK is supplied to the input of the variable delay circuit 110 as a signal SRCCLK.

That is, as compared with the case where the clock signal given from outside is received as signal SRCCLK in FIG. 10 and delayed by time τd and output as signal DSTCLK, in FIG.
The period of K is doubled. This is the variable delay circuit 1
This is because a signal for one cycle is generated by passing the signal twice through 10.

Therefore, in the case of the configuration as shown in FIG. 11, when the operation mode is changed from the DLL operation mode to the PLL operation mode, the external clock signal Ext. In order to maintain the synchronization state with CLK, the delay amount of the variable delay circuit 110 is set to about 1
/ 2 must be adjusted. This means that, for example, the time required to change from the DLL operation mode to the PLL operation mode until the synchronous state is established increases, or the scale of the circuit controlling the variable delay circuit 110 needs to be increased. Means

FIG. 13 is a schematic block diagram showing another example of the configuration of the ring oscillator including variable delay circuit 110.

In the configuration shown in FIG. 13, inverter 2202 receives output signal DSTCLK from the center of variable delay circuit 110, and applies an inverted signal to the input of variable delay circuit 110. That is, the inverter 2202
Is a signal delayed by the delay time τd / 2 with respect to the input signal SRCCLK, where τd is the delay time of the entire variable delay circuit 110.

FIG. 14 is a timing chart for explaining the operation of the ring oscillator having the configuration shown in FIG.

In contrast to the operation described with reference to FIG. 12, a signal delayed by delay time τd / 2 from input signal SRCCLK is used as an input signal to variable delay circuit 110. Even if the delay time of the entire variable delay circuit 110 remains τd, the cycle of the output signal DSTCLK is the same as that in the DLL operation mode described with reference to FIG.

FIG. 15 is a schematic block diagram showing a configuration for enabling operation by switching between the configuration in the DLL operation mode described in FIG. 9 and the configuration in the PLL operation mode described in FIG.

As inputs to the variable delay circuit 110, a multiplexer 200 for switching between an external signal SRCCLK and a signal obtained by inverting a signal from the center of the variable delay circuit 110 by an inverter 2202, and providing the same. A multiplexer 2320 is provided for switching between an output signal and a signal from the center of the variable delay circuit 110 and outputting the signal as a signal DSTCLK. Such a configuration corresponds to the first embodiment shown in FIGS.
Of the variable delay circuit 110 of the clock generation circuit 2100 of FIG.

Even when operating as a DLL circuit, PL
Even when operating as an L circuit. Variable delay circuit 110,
Since the phase comparison circuit 120, the shift logic circuit 180, the delay control value holding circuit 170, the voltage generation circuit 150, and the like can be commonly used, an increase in chip area can be suppressed.

[Details of Configuration of Internal Synchronous Signal Generating Circuit 2018] The following describes the internal synchronous signal generating circuit 20 shown in FIG.
18 describes a more detailed configuration for realizing the operation as shown in FIGS. 7 and 8.

FIG. 16 is a schematic block diagram for describing the configuration of variable constant current circuit 140 in more detail.

The variable constant current circuit 140 has a base current Ib
And a current generation circuit 1400 that generates a current of 2 ^j−1 × I and a current of I / 2 ^k (j, k: predetermined natural numbers) with respect to the reference current value I, and delay control According to the delay control value from the value holding circuit 170, the current generation circuit 1
And a current synthesizing circuit 143 for synthesizing the current from 400.

The current generation circuit 1400 generates a current of 2 ^j−1 × I and a current of I / 2 ^k based on the reference current I and a reference current generation circuit 141 for generating a reference current value I. Constant current cell group 1 having a plurality of constant current source cells
42.

According to the output from the current synthesizing circuit 143,
The voltage generation circuit 150 includes a reference voltage Vrp and a reference voltage Vr
n. The delay circuits 110a to 110d transmit signals with a delay time according to the values of the reference voltages Vrp and Vrn.

FIG. 17 is a circuit diagram for describing a configuration of reference current generating circuit 141 and constant current source cell group 142. Referring to FIG.

The reference current generation circuit 141 operates at the power supply voltage Vc
a P-channel MOS transistor P1, a P-channel MOS transistor P2, and an N-channel MOS transistor N1 connected in series between c and the ground potential Vss.
The gates of P-channel MOS transistors P1 and P2 receive the ground potential, and these transistors operate as a constant current source.

The gate of N-channel MOS transistor N1 is connected to an N-channel MOS transistor and a P-channel MOS transistor.
It is connected to the drain of an N-channel MOS transistor N1, which is a connection node with the S transistor P2.

The source / drain current flowing through N channel MOS transistor N1 corresponds to reference current I.

Of the constant current source cells included in constant current source cell group 142, constant current source cell 1422 outputting current I
Are P-channel MOS transistors P11 and N connected in series between power supply voltage Vcc and ground potential Vss.
Channel MOS transistor N11 and P-channel MOS transistor P12 receiving power supply potential Vcc at its source
And The gate of P-channel MOS transistor P11 and the gate of P12 are connected, and the gate and drain of P-channel MOS transistor P11 are connected. Thereby, P-channel MOS transistor P11
And P12 operate as a pair as a current mirror circuit.

Since the gate of N channel MOS transistor N1 and the gate of N channel MOS transistor N11 are connected, N channel MOS transistor N1
And N11, the same current I flows. That is, the current I also flows through the current mirror circuit including the P-channel MOS transistors P11 and P12, and the current I is output from the constant current source cell 1422.

Of the constant current source cells included in constant current source cell group 142, constant current source cell 1424 outputting current 2I
Are P-channel MOS transistors P21 and N connected in series between power supply voltage Vcc and ground potential Vss.
Channel MOS transistor N21 and P-channel MO
N-channel MOS transistor N22 connected in parallel with N-channel MOS transistor N21 between S transistor P21 and ground potential Vss, and P-channel MOS transistor P22 having a source receiving power supply potential Vcc. The gate of P-channel MOS transistor P21 and the gate of P22 are connected, and the gate and drain of P-channel MOS transistor P21 are connected. Thereby, P-channel MOS transistor P21
And P22 also operate as a pair as a current mirror circuit.

The gate of N-channel MOS transistor N1 and N-channel MOS transistors N21 and N22
The same current I flows through the N-channel MOS transistors N1, N21 and N22. That is, the P-channel MOS transistor P21
And a current mirror circuit P22, the current 2I
Flows, and this current 2I is supplied to the constant current source cell 14.
24.

Of the constant current source cells included in constant current source cell group 142, constant current source cell 142 outputting current I / 2
6, a P-channel MOS transistor P31 and an N-channel MOS transistor N31 connected in series between the power supply voltage Vcc and the ground potential Vss;
P connected in parallel with P-channel MOS transistor P31 between OS transistor P31 and power supply potential Vcc
Channel MOS transistor N32 and P-channel MOS transistor P33 receiving power supply potential Vcc at its source
And The gate of the P-channel MOS transistor P31, the gate of P32, and the gate of P33 are connected, and the gate and drain of the P-channel MOS transistor P31 are connected.

Since the gate of N channel MOS transistor N1 and the gate of N channel MOS transistor N31 are connected, N channel MOS transistor N
The same current I flows through 1 and N31. That is, the current I / 2 flows through the P-channel MOS transistors P31 and P32. Current I / 2 also flows through P channel MOS transistor P33, and current I /
2 is output from the constant current source cell 1426.

The other constant current source cells have the same basic configuration except that the number of P-channel transistors or N-channel MOS transistors connected in parallel is different depending on the output current value.

FIG. 18 is a schematic block diagram showing a configuration of current synthesizing circuit 143 and voltage generating circuit 150.

Current combining circuit 143 has N-channel MOS transistors N41 to N45 whose gate potentials are controlled in accordance with each bit value of the delay control value held in delay control value holding circuit 170 in binary notation. including. Each of N-channel MOS transistors N41 to N45 receives a current from a corresponding constant current source cell at its source, and has a drain connected to output node n1.

Although only five N-channel MOS transistors are shown in FIG. 18 and the other N-channel MOS transistors are omitted, actually, a number corresponding to the number of bits of the delay control value is provided.

Further, base current I is applied to output node n1.
An N-channel MOS transistor N51 for supplying b is also connected.

Voltage generation circuit 150 includes an N-channel MOS transistor N61 connected between output node n1 and ground potential Vss, power supply potential Vcc and ground potential Vss.
And a P-channel MOS transistor P61 and an N-channel MOS transistor N62 connected in series.

The gate of N-channel MOS transistor N61 and the gate of N62 are connected to form an N-channel MOS transistor.
The gate and the drain of the transistor N61 are connected. Thereby, N-channel MOS transistor N6
1 and N62 operate as a pair as a current mirror circuit.

That is, the same current value as that supplied to output node n1 is applied to N-channel MOS transistor N1.
62 and the P-channel MOS transistor P61.

The gate potential of P channel MOS transistor P61 is output as reference potential Vrp, and the gate potential of N channel MOS transistor N62 is changed to reference potential Vr.
output as n.

FIG. 19 is a block diagram showing a configuration of delay circuits 110a and 110b in variable delay circuit 110.

The delay circuit 110a includes four inverter rows Inv11 to Inv14.
It includes four inverter rows Inv21 to Inv24.

Output CKMD1 of delay circuit 110a and output CKMD2 of delay circuit 110b are applied to initial delay control value determination circuit 160.

Each of inverters Inv11 to Inv24 operates with an operation current corresponding to reference potentials Vrp and Vrn.

Delay circuit 110c and delay circuit 110d
Is also configured such that the signal output from each of them is the signal CKMD3
And the signal CKMD4, except that the delay circuit 11
0a and the configuration of the delay circuit 110b.

FIG. 20 is a circuit diagram of the inverter In shown in FIG.
It is a circuit diagram which shows the structure of v11. Inverter Inv1
Reference numeral 1 denotes P-channel MOS transistors P71 and P7 connected in series between a power supply potential Vcc and a ground potential Vss.
2, including N-channel MOS transistors N71 and N72.

The gate of P-channel MOS transistor P71 receives reference potential Vrp, and the gate of N-channel MOS transistor N72 receives reference potential Vrn.

The gate of P-channel MOS transistor P72 and the gate of N-channel MOS transistor N71 receive an input signal, and are connected to P-channel MOS transistor P72.
An output signal is output from a connection node between the transistor and N-channel MOS transistor N71.

That is, the operating current value of the inverter Inv11 is controlled by the values of the reference potentials Vrp and Vrn, and as the operating current value increases, the inverter Inv1
One delay time is reduced.

The configuration of other inverters Inv12 to Inv24 is the same. FIG. 21 is a schematic block diagram showing a configuration of the initial delay control value determination circuit 160.

Referring to FIG. 21, initial delay control value determination circuit 160 receives signal FFRST from detection control circuit 190.
C in response to the external clock signal Ext. C
LK count operation is started, the timing generation circuit 164 for controlling the timing of the signal FSCYC, and the signals CKMD1 to CKMD3 from the variable delay circuit 110 are received, and the signals CKMD1 to CKMD1 are received at the timing of the signal FSCYC.
A comparison logic circuit 166 for detecting which of CKMD3 is activated and outputting an initial delay control value;
Reset signal FSRST to timing generation circuit 164 in response to signal FPFD from detection control circuit 190
And a reset signal generation circuit 162 for outputting the same.

FIG. 22 is a block diagram showing a configuration of reset signal generation circuit 162. Reset signal generation circuit 1
62, inverters 1622 to 1634 connected to each other and receiving the signal FPFD;
Receiving as input the output of signal No. 4 and the signal FPFD
Circuit 1636.

That is, the reset signal generation circuit 162
Outputs a one-shot pulse having a pulse width determined by the delay time of the inverter trains 1622 to 1634 as the signal FSRST in response to the rising edge of the signal FPFD.

FIG. 23 is a block diagram showing a configuration of the timing generation circuit 164. Timing generation circuit 164
Is the external clock signal Ext. And an inverter 1642 that receives the clock signal CLK and generates an inverted signal thereof.
An inverter 1644 that receives the output of 42 and further inverts the output, and is set according to the signal FFRSTC. After the level of the signal FSCYC changes from “L” level to “H” level, it returns to “L” level again. The flip-flop circuit 1646 includes a flip-flop circuit 1646 that is reset in response to the reset operation and a counter 1648 that is reset in response to the activation (“H” level) of the signal FFRSTC and starts the count operation.

That is, referring to FIG. 7 and FIG. 23, at time t4, timing generation circuit 164 detects
The counting operation is started in response to the signal FFRSTC becoming “H” level, and the external clock signal Ext. The signal FSCYC is set to the “H” level in response to the rising edge of the CLK.

Subsequently, the timing generation circuit 164
External clock signal Ext. At time t7. In response to the rising edge of CLK, the signal FSCYC is set to "L".
And At this time, the output level of the flip-flop circuit 1646 is also reset.
C maintains the “L” level.

FIG. 24 is a schematic block diagram showing a configuration of comparison logic circuit 166. Referring to FIG. Each of the comparison logic circuits 166 is reset by the signal FFRSTC and the signal F
Comparators 1662 to 1668 receiving and holding the levels of corresponding signals CKMD1 to CKMD3 from variable delay circuit 110 during a period in which SCYC is active;
And an encoder 1670 that receives and encodes the outputs MIDD0 to MIDD2 from 2 to 1668 and outputs an initial delay control value.

FIG. 25 is a circuit diagram showing the comparator 1662 shown in FIG.
FIG. 3 is a block diagram showing the configuration of FIG. Comparator 1662 includes a NAND circuit 170 that receives signal CKMD1 and signal FSCYC, and a flip-flop circuit 172 that is set by the output of the NAND circuit, reset by signal FFRSTC, and outputs signal MIDD0. The flip-flop circuit 172 is connected to the cross-connected NAND circuit 1
74 and 176.

That is, the flip is performed by the signal FFRSTC.
Signal FSCYC is active and signal CKDM1 becomes active after signal MIDD
The level of 0 is set.

The structure of the other comparators 1664 and 1668 is the same. FIG. 26 shows the encoder 1 shown in FIG.
FIG. 670 is a schematic block diagram showing the configuration of 670.

Encoder 1670 includes an inverter 1672 receiving signal MIDD2, an inverter 167 receiving signal MIDD1, a signal MIDD0 and a signal MIDD0.
NAND circuit 1676 receiving DD2 and inverter 1
NAND circuit 1 receiving output of signal 672 and signal MIDD1
678, the output of the inverter 1674 and the signal MIDD0
And a NAND circuit 167 receiving
6, an inverter 1684 receiving an output of the NAND circuit 1678, an output of the inverter 1682, an output of the inverter 1642,
3-input NAND circuit 1686 receiving the output of ND circuit 1680, NAND circuit 1688 receiving the output of inverter 1684 and the output of NAND circuit 1680, the output of 3-input NAND circuit 1686 and the NAND circuit 1688
Circuit 1690 that receives the output of the
A NAND circuit 1692 receiving the output of the D circuit 1686 and the output of the NAND circuit 1680;
And an inverter 1696 that receives the output of the NAND circuit 1692 and outputs the sixth bit data bit6 of the initial delay control value. including.

Encoder 1670 further receives, as input, ground potential level as input and outputs inverter bit 598 of fifth bit data of initial delay control value, and power supply potential Vcc as input, respectively, and receives an input of initial delay control value. 4th to 0th bit data bit4 to bi
and inverters 1700 to 1708 that output t0.

Therefore, the values of the data bits 4 to 0 of the 4th to 0th bits of the initial delay control value are all fixed to “0”, and the value of the 5th bit data bit5 of the initial delay control value is “1”. It is fixed to "".

The values of the data bits 7 to 6 of the 7th to 6th bits of the initial delay control value are determined by the signals MIDD0 to MIDD0.
The value becomes an encoded value according to the level of the signal MIDD2.

With the above configuration, the initial delay control value is encoded as a value in binary notation based on the detection result of the propagation of the test signal, and stored in the delay control value holding circuit 170.

In the present embodiment, the variable delay circuit 1
10 includes four delay circuits 110a to 110d, and CKDM1 to CKDM of output signals from the respective delay circuits.
3, only the upper 2 bits of the 8-bit initial delay control value are encoded. However, the present invention is not limited to such a case, and increases or decreases the number of delay circuits or the number of bit data of the initial delay control value determined by encoding according to the number of bits of the delay control value. A configuration is also possible.

As described above, according to the configuration of initial value extension control value determining circuit 160, an internal synchronizing signal generating circuit capable of shortening the time until the completion of a synchronizing operation even when the accuracy of phase matching is increased. It is possible to provide a synchronous semiconductor memory device including:

Further, according to the invention of the first embodiment, even when a delay control value expressed in a binary number is used for controlling the delay amount of a delay circuit, an increase in the number of circuit elements is suppressed, and high-speed delay time control is possible. It is possible to provide a synchronous semiconductor memory device provided with a simple internal synchronization signal generation circuit.

[Details of Configuration of Clock Generation Circuit 2100] FIG.
FIG. 2 is a schematic block diagram illustrating a configuration of 100 functional blocks. Referring to FIGS. 27 and 5, in the following, the configuration of phase comparison circuit 120, the configuration of shift logic circuit 180 and multiplexer 2310 included in phase control circuit 2800, the configuration of variable delay circuit 2110, and the configuration of frequency divider 2300 will be described. The configuration and the configuration of the control circuit 2190 will be described.

[Configuration of Phase Comparison Circuit 120] FIG.
FIG. 2 is a block diagram for describing a configuration of a phase comparison circuit 120.

Referring to FIG. 28, phase comparing circuit 120
Is an inverter 3002 receiving a signal FDSP instructing to provide a clock signal to variable delay circuit 110.
, Signal FDLSP and external clock signal Ext. CLK
And a NAND circuit 3004 receiving the
An inverter 3006 receiving the output of the inverter 04, a NOR circuit 3008 receiving the ground potential Vss at any input,
Inverter 3010 receiving the output of NOR circuit 3008
, The signal FDSP and the signal int. A NAND circuit 3012 receiving CLK1;
The output of inverter 3002 and external clock signal Ext.
CLK and a NAND circuit 3016 receiving outputs of NAND circuits 3012 and 3014.

Therefore, when signal FDLSP is in an active state ("H" level), a signal output from inverter 3006 (hereinafter, referred to as signal SRCCLK) receives external clock signal Ext. CLK and the NAND circuit 301
6 (hereinafter referred to as signal REFCLK) is the internal clock signal i from the clock tree 168.
nt. CLK1. On the other hand, when the signal FDLSP is in an inactive state (“L” level), the inverter 3006 outputs “
L ”level signal is output, and external clock signal Ext.CLK is output from NAND circuit 3016.

Phase comparison circuit 120 further receives NAND output of inverter 3006 at one input node.
Circuit 3020 and a NAND circuit 30 at one input node.
20 and the other input node is the internal node n1
1 and an output node coupled to the other input node of NAND circuit 3020, and an input node coupled to one input node of NAND circuit 3020 and N
NAND coupled to output node of AND circuit 3020
A circuit 3024, a NAND circuit 3026 receiving one of the outputs of the NAND circuit 3024 at an input node,
A three-input NAND circuit 3028 having an input node coupled to an output node of circuit 3026, an output node of NAND circuit 3020, and a node n11;
0 and the output of the NAND circuit 3028,
A NOR circuit 3030 for outputting a signal.

The phase comparison circuit 120 further comprises a NAND
NAN receiving output of circuit 3016 at one input node
D circuit 3040 and NAND circuit 3 at one input node
040 and the other input node is the internal node n
11, and an NAN whose output node is connected to the other input node of NAND circuit 3040 and whose input node is connected to one input node of NAND circuit 3040 and the output node of NAND circuit 3040
A D circuit 3044, a NAND circuit 3046 receiving the output of the NAND circuit 3044 at one of its input nodes,
A three-input NAND circuit 3048 whose input node is coupled to the output node of D circuit 3046, the output node of NAND circuit 3040, and node n11;
10 and the output of NAND circuit 3048,
A NOR circuit 3050 that outputs an OWN signal. Phase comparison circuit 120 further includes a NAND circuit 3060 receiving the outputs of NAND circuits 3026 and 3046 and having an output node coupled to internal node n11.

The operation of the phase comparison circuit 120 will be briefly described as follows. For example, in a normal phase comparison operation mode, external clock signal Ext. CLK compared to the internal clock signal int. Consider a case where the phase of CLK1 is advanced.

In this case, external clock signal Ext. CL
K rises to "H" level and after a lapse of a predetermined time, the internal clock signal int. CLK1 is also “H”
Stand up to the level. During this fixed period, the NAND circuit 3
The potential of one input node 020 is at “H” level, and the potential of one input node of NAND circuit 3040 is at “L” level. In this state, the NOR circuit 30
30 is at "L" level and N
The DOWN signal output from the OR circuit 3050 is “H”
Becomes That is, the internal clock signal int. Control is performed to delay the phase of CLK1.

In the normal phase comparison operation mode, external clock signal Ext. CLK compared to the internal clock signal int. If the phases of CLK1 match,
Both the UP signal and the DOWN signal are at "L" level.

FIG. 29 shows one input signal SRCCLK of the phase comparison circuit 120 and a signal RE which is the other input signal.
6 is a timing chart showing a relationship with FCLK.

At time t1, signal SRCCLK is held at zero level after phase comparison circuit 120 is reset. At time t2, in a state where the UP signal is not output from the phase comparison circuit 120, the signal REFC
LK as the external clock signal Ext. When CLK is input, the DOWN signal is activated ("H" level).

After the normal phase comparison mode (DLL circuit operation mode) is set at time t3, the signal REFCL is set.
K is an external clock signal Ex by the variable delay circuit 110.
t. CLK switches to a delayed signal. On the other hand, signal SRCCLK is equal to external clock signal Ext. CLK.

At time t4, signal DOWN is reset in response to activation of signal SRCCLK.
After time t4, at time t5 when signal SRCCLK rises next, phase comparison between signal SRCCLK and signal REFCLK is performed.

In FIG. 29, at time t5, the signal DOWN is activated because the phase of signal SRCCLK is ahead of signal REFCLK.

With such a configuration, one of the outputs of the phase comparison circuit 120 (DOWN signal in FIG. 29) is activated by the phase comparison until time t3, and the signals REFCLK and REFCLK at time t3. Signal SRCC
LK, the operation of inactivating one of the signals at time t4 is performed. Therefore, at time t5, external clock signal Ext.
The pulse PS2 of the clock of CLK and the signal REF
CLK of the external clock signal Ext. The phase comparison is performed with the pulse DPS1 obtained by delaying the pulse PS1 of CLK.

If signal REFCLK and signal SRCCLK are not exchanged at time t3, pulse P
A case may occur where the phase comparison between S1 and pulse DPS1 is performed. In this case, even if the amount of delay is controlled based on the result of the phase comparison, the phase cannot be synchronized, so that extra time is required until the phase synchronization is completed.

With the configuration of the phase comparison circuit 120 shown in FIG. 28, such a useless time can be omitted.

[Configuration of Phase Control Circuit 2800] FIG.
FIG. 29 is a schematic block diagram showing a configuration of a phase control circuit 2800 shown in FIG. 28.

The phase control circuit 2800 includes a shift logic circuit 180, a multiplexer 210, and a delay control value holding circuit 170. Shift logic circuit 180 receives an UP signal and a DOWN signal from phase comparison circuit 120, and detects a timing of changing the delay control value.
OWN identification circuit 3100 and delay control value holding circuit 170
And a control value shift circuit 3200 for increasing or decreasing the delay control value in response to the output from the UP / DOWN discrimination circuit 3100 in response to the delay control value held in. UP / DOWN
In response to the signal CDLAT output from the identification circuit 3100, the delay control value holding circuit 170
At 200, the updated delay control value is fetched.

In the process of determining the initial delay control value, the delay control value holding circuit 170 receives the initial delay control value PICD <from the initial delay control value determination circuit 160.
7: 0> in response to a signal FTLAT from the control circuit 2190.

The multiplexer 210 controls the delay control value and signal C updated by the control value shift circuit 3200.
DLAT signal set and initial delay control value PICD
<7: 0> and the signal set of the signal FTLAT,
It is controlled by the control circuit 2190 and selectively outputs to the delay control value holding circuit 170 according to the operation mode.

FIG. 31 shows an UP / DOWN identification circuit 310.
FIG. 3 is a schematic block diagram illustrating a configuration of a zero.

UP / DOWN discriminating circuit 3100 includes an inverter 31 receiving an UP signal from phase comparing circuit 120.
02, a NAND circuit 3104 receiving the output of the inverter 3102 at one input node, and an inverter 3102
Circuit receiving one output node at its input node
6, the output of the NAND circuit 3104 and the NAND circuit 31
06, the output node is connected to the NAND circuit 310
Circuit 3108 coupled to the other input node 6
A NAND circuit 3110 receiving the output of NAND circuit 3106 at one input node, and a NAND circuit 3110
And an inverter 3112 which inverts the output of the NAND circuit 3104 to apply the inverted output to the other input node of the NAND circuit 3104.

UP / DOWN identification circuit 3100 further includes an inverter 3122 receiving the DOWN signal from phase comparison circuit 120, a NAND circuit 3124 receiving the output of inverter 3122 at one input node, and an output of inverter 3122 at one input node. NAN received by input node
D circuit 3126, output of NAND circuit 3124 and NA
Receiving the output of ND circuit 3126 and setting the output node to NAN
NAND coupled to the other input node of D circuit 3126
A circuit 3128, a NAND circuit 3130 receiving the output of the NAND circuit 3126 at one input node,
The output of the circuit 3130 is inverted and inverted, and the NAND circuit 31
24 includes an inverter 3132 provided to the other input node.

Output signals of NAND circuits 3106 and 3126 are applied to control value shift circuit 3200 as signal BUP and signal BDOWN, respectively.

UP / DOWN discriminating circuit 3100 further includes a NOR circuit 3140 receiving the outputs of NAND circuits 3106 and 3126, and a delay circuit 3142 receiving the output of NOR circuit 3140 and delaying the output by a predetermined time to output.
And an inverter 314 receiving the output of the delay circuit 3142
4, the output of the NOR circuit 3140 and the inverter 3144
And a NOR circuit 3146 receiving the NOR circuit 3146 receiving the output of the NOR circuit 3146 and outputting the signal CDLAT.

Here, the UP / DOWN identification circuit 3100
The operation of is simply described as follows. That is, signal UP and signal DO from phase comparison circuit 120 are output.
When both of WN are at “L” level, NOR circuit 3140
Input signals are also at "L" level. Therefore, a signal of “H” level is output from NOR circuit 3140.

Here, when either the UP signal or the DOWN signal changes to “H” level, the NOR circuit 314
The output level of “0” changes to “L” level, and in response, the NOR circuit 3146 outputs a signal CDLAT having a pulse width corresponding to the delay time of the delay circuit 3142 and the inverter 3144.

Further, signal BUP and signal BDOWN are
Are signals UP and DOWN from the phase comparison circuit 120
And "H" are signals having the same level.
The level is held at least during the CDLAT pulse signal output period.

FIG. 32 is a schematic block diagram showing a configuration of control value shift circuit 3200. Referring to FIG. 32, control value shift circuit 3200 includes delay control value holding circuit 170
8-bit delay control value data DLAST <0: 7
> And signals UPIN <0> to instruct each bit data of delay control value data DLAST <0: 7> to change in response to activation of a BUP signal from UP / DOWN discriminating circuit 3100. Signal UPIN <
7>, and an upshift operation circuit 3300 that outputs
In response to activation of the BDOWN signal from / DOWN identification circuit 3100, delay control value data DLAST <0: 7>
Signal DNIN <0> instructing change of each bit data of
.. Are provided for each bit data of the delay control value data DLAST <0: 7> and the signal UPIN <0>.
A corresponding signal of signal UPIN <7> and signal DN
IN <0> to corresponding signals of signals DNIN <7>, respectively, and receive updated delay control value data D
Bit operator 3500-3 for outputting NEW <0: 7>
570.

FIG. 33 shows an upshift operation circuit 3300.
FIG. 3 is a circuit diagram showing the configuration of FIG. Referring to FIG. 33, upshift operation circuit 3300 receives an inverter 3302 receiving signal BUP and an output of inverter 3302,
An inverter 3304 that outputs a signal UPIN <0>;
NAND circuit 3306 receiving signal BUP and delay value control data DLAST <0>, inverter 3308 receiving the output of NAND circuit 3306 and outputting signal UPIN <1>, signal BUP and delay value control data DLAST
NAND circuit 3310 receiving <0> and delay value control data DLAST <1>, and inverter 33 receiving an output of NAND circuit 3310 and outputting signal UPIN <2>
12, the signal BUP and the delay value control data DLAST <0
>, Delay value control data DLAST <1> and delay value control data DLAST <2>
Receiving the output of NAND circuit 3314 and receiving signal UPIN
And an inverter 3316 that outputs <3>.

Upshift operation circuit 3300 further includes delay value control data DLAST <0>, DLAST <
1>, DLAST <2> and DLAST <3>, and a signal UPIN <4> receiving NAND circuit 3318 and the output of inverter 3302.
A NOR circuit 3320 for outputting the delay value control data D
LAST <1>, DLAST <2>, DLAST <3>
Circuit 3322 receiving DLAST and DLAST <4>
NOR circuit 3 receiving NAND circuit 3322 and the output of inverter 3306 and outputting signal UPIN <5>
324, delay value control data DLAST <2>, DLA
ST <3>, DLAST <4> and DLAST <5>
Receiving a NAND circuit 3326 and a NAND circuit 332
6 and the output of the inverter 3310 to receive the signal UPIN
NOR circuit 3328 for outputting <6>, delay value control data DLAST <3>, DLAST <4>, DLAST
NAND circuit 3 receiving <5> and DLAST <6>
330, NAND circuit 3330 and inverter 3314
That outputs signal UPIN <7> in response to the output of
And a circuit 3332.

Next, the operation of upshift operation circuit 3300 will be briefly described. Upshift operation circuit 33
00 output signals UPIN <0> to UPIN <7>
Is a signal indicating whether or not there is a carry from the lower bit for each bit data when the delay value control data DLAST <0: 7> is increased by one. That is, when attention is paid to specific bit data, a carry is generated from a lower bit of the bit data only when all bit data lower than the bit data are “1”. Therefore, the upshift operation circuit 3300 outputs the extended value control data DLAST <0:
7>, when all the lower bits are “1”, the corresponding signal UPI
N <i> is set to “H” level.

FIG. 34 shows a downshift operation circuit 3400.
FIG. 3 is a circuit diagram showing the configuration of FIG. Referring to FIG. 34, downshift operation circuit 3300 includes an extended value control data DLAST.
Inverters 3450 to 3462 for receiving, inverting, and outputting the respective day bit data of <0: 7>, and a signal B
An inverter 3402 receiving DOWN, and an inverter 3
Inverter 3404 receiving signal 402 and outputting signal DNIN <0>, and NAND receiving signal BDDOWN and inverted data of delay value control data DLAST <0>.
A circuit 3406, an inverter 3408 receiving an output of the NAND circuit 3406 and outputting a signal DNIN <1>,
NAND circuit 3410 receiving signal BDOWN, inverted data of delay value control data DLAST <0>, and inverted data of data DLAST <1>, and NAND circuit 341
Inverter 3412 that receives signal 0 and outputs signal DNIN <2>, signal BDOWN and delay value control data D
Inversion data of LAST <0> and data DLAST <1>
Circuit 3414 receiving inverted data of data DLAST <2> and NAND circuit 341;
And an inverter 3416 receiving the output of signal No. 4 and outputting signal DNIN <3>.

The downshift operation circuit 3400 further includes inverted data of the delay value control data DLAST <0>,
A NAND circuit 3418 receives inverted data of DLAST <1>, inverted data of DLAST <2>, and inverted data of DLAST <3>, and receives the output of NAND circuit 3418 and inverter 3402 to output signal DNIN <4>. NOR circuit 3420 and delay value control data DL
Inverted data of AST <1>, inverted data of DLAST <2>, inverted data of DLAST <3>, and DLAST
A NAND circuit 3422 receiving the inverted data of <4>,
NOR circuit 342 receiving NAND circuit 3422 and the output of inverter 3406 and outputting signal DNIN <5>
4, inversion data of delay value control data DLAST <2>, inversion data of DLAST <3>, DLAST <4>
Circuit 3426 which receives the inverted data of DLAST <5> and the output of NAND circuit 3426 and inverter 3410, and receives signal DNIN <6
>, A delay value control data DLAST <3> inverted data, a DLAST <4> inverted data, a DLAST <5> inverted data and a DLA
NAND circuit 3430 receiving inverted data of ST <6>
NOR circuit 3 which receives the output of NAND circuit 3430 and inverter 3414 and outputs signal DNIN <7>
432.

Next, the operation of downshift operation circuit 3400 will be briefly described. Downshift operation circuit 34
00 output signals DNIN <0> to DNIN <7>
Is a signal indicating whether bit data is changed for each bit data as a result of occurrence of borrowing when the delay value control data DLAST <0: 7> is decreased by one. That is, when attention is paid to specific bit data, a change in the bit data due to the occurrence of a borrow occurs only when all bit data lower than the bit data are “0”. Therefore, the downshift operation circuit 3400 outputs the extended value control data DLAST <0:
7>, when all the lower bits are “0”, the corresponding signal DNI
N <i> is set to “H” level.

FIG. 35 is a circuit diagram showing a configuration of bit operation unit 3510. Other bit operators 3500, 352
The configurations of 0 to 3570 are the same except that the input signal and the output signal are different.

The bit operator 3510 outputs the signal UPIN <
NOR circuit 360 receiving signal DN1 <1> and signal DNIN <1>
0 and the inverter 3 receiving the output of the NOR circuit 3600
602, the output of the NOR circuit 3600 and the data DLAS
NAND circuit 3604 receiving T <1> and data DL
Inverter 3606 receiving inverted AST <1> and outputting inverted data, NAND circuit 3608 receiving outputs of inverters 3602 and 3606, and NAND circuit 360
4 and 3608, the data DNEW <
1> which outputs a NAND circuit 3610.

That is, bit operation unit 3510 outputs signal UPIN <1> and signal DNIN <1> to both "
When the signal is at L level, the same data as data DLAST <1> is output as data DNEW <1>, and when either signal UPIN <1> or signal DNIN <1> is at H level Outputs inverted data of data DLAST <1> as data DNEW <1>.

FIG. 36 is a schematic block diagram for describing a configuration of variable delay circuit 110, multiplexer 2310, and voltage generation circuit 150.

The variable delay circuit 110 includes the multiplexer 2
The first delay circuit 110.1 receives the output of the first delay circuit 310 and receives the output of the first delay circuit 110.1 under the control of the voltage generation circuit 150 for a predetermined time, and receives the output of the first delay circuit 110.1. And a second delay circuit 110.2.

First delay circuit 110.1 includes delay circuits 110a and 110b connected in series to each other.
Second delay circuit 110.2 includes delay circuits 110c and 110d connected in series with each other.

The variable delay circuit 110 further receives the outputs of the delay circuits 110a, 110b, 110, and 110d, and outputs the clock signals CKDM1, CKDM2, and CK.
Buffer circuit 1 for outputting as DM3 and CKDM4
12 inclusive.

FIG. 37 is a schematic block diagram showing a structure of multiplexer 2310 shown in FIG.

Referring to FIG. 37, multiplexer 231
0 is the inverter 37 receiving the output of the delay circuit 110b.
02, an inverter 3704 receiving a signal FSLDP instructing the PLL operation, and an external clock signal Ext. CL
K, a 3-input NAND circuit 3706 receiving an output of the inverter 3704, and a signal FDSP instructing to supply a clock signal to the variable delay circuit; and an inverter 3702.
3 which receives the output of the signal FSLDP and the signal FDLSP
An NAND which receives an input NAND circuit 3708, an output of the NAND circuit 3706 and an output of the NAND circuit 3708, and outputs a clock signal to be supplied to the variable delay circuit 110
Circuit 3710.

Therefore, the multiplexer 2310
It becomes active in response to the activation of the signal FDSP, and the signal FS
When LDP is inactive ("L" level), external clock signal Ext. When CLK is in the active state (“H” level), an inverted signal of signal CKDM 2 is applied to variable delay circuit 110.

FIG. 38 is a schematic block diagram showing a configuration of frequency divider 2300 and multiplexer 2410 shown in FIG.

Receiving signal CKDM2, frequency dividing section 2300 performs a frequency dividing operation in response to activation of signal FDSP.
Multiplexer 2410 is controlled by signal TMDLPL instructing switching between the DLL operation and the PLL operation, and selectively outputs signal CKDM4 and the output signal of frequency divider 2300.

FIG. 39 is a circuit diagram illustrating the structure of quadruple frequency divider 2304 in frequency divider 2300.

The quadruple frequency divider 2304 outputs the clock signal CK
An inverter 3802 receiving DM2;
02 receiving the output of signal FDL
NAND circuit 3806 receiving SP at one input node
And the output of the NAND circuit 3806 to receive the signal CKDM
2 is turned on to the “H” level, and the transmission gate 3808 is turned on when the output from the transmission gate 3808 is received.
Inverter 3810 applied to the other output node of AND circuit 3806, transmission gate 3812 receiving an output of inverter 3810, and becoming conductive when signal CKDM 2 attains an “H” level, and an output and a signal of transmission gate 3812. A NAND circuit 3814 receiving the FDSP and a NAND circuit 381
4, which is provided between an output node of the inverter 3816 and a connection node between the transmission gate 38121 and the NAND circuit 3814, and is turned on in response to the signal CKDM2 attaining the "L" level. Transmission gate 3818
Receiving the output of the NAND circuit 3814 and the quadruple frequency divider 2
Inverter 38 that outputs output signal CKOUT of 304
18 inclusive.

The quadruple frequency divider 2304 further includes a NAND
A transmission gate 3820 which receives an output of the circuit 3814 and is turned on in response to the signal CKDM2 attaining the “L” level, and a transmission gate 38
20, an inverter 3822 for receiving the output of the inverter 20, the NAND circuit 3824 for receiving the output of the inverter 3822 and the signal FDSP, and provided between the output node of the NAND circuit 3824 and the input node of the inverter 3822, and the signal CKDM2 is at "H" level. The transmission gate 3826 and the transmission gate 3820 which receive the output of the inverter 3822 and the transmission gate 3826 which become conductive when the signal CKDM2 becomes "H" level,
Circuit 383 receiving the output of FD and signal FDSP
2, an inverter 3834 receiving an output of the NAND circuit 3832, a transmission gate 3830, and an NA
The signal CKDM2 is provided between the connection node of the ND circuit 3832 and the output node of the inverter 3834, and the signal CKDM2 is "L".
A transmission gate 3836 which becomes conductive according to the level, an inverter 3840 receiving an output of the NAND circuit 3832, and an output node of the inverter 3840 and an input node of the inverter 3810 are provided. Transmission gate 38 which becomes conductive in response to L "level
42.

With the above configuration, in the quadruple frequency divider 2304, four latch circuits for sequentially taking in signals in accordance with activation and inactivation of the clock signal CKDM2 are connected in series, and the input signal The configuration is such that a clock signal having a cycle four times that of CKDM2 is generated.

[Configuration of Control Circuit 2190] FIG. 40 is a schematic block diagram for illustrating a configuration of control circuit 2190 shown in FIG.

Control circuit 2190 controls external clock signal E
xt. A counter circuit 3900 that counts the number of activations of CLK; a timing signal generation circuit 3902 that controls the timing of generating a control signal in accordance with the count result of the counter circuit 3900; and a control circuit that controls the output of the timing signal generation circuit 3902 A flag generation circuit 3904 for generating a flag signal corresponding to the signal, and a signal FPFD for controlling which of the data from the initial delay control value determination circuit 180 and the data from the shift logic circuit 180 is supplied to the delay control value holding circuit 170 A delay circuit 3906 for adjusting the output timing of the control signal and a signal T from the control circuit.
A DLL / PLL switching signal generation circuit 3908 that outputs a signal FSLDP instructing switching between the PLL operation and the DLL operation according to MDLPL, and a reset signal generation circuit 3910 that generates a reset signal according to a reset signal from control circuit 20 And

Here, control signal FDRST output from flag generation circuit 3904 is a signal indicating a value for resetting the delay control value, and control signal FTRST is a signal for instructing reset of the delay control value. Control signal FFR
ST is a signal for instructing reset of the initial value extension control value setting circuit, and the control signal FDLSP is
And a control signal FTLAT is a signal for instructing the timing of the delay control value holding circuit 170 to capture the delay control value.

Control signal FPFD is a signal for controlling which of data from initial delay control value determination circuit 180 and data from shift logic circuit 180 is supplied to delay control value holding circuit 170, and control signal FSLDP is PLL
This is a signal for instructing the start of the ring oscillator operation in the operation mode.

FIG. 41 is a schematic block diagram illustrating a structure of timing signal generating circuit 3902 shown in FIG.

Timing signal generation circuit 3902 receives signal FCNT from flag generation circuit 3904 and receives signal CCNT.
An inverter 3920 that outputs NTR0, an inverter 3922 that receives an output of the inverter 3920 and outputs a signal CNTR1, a third bit data TCD <3> of the count value from the counter circuit 3900, and a signal CN
NAN that receives TR0 and outputs signal SDRST
D circuit 3924, signal CNTR1 and data TCD <4
> NAND circuit 3 that outputs signal RDRST in response to
926, NAND circuit 3928 receiving signal CNTR0 and data TCD <4> and outputting signal RTRST
And the external clock signal Ext. Inverter 3930 receiving CLK, NAND circuit 3932 receiving signal CNTR1, data TCD <1>, and the output of inverter 3930 to output signal RFRST, and outputting signal STLAT in response to signal CNTR1 and data TCD <3>. Circuit 3934, the signal CNTR1 and the data TC
NAND that receives D <4> and outputs signal RTLAT
Circuit 3936, signal CNTR1 and data TCD <6>
Circuit 393 that outputs signal SPFD in response to
8 and a reset signal MRS from the control circuit 20.
T which receives signal T, signal CNTR0, and signal FCNTF from flag generation circuit 3904 and outputs signal SRST2
ND circuit 3940, signal CNTR1 and data TCD <
0> and outputs a signal RRST2, and a NAND circuit 3944 that receives a signal CNTR0 and data TCD <6> and outputs a signal SCNTF.
, A signal CNTR0, data TCD <0>, and a signal FRST2 from the flag generation circuit, and a NAND circuit 3946 that outputs a signal SCNT. Circuit 3948 for outputting the signal SDLSP
And a NAND circuit 3948 that receives signal CNTR1, data TCD <5>, and the output of inverter 3930, and outputs signal RDLSP.

FIG. 42 is a circuit diagram showing a configuration of flag generation circuit 3904. Flag generation circuit 3904 includes an inverter 3952 receiving signal MRST, and an inverter 3
Inverter 3954 that receives signal 952 and outputs signal IRST, and is set in response to activation of signal SPFD (change to “L” level), and activation of signal IRST (change to “L” level) Flip-flop circuit 395 that is reset in response to and outputs signal FPFDS
6 and activation of signal IRST (change to "L" level)
Signal RDRST or signal SDR
SR flip-flop circuit 3958, which is reset in response to activation of ST (change to “L” level) and outputs signal FDRST, is set in response to activation of signal SCNT, and is activated in response to activation of signal IRST. Reset,
SR flip-flop circuit 39 for outputting signal FCNT
60.

The flag generation circuit 3904 is set in response to the activation of the signal STLAT, and sets the signal IRST.
Or reset in response to activation of signal RTLAT,
SR flip-flop circuit 3 that outputs signal FTLAT
962, an SR flip-flop circuit 396 which is set in response to the activation of the signal RFRST, is reset in response to the activation of the signal IRST, and outputs the signal FFRST.
4 is set in response to the activation of the signal RTRST, and is reset in response to the activation of the signal IRST.
And an SR flip-flop circuit 3966 for outputting ST.

The flag generation circuit 3904 is set in response to the activation of the signal SCNTF, and sets the signal IRST.
SR flip-flop circuit 3968 which is reset in response to the activation of the signal and outputs signal FCNTF, and signal RFR
ST is set in response to activation of ST or signal RDLSP, is reset in response to activation of signal IRST or signal SDLSP, is set in response to activation of signal SRST2, and SR flip-flop circuit 3970 that outputs signal FDLSP. Signal IRST or signal RRST2
, And an SR flip-flop circuit 3972 that outputs signal FRST2.

Delay circuit 3906 receives signal FPFDS, delays it by a predetermined time, and outputs it as signal FPFD.

FIG. 43 is a circuit diagram showing a configuration of DLL / PLL switching signal generation circuit 3908.

DLL / PLL switching signal generating circuit 3908
Is set in response to activation of signal STLAT, and is reset in response to activation of signal TFRST from reset signal generation circuit 3910.
988, a NAND circuit 3984 receiving the signal TMDLPL and the output of the SR flip-flop circuit 3908,
Upon receiving the output of the NAND circuit 3984, the signal FSLDP
And an inverter 3986 for outputting the same.

Therefore, when signal TMDLPL is at "L" level and the DLL operation mode is designated, signal FSLDP is at "L" level. On the other hand, when the signal TMDLPL is at the “H” level and the PLL operation mode is designated, the signal FSLDP causes the delay control value holding circuit 170 to take in the fixed delay control value and activate the signal FTLAT. It becomes "H" level when instructed.

With the above configuration, FIGS.
The operation of the internal clock generation circuit 2100 described above is realized.

[Modification of First Embodiment] FIG. 44 shows a DPLL circuit 4 capable of operating by switching between a DLL operation mode and a PLL operation mode according to a modification of the first embodiment.
It is a schematic block diagram which shows the structure of 018.

Referring to FIG. 44, internal synchronization signal generating circuit 4018 includes a variable delay circuit 110 which delays an input signal by a predetermined time and outputs the delayed signal.

The variable delay circuit 110 comprises a first delay circuit 110.1 and a second delay circuit 11
0.2.

Internal synchronization signal generation circuit 4018 further includes an external clock signal Ext. CLK and the output signal of the first delay circuit 110.
xt. A multiplexer 2310 for selectively outputting the CLK or an inverted signal of the output signal of the delay circuit 110.1 to the variable delay circuit 110; an output of the first delay circuit 110.1 and an output of the second delay circuit 110.2; In response to this, one of the internal clock signals int. Multiplexer 2320 for outputting as CLK and first delay circuit 11
A frequency divider 2300 that receives an output of 0.1 and divides the frequency by a predetermined frequency division ratio; an output of the frequency divider 2300 and the second delay circuit 1
10.2, which selectively receives and outputs the output of the external clock signal Ext. CLK, and compares the two phases. Depending on whether the phase of the output of the multiplexer 2410 is advanced or delayed, a phase comparison circuit 120 that activates either the UP signal or the DOWN signal is provided. Charge pump circuit 4510 that operates in response to an UP signal and a DOWN signal from circuit 120, and a capacitor 4512 and a resistor 45 connected in series between an output node of charge pump circuit 4510 and a power supply potential.
14 and a voltage generation circuit 4520 that receives an output from the charge pump circuit 4510 and generates a reference potential for controlling the delay amount of the variable delay circuit 110.

In the above configuration, similarly to the internal synchronization signal generating circuit of the first embodiment, the DLL operation mode and the PL
It is possible to operate by switching between the L operation mode.

In this case, regardless of whether the circuit operates as a DLL circuit or a PLL circuit, the variable delay circuit 110, the phase comparison circuit 120, the charge pump circuit 4
Since the 510, the voltage generation circuit 2520, and the like can be commonly used, an increase in chip area can be suppressed.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0276]

According to the synchronous semiconductor memory device of the first aspect, the DLL operation and the PL operation can be performed while suppressing an increase in chip area.
It is possible to operate by switching the L operation.

A synchronous semiconductor memory device according to claim 2 is
It is possible to generate an internal clock signal that changes faster than the external clock signal.

In the synchronous semiconductor memory device according to the third and fourth aspects, the configuration of the phase control circuit can be simplified.

A synchronous semiconductor memory device according to claim 5 is
The initial value of the delay control amount is detected in advance by the delay detection circuit,
Since the delay amount of the delay locked loop circuit is set, it is possible to shorten the time until the completion of the synchronization operation even when the accuracy of the phase adjustment is increased.

In the synchronous semiconductor memory device according to the sixth and seventh aspects, the current from the constant current source cell for generating a current of 2 ^j-1 × I and the current from the constant current source cell for generating a current of I / 2 ^k Since the delay time of the variable delay circuit is controlled by the current value obtained by combining the currents of the above, even if the delay amount is expressed in a binary number, the increase in the number of circuit elements is suppressed, and high-speed delay time control is achieved. It is possible to provide a synchronous semiconductor memory device including a possible internal synchronization signal generation circuit.

A synchronous semiconductor memory device according to claim 8 is
It is possible to reduce the time required to achieve synchronization between the internal clock signal and the external clock signal.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing a configuration of a synchronous semiconductor memory device 1000 according to a first embodiment of the present invention.

FIG. 2 is a schematic block diagram illustrating a configuration of an internal synchronization signal generation circuit 2018 according to the first embodiment of the present invention.

FIG. 3 is a conceptual diagram showing a configuration of a clock tree 168.

FIG. 4 is a schematic block diagram for describing the configurations of an internal synchronization signal generation circuit 2018 and a clock tree 168 in more detail.

FIG. 5 shows a phase control circuit 2800 and a multiplexer 23.
FIG. 2 is a schematic block diagram for describing the configuration of a variable delay circuit and a variable delay circuit in more detail.

FIG. 6 is a flowchart illustrating an operation of an internal synchronization signal generation circuit 2018.

FIG. 7 is a timing chart for explaining the DLL operation of the internal synchronization signal generation circuit 2018 in more detail.

FIG. 8 is a timing chart for explaining the PLL operation of the internal synchronization signal generation circuit 2018 in more detail.

FIG. 9 is a conceptual diagram schematically showing the operation of a variable delay circuit 110 in a clock generation circuit 2100.

FIG. 10 shows the input signal SRCCL described in FIG.
5 is a timing chart showing a relationship between K and an output signal DSTCLK.

FIG. 11 is a schematic block diagram showing an example of a configuration of a ring oscillator including a variable delay circuit 110.

12 is a timing chart for explaining the operation of the ring oscillator of FIG.

FIG. 13 is a schematic block diagram showing another example of the configuration of the ring oscillator including the variable delay circuit 110.

14 is a timing chart for explaining the operation of the ring oscillator having the configuration shown in FIG.

FIG. 15 is a schematic block diagram showing a configuration for enabling operation by switching between a DLL operation mode and a PLL operation mode.

FIG. 16 is a schematic block diagram for explaining the configuration of the variable constant current circuit 140 in more detail.

FIG. 17 is a circuit diagram for describing a configuration of a reference current generation circuit 141 and a constant current source cell group 142.

FIG. 18 shows a current synthesis circuit 143 and a voltage generation circuit 1
It is a schematic block diagram which shows the structure of 50.

FIG. 19 shows a delay circuit 110a in the variable delay circuit 110
And FIG. 110b is a block diagram showing the configuration of 110b.

20 is a circuit diagram showing a configuration of an inverter Inv11 shown in FIG.

21 is a schematic block diagram illustrating a configuration of an initial delay control value determination circuit 160. FIG.

FIG. 22 is a block diagram illustrating a configuration of a reset signal generation circuit 162.

FIG. 23 is a block diagram showing a configuration of a timing generation circuit 164.

FIG. 24 is a schematic block diagram showing a configuration of a comparison logic circuit 166.

FIG. 25 is a block diagram showing a configuration of a comparator 1662 shown in FIG.

FIG. 26 is a schematic block diagram showing a configuration of an encoder 1670 shown in FIG.

FIG. 27 is a schematic block diagram showing a configuration of a functional block of a clock generation circuit 2100.

FIG. 28 is a block diagram for explaining a configuration of a phase comparison circuit 120.

FIG. 29 shows one input signal SR of the phase comparison circuit 120.
9 is a timing chart showing a relationship between CCLK and a signal REFCLK which is another input signal.

FIG. 30 is a schematic block diagram showing a configuration of a phase control circuit 2800.

FIG. 31 is a schematic block diagram showing a configuration of an UP / DOWN identification circuit 3100.

FIG. 32 is a schematic block diagram showing a configuration of a control value shift circuit 3200.

FIG. 33 is a circuit diagram showing a configuration of an upshift operation circuit 3300.

FIG. 34 is a circuit diagram showing a configuration of a downshift operation circuit 3400.

FIG. 35 is a circuit diagram showing a configuration of a bit operator 3510.

FIG. 36 shows a variable delay circuit 110 and a multiplexer 23.
10 is a schematic block diagram for explaining a configuration of a voltage generation circuit 150. FIG.

FIG. 37 is a schematic block diagram showing a configuration of a multiplexer 2310 shown in FIG.

38 is a schematic block diagram illustrating a configuration of a frequency divider 2300 and a multiplexer 2410 illustrated in FIG.

39 is a circuit diagram illustrating a configuration of a quadruple frequency divider 2304 in a frequency divider 2300. FIG.

40 is a schematic block diagram for illustrating a configuration of control circuit 2190 shown in FIG.

FIG. 41 is a timing signal generation circuit 3 shown in FIG. 40;
FIG. 2 is a schematic block diagram for explaining a configuration of the image processing unit 902.

FIG. 42 is a circuit diagram showing a configuration of a flag generation circuit 3904.

FIG. 43 shows a DLL / PLL switching signal generation circuit 3908.
FIG. 3 is a circuit diagram showing the configuration of FIG.

FIG. 44 shows a DPLL circuit 40 according to a modification of the first embodiment.
It is a schematic block diagram which shows the structure of 18.

FIG. 45 is a schematic block diagram showing a configuration of a conventional internal synchronization signal generation circuit 5000.

[Explanation of symbols]

Reference Signs List 10 external control signal input terminal group, 12 address signal input terminal group, 14 input / output buffer circuit, 16 clock signal input terminal, 20 control circuit, 30 redundant column selection circuit, 32 redundant row selection circuit, 34 predecoder, 3
6 row pre-decoder, 38 read / write amplifier, 4
0 column predecoder, 42 column decoder, 44
Row decoder, 50a to 50c address bus, 52
Address driver, 54 data bus, 100 memory cell array, 110 variable delay circuit, 120 phase comparison circuit, 140 variable constant current circuit, 150 voltage generation circuit, 160 initial delay control value determination circuit, 170 delay control value holding circuit, 180 shift logic Circuit, 190 detection control circuit, 200, 210 multiplexer, 1000
Synchronous semiconductor memory device, 2018 Internal synchronization signal generation circuit, 2190 control circuit, 2300 frequency divider, 2310,
2220, 2320, 2410 Multiplexer, 28
00 Phase control circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B024 AA07 AA15 BA21 BA23 CA07 CA27 5J106 AA03 AA04 CC21 CC52 CC59 DD10 DD24 DD39 GG14 HH02 JJ07 KK03 KK39

Claims (8)

[Claims] 1. A synchronous semiconductor memory device receiving an address signal and a control signal from the outside in synchronization with an external clock signal, and transmitting and receiving storage data to and from the outside, wherein the semiconductor devices are arranged in a matrix. A memory cell array having a plurality of memory cells; a control circuit controlling operation of the synchronous semiconductor memory device in accordance with the control signal; and selecting the memory cell in accordance with the address signal; A cell selection circuit for transmitting and receiving the storage data between the external clock signal and an internal synchronization signal generation circuit for outputting an internal clock signal synchronized with the external clock signal. A variable delay circuit having a plurality of serially connected internal delay circuits, and inverting an output from a predetermined one of the plurality of internal delay circuits. A first switching circuit that receives the signal and the external clock signal and selectively provides the variable delay circuit with the output signal, and receives an output signal from the predetermined internal delay circuit and an output from the variable delay circuit, A second switching circuit that selectively outputs the internal clock signal, a phase comparison circuit that compares a phase of the external clock signal with a signal corresponding to a signal transmitted through the variable delay circuit, A phase control circuit that controls a delay amount of the variable delay circuit so that a phase is synchronized according to the comparison result, wherein the cell selection circuit operates in synchronization with the internal clock signal. . 2. A frequency divider that receives an output of the predetermined internal delay circuit and divides the frequency by a predetermined frequency division ratio; and receives an output signal of the frequency divider and an output signal of the variable delay circuit. 3. The circuit according to claim 1, further comprising a third switching circuit that selectively outputs one of them, wherein the phase comparison circuit compares a phase of an output signal of the third switching circuit with a phase of the external clock signal. Synchronous semiconductor memory device. 3. The variable delay circuit includes 2m (m: natural number) internal delay circuits connected in series with each other, and the predetermined internal delay circuit is an m-th internal delay circuit. A synchronous semiconductor memory device according to claim 1 or 2. 4. The storage device according to claim 1, wherein the phase control circuit updates a delay amount held in accordance with an output from the phase comparison circuit; 2. The synchronous semiconductor memory device according to claim 1, further comprising: a delay control circuit that controls a delay time of said variable delay circuit. 5. The phase control circuit further includes a delay detection circuit that detects a delay amount of the external clock signal in the variable delay circuit, determines an initial value of the delay amount, and provides the delay value to the storage circuit. The delay detection circuit includes: a detection control circuit configured to control an operation of the delay detection circuit; receiving the external clock signal, and selectively controlling a test signal for one cycle of the external clock signal under the control of the detection control circuit. A first selection circuit for supplying to the variable delay circuit, a delay for detecting to which of the plurality of internal delay circuits the test signal has propagated during a predetermined time, and determining an initial value of the delay amount A measurement circuit, which is provided between the comparison circuit and the storage circuit, receives an output of the comparison circuit and an output of the delay detection circuit, and is selectively controlled by the detection control circuit to select one of the outputs; 2. The synchronous semiconductor memory device according to claim 1, further comprising a second selection circuit provided to the storage circuit. 6. The delay control circuit includes a variable constant current circuit that generates a control current according to the delay amount held in the storage circuit, wherein the variable constant current circuit sets a predetermined current value to I. , J and k are natural numbers, and have a plurality of first constant current sources, and the j-th first constant current source among the first constant current sources is:
Generating a current of 2 ^j-1 × I, further comprising a plurality of second constant current sources, wherein the k-th second constant current source among the second constant current sources is:
A current of I / 2 ^k is generated, and a current from the first constant current source and a current from the second constant current source are selectively combined according to the delay amount held in the storage circuit. 5. The synchronous semiconductor memory device according to claim 4, further comprising a current synthesis circuit configured to generate the control current, wherein a delay time of the variable delay circuit is controlled according to the control current value. 6. 7. Each of the internal delay circuits includes a plurality of serially connected buffer circuits whose signal delay time changes according to an operation current value, and wherein the delay control circuit stores the control current value in the buffer circuit. 7. The synchronous semiconductor memory device according to claim 6, further comprising: a voltage generation circuit for converting an operation current value of said semiconductor device into a reference voltage. 8. A phase comparison circuit comprising: a first internal node to which a reference clock signal is applied; a second internal node to which a clock signal to be compared is applied; A comparison circuit for comparing signals, receiving an output signal of the third switching circuit and the external clock signal, providing a signal of a predetermined level to the first internal node, and providing the external signal to the second internal node. An input for switching between a first state in which a clock signal is applied and a second state in which the external clock signal is applied to the first internal node and the output signal of the third switching circuit is applied to the second internal node; 3. The synchronous semiconductor memory device according to claim 2, further comprising a control unit.