JP2000068367A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

(57) [Problem] To provide a technique capable of preventing a reduction in the manufacturing yield of a semiconductor integrated circuit device having a shallow trench isolation in an element isolation region. SOLUTION: After forming a groove 5a in an element isolation region of a semiconductor substrate 1, a relatively thin silicon oxide film 6 is formed on the inner wall of the groove 5a, and then by a CVD method using TEOS and ozone as a source gas. A silicon oxide film 7 is deposited on the semiconductor substrate 1. Thereafter, by subjecting the semiconductor substrate 1 to a heat treatment under a high-temperature hydrostatic pressure at a temperature equal to or higher than the glass softening point, it is possible to prevent the deposition change accompanying the contraction of the silicon oxide film 7 from gathering at the center of the groove 5a. The generation of voids in the buried silicon oxide film 7 is suppressed to form a shallow trench isolation having a smooth surface.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device manufacturing technique, and more particularly, to a shallow trench isolation (Shallow Trench) for electrically separating adjacent semiconductor elements from each other.
The present invention relates to a technology effective when applied to a semiconductor integrated circuit device having ench isolation (STI).

[0002]

2. Description of the Related Art One of the isolations for electrically isolating adjacent semiconductor elements from each other is to provide a groove of, for example, about 0.4 μm in a semiconductor substrate serving as an element isolation region and bury an insulating film in the groove. There is a shallow trench isolation formed. This shallow groove isolation is a typical isolation such as LOCOS (Local Oxidation
As compared with (f Silicon) isolation, there are advantages such as better flatness and prevention of a decrease in the area of an active region for forming a semiconductor element.

In the shallow trench isolation, first, a trench is formed in an element isolation region of a semiconductor substrate composed of silicon single crystal, and then the semiconductor substrate is exposed by performing a thermal oxidation process. 1 thickness on the surface
A thin silicon oxide film of about 0 to 20 nm is formed. After this, tetraethoxysilane (Tetra Ethyl Ortho Silicon)
cate (Si (OC ₂ H ₅ ) ₄ ); TEOS) gas and ozone gas as raw materials for plasma CVD (Chemical Vapor Deposit)
A silicon oxide film is deposited on a semiconductor substrate by an ion (chemical vapor deposition) method, and then the silicon oxide film is densified by subjecting the semiconductor substrate to a heat treatment in an inert atmosphere under normal pressure. (Bake tightening). Next, by flattening the surface of the silicon oxide film, the silicon oxide film is buried in the above-described groove to form shallow groove isolation.

As an example describing shallow groove isolation, a symposium on VLSI Technology Digest of Technical
Paper (1996 Symposium on VLSI Technology Digest o
f Technical Papers, pp.158, HS Lee et.al. An O
ptimizied densification of the filled oxide forqua
rter micron Shallow Trench Isolation (STI)).

[0005]

However, according to the study by the present inventors, it has been found that when the heat treatment for baking is performed on a semiconductor substrate, voids are generated in the silicon oxide film embedded in the trench. It became. The formation of the voids is caused by the fact that the bonding state of silicon atoms and oxygen atoms constituting the silicon oxide film embedded in the trench is different between the central portion of the trench and the other portions, and the change in deposition due to the shrinkage of the silicon oxide film is caused by the trench. It is thought to be gathered in the central part of.

When the voids are formed in the silicon oxide film buried in the grooves, even if the surface of the silicon oxide film is polished in a later step, the surface of the silicon oxide film 7 is flattened by the voids as shown in FIG. do not become. For this reason, unevenness occurs on the surface of the shallow groove isolation formed by the silicon oxide film, and an etching residue occurs when etching the film deposited on the upper portion of the shallow groove isolation, thereby lowering the manufacturing yield. .

An object of the present invention is to provide a technique capable of improving the manufacturing yield of a semiconductor integrated circuit device having shallow groove isolation.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, when a shallow trench isolation is formed in an element isolation region on a main surface of a semiconductor substrate, a first silicon oxide film and a nitride film are formed on the surface of the semiconductor substrate. A step of sequentially forming a silicon film; a step of sequentially etching the silicon nitride film, the first silicon oxide film and the semiconductor substrate in the element isolation region to form a groove in the semiconductor substrate in the element isolation region; After forming a relatively thin second silicon oxide film,
Depositing a third silicon oxide film on the semiconductor substrate by a CVD method using TEOS and ozone as source gases, and subjecting the semiconductor substrate to a heat treatment under a high-temperature hydrostatic pressure at a temperature equal to or lower than the glass softening point; After planarizing the surface of the third silicon oxide film and leaving the third silicon oxide film inside the groove, the silicon nitride film exposed on the surface of the semiconductor substrate is removed, and then exposed on the surface of the semiconductor substrate. Removing the first silicon oxide film thus formed.

According to the above means, the silicon oxide film embedded in the groove is subjected to a heat treatment under a high-temperature hydrostatic pressure, so that the bonding state between silicon atoms and oxygen atoms constituting the silicon oxide film is changed to the center of the groove. This is almost the same between the portion and the other portion, and it is possible to prevent the change in deposition due to the contraction of the silicon oxide film from being collected at the center of the groove. by this,
Since voids do not occur in the silicon oxide film embedded in the groove, even if the surface of the silicon oxide film is polished in a later step to leave the silicon oxide film inside the groove, the surface becomes smooth and the shallow groove When etching the film deposited on the silicon oxide film that forms the portion, no etching residue occurs.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. A method of manufacturing shallow groove isolation applied to a DRAM (Dynamic Random Access Memory) according to an embodiment of the present invention will be described with reference to FIGS. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and
The description of the repetition is omitted.

1 to 9 are cross-sectional views of a main part of a semiconductor substrate showing a method of manufacturing a shallow trench isolation formed in a device isolation region of a DRAM in the order of steps. FIG. FIG. 4 is a graph showing a relationship between a length of a void generated in a silicon film and a heat treatment temperature.

First, as shown in FIG. 1, a p-type semiconductor substrate (semiconductor wafer) 1 having a specific resistance of about 10 .OMEGA.
After a thin silicon oxide film 2 having a film pressure of about 10 nm is formed on the surface by wet oxidation at about 0 ° C., a silicon nitride film 3 having a thickness of about 140 nm is deposited on the silicon oxide film 2 by a CVD method. The silicon oxide film 2 is formed to alleviate stress applied to the semiconductor substrate 1 when, for example, baking down a silicon oxide film embedded in the trench of the element isolation region in a later step. Silicon nitride film 3
Is used as a mask for preventing oxidation of the surface of the semiconductor substrate underneath (active region).

Next, as shown in FIG. 2, the silicon nitride film 3, the silicon oxide film 2 and the semiconductor substrate 1 are dry-etched using the photoresist film 4 as a mask, so that the semiconductor substrate 1 in the element isolation region is deeply etched. 300-400
A groove 5a of about nm is formed. To form the groove 5a,
After the silicon nitride film 3 is dry-etched using the photoresist film 4 as a mask, and then the photoresist film 4 is removed, the silicon oxide film 2 and the semiconductor substrate 1 may be dry-etched using the silicon nitride film 3 as a mask. .

Next, after removing the photoresist film 4,
As shown in FIG. 3, in order to remove a damaged layer formed on the inner wall of the groove 5a by the above-mentioned etching, the semiconductor substrate 1 is removed by 85.
By wet oxidation at about 0 to 900 ° C., a thin silicon oxide film 6 having a thickness of about 10 nm is formed on the inner wall of the groove 5a. A silicon nitride film or a silicon oxynitride film may be formed on the inner wall of the groove 5a.

Next, as shown in FIG. 4, a silicon oxide film 7 having a thickness of about 600 nm is deposited on the semiconductor substrate 1.
The silicon oxide film 7 is formed at a low temperature of about 300 to 350 ° C.
Deposition is performed by a CVD method that can cause a chemical reaction under reduced pressure or under normal pressure or higher pressure than atmospheric pressure. As a source gas for supplying silicon atoms, for example, TEOS or silane-based gas as ethyl silicate is used, and as a source gas for supplying oxygen atoms, for example, ozone, oxygen, N ₂ O, NO, or H ₂ O ₂ is used. .

Thereafter, the semiconductor substrate 1 is subjected to a heat treatment under a high hydrostatic pressure at a temperature equal to or higher than the glass softening point of the silicon oxide film 7 to change the bonding state between silicon atoms and oxygen atoms constituting the silicon oxide film 7. At the same time, the silicon oxide film 7 is softened to suppress generation of voids.

This heat treatment is performed in an inert gas atmosphere (A
r, N ₂ , He, etc.) or in an oxidizing atmosphere, where alcohols (CH ₃ OH, C ₂ H ₅ OH)
Etc.) or TEOS may be added. By adding alcohols or TEOS, it becomes possible to change the concentration of impurities contained in the silicon oxide film 7 and shift the glass softening point of the silicon oxide film 7 to a lower temperature side. The heat treatment is performed at a pressure of 10 atm or more, but the glass softening point can be shifted to a lower temperature side by increasing the pressure.

Next, as shown in FIG. 5, a silicon nitride film 8 having a thickness of about 100 nm is deposited on the silicon oxide film 7 by the CVD method, and then, as shown in FIG. Then, the silicon nitride film 8 is dry-etched so that the silicon nitride film 8 is formed only on the upper portion of the groove 5a having a relatively large area, for example, at the boundary between a memory array (a region where a memory cell is formed) and a peripheral circuit. Leave. The silicon nitride film 8 remaining on the upper part of the groove 5a is formed by chemically polishing the silicon oxide film 7 in the next step.
When polishing and flattening by a CMP (Chemical Polishing) method, the silicon oxide film 7 inside the groove 5a having a relatively large area is deeper than the silicon oxide film 7 inside the groove 5a having a relatively small area. The phenomenon of polishing (dishing; dishin
g) is formed to prevent.

Next, after removing the photoresist film 9,
As shown in FIG. 7, the silicon oxide film 7 is polished by a CMP method using the silicon nitride films 3 and 8 as a stopper and is left inside the groove 5a to form an element isolation groove (shallow groove isolation) 5. I do.

Next, as shown in FIG. 8, the silicon nitride films 3 and 8 are removed by wet etching using hot phosphoric acid. Here, as shown in the steps described with reference to FIG. 4, since the silicon oxide film 7 is softened by heat treatment under high-temperature hydrostatic pressure to prevent generation of voids, the silicon nitride film 8 is removed. The silicon oxide film 7 buried inside the groove 5a after the etching has a smooth surface.

Next, an n-type impurity, for example, P (phosphorus) is ion-implanted into the semiconductor substrate 1 of the memory array to form an n-type semiconductor region 10 and a part of the memory array and peripheral circuits (n-channel MISFET ( Metal Insulator Semico
nductor Field Effect Transistor)
A p-type impurity, for example, B (boron) is ion-implanted to form a p-type well 11, and an n-type impurity is formed in another part of the peripheral circuit (a region for forming a p-channel MISFET).
For example, P ions are implanted to form the n-type well 12. Following this ion implantation, MISFET
For adjusting the threshold voltage of BF ₂ , for example, BF ₂
(Boron fluoride) in p-type well 11 and n-type well 1
2 is ion-implanted.

Next, the p-type well 11 and the n-type well 1
After removing the silicon oxide film 2 on each surface of the substrate 2 using an HF (fluorine) cleaning solution, the semiconductor substrate 1 is wet-oxidized at about 850 ° C. to form a film on each surface of the p-type well 11 and the n-type well 12. Clean gate oxide film 1 about 7 nm thick
Form 3

Next, as shown in FIG.
The gate electrodes 14A, 14B, 14C are formed on the upper part of 3 The gate electrode 14A is a MISFE for selecting a memory cell.
T and a word line W in a region other than the active region.
Functions as L. The gate electrode 14B and the gate electrode 14C constitute each part of the n-channel MISFET and the p-channel MISFET of the peripheral circuit.

For the gate electrode 14A (word line WL) and the gate electrodes 14B and 14C, a polycrystalline silicon film having a thickness of about 70 nm doped with an n-type impurity such as P is deposited on the semiconductor substrate 1 by the CVD method. Then, a WN (tungsten nitride) film having a thickness of about 50 nm and a W film having a thickness of about 100 nm are deposited thereon by a sputtering method, and a silicon nitride film 15 having a thickness of about 150 nm is further formed thereon by a CVD method. After deposition, these films are formed by patterning these films using the photoresist film 16 as a mask. Here, the surface of the element isolation groove (shallow groove isolation) 5 is smooth without any irregularities.
Gate electrode 14A (word line WL) and gate electrode 1
It is possible to prevent an etching residue at the time of patterning of 4B and 14C.

The WN film functions as a barrier layer for preventing the W film and the polycrystalline silicon film from reacting during the high-temperature heat treatment to form a high-resistance silicide layer at the interface between them.
Further, by forming the gate electrode 14A (word line WL) and part of the gate electrodes 14B and 14C with a low-resistance W film, the sheet resistance can be reduced to about 2 to 2.5 Ω / □.

Next, although not shown, after the photoresist film 16 is removed, a dry etching residue and a photoresist residue remaining on the surface of the semiconductor substrate 1 are removed using an etching solution such as fluorine. Thereafter, a bit line is formed above the gate electrode 14A (word line),
Next, an information storage capacitor is formed in the memory array,
Further, a wiring layer is formed.

FIG. 10 shows that after a silicon oxide film 7 is deposited on the semiconductor substrate 1 by a plasma CVD method using TEOS and ozone as source gases, the temperature of the heat treatment performed on the semiconductor substrate 1 under a high-temperature hydrostatic pressure is shown. The relationship with the length (L) of the void generated in the silicon oxide film 7 by this heat treatment is shown.
The heat treatment is performed for about 30 minutes in an Ar gas atmosphere at a constant pressure of 150 MPa. In the figure, the length of the voids generated in the silicon oxide film 7 subjected to the heat treatment is plotted with the length of the voids generated in the silicon oxide film 7 not subjected to the heat treatment as 1.

If the heat treatment temperature is equal to or lower than the glass softening point of 1100 ° C. or less, voids are generated even when the heat treatment is performed under high hydrostatic pressure, and the length of the voids is equal to the length of the void generated in the silicon oxide film 7 not subjected to the heat treatment. And almost the same. On the other hand, when the heat treatment temperature is equal to or higher than the glass softening point of 1200 ° C. or higher, no void is generated.

As described above, according to the present embodiment, the groove 5
By subjecting the silicon oxide film 7 embedded in the silicon oxide film 7 to a heat treatment under a high-temperature hydrostatic pressure at a temperature higher than the glass softening point, the bonding state of silicon atoms and oxygen atoms constituting the silicon oxide film 7 The central portion and the other portions are substantially the same, and it is possible to prevent a change in deposition due to the contraction of the silicon oxide film 7 from being collected at the central portion of the groove 5a. As a result, no void is generated in the silicon oxide film 7 buried in the groove 5a, so that even if the surface of the silicon oxide film 7 is planarized and the silicon oxide film 7 is left inside the groove 5a,
The surface becomes smooth, and the gate electrode (word line WL) 14A and the gate electrode 1A deposited on the silicon oxide film 7 forming the element isolation trench (shallow trench isolation) 5 are formed.
When etching the films constituting 4B and 14C, no etching residue occurs.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, the semiconductor wafer is not limited to a single silicon single crystal, but can be variously modified.
For example, an epitaxial wafer having a thin (eg, 1 μm or less) epitaxial layer formed on the surface of a silicon single crystal semiconductor substrate, an SOI (Silicon On Insulator) wafer having a semiconductor layer for element formation on an insulating layer, or gallium arsenide As described above, a compound semiconductor wafer may be used.

In the above description, the invention made mainly by the inventor has been described in terms of the DRA, which is a field of application in which the background was used.
M has been described as being applied to the manufacturing technology, but the present invention is not limited to this. For example, an SRAM (Static R)
andom Access Memory) or flash memory (EE
PROM: Electronically Erasable Programmable ROM)
And the like, and a memory-logic mixed circuit in which a semiconductor memory circuit and a logic circuit are provided on the same semiconductor substrate. Further, the present invention can be applied to a semiconductor device in which a bipolar transistor is provided on a semiconductor substrate.

[0035]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, no void is formed in the silicon oxide film buried in the groove, so that even if the surface of the silicon oxide film is flattened and the silicon oxide film is left inside the groove,
The surface becomes smooth, and no etching residue occurs when etching the film deposited on the silicon oxide film constituting the shallow groove isolation, so that the production yield can be prevented from lowering due to generation of voids.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing shallow groove isolation formed in an element isolation region of a DRAM according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing shallow groove isolation formed in an element isolation region of a DRAM according to an embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing shallow groove isolation formed in an element isolation region of a DRAM according to an embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing shallow trench isolation formed in an element isolation region of a DRAM according to an embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing shallow groove isolation formed in an element isolation region of a DRAM according to an embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing shallow groove isolation formed in an element isolation region of a DRAM according to an embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate showing a method for manufacturing shallow groove isolation formed in an element isolation region of a DRAM according to an embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing shallow groove isolation formed in an element isolation region of a DRAM according to an embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing shallow groove isolation formed in an element isolation region of a DRAM according to an embodiment of the present invention;

FIG. 10 is a graph showing a relationship between a length of a void generated in a silicon oxide film embedded in a groove and a heat treatment temperature.

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate for describing voids formed in shallow groove isolation;

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 silicon oxide film 3 silicon nitride film 4 photoresist film 5 element isolation groove (shallow groove isolation) 5a groove 6 silicon oxide film 7 silicon oxide film 8 silicon nitride film 9 photoresist film 10 n-type semiconductor region 11 p Type well 12 n-type well 13 gate oxide film 14A gate electrode 14B gate electrode 14C gate electrode 15 silicon nitride film 16 photoresist film WL word line L void length

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Akira Okawa 3-16-16 Shinmachi, Ome-shi, Tokyo F-term in the Hitachi, Ltd. Device Development Center Co., Ltd. 5F032 AA34 AA45 AA46 AA54 BA02 CA01 CA03 CA14 CA17 DA02 DA04 DA23 DA24 DA28 DA33 DA53 DA74 DA78 5F083 AD21 GA27 JA32 JA39 JA40 NA01 PR03 PR05 PR06 PR21 PR33 PR40 ZA03

Claims (9)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device in which shallow groove isolation is formed in an element isolation region on a main surface of a semiconductor substrate, comprising: (a) forming a groove in the semiconductor substrate in the element isolation region; (B) depositing a silicon oxide film on the semiconductor substrate by a chemical vapor deposition method using a gas for supplying silicon atoms and a gas for supplying oxygen atoms, and (c) And (d) flattening the surface of the silicon oxide film and leaving the silicon oxide film inside the groove. Of manufacturing a semiconductor integrated circuit device. 2. A method of manufacturing a semiconductor integrated circuit device, wherein shallow trench isolation is formed in an element isolation region on a main surface of a semiconductor substrate, the method comprising: (a) forming a first insulating film on a surface of the semiconductor substrate; Forming a second insulating film sequentially; and (b) sequentially etching the second insulating film, the first insulating film, and the semiconductor substrate in the device isolation region to form a second insulating film in the device isolation region. Forming a groove in the semiconductor substrate; (c).
After forming a relatively thin third insulating film on the inner wall of the trench, the semiconductor substrate is formed on the semiconductor substrate by a chemical vapor deposition method using a gas for supplying silicon atoms and a gas for supplying oxygen atoms. Depositing a silicon oxide film, and (d) subjecting the semiconductor substrate to a heat treatment under a high-temperature hydrostatic pressure; and (e).
After planarizing the surface of the silicon oxide film and leaving the silicon oxide film inside the trench, removing the second insulating film exposed on the surface of the semiconductor substrate, and then removing the second insulating film from the surface of the semiconductor substrate. Removing the exposed first insulating film. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the temperature of the heat treatment applied to the semiconductor substrate under a high hydrostatic pressure is equal to or higher than a glass softening point. A method for manufacturing a semiconductor integrated circuit device. 4. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein an atmosphere of the heat treatment performed on the semiconductor substrate under a high-temperature hydrostatic pressure is an inert gas atmosphere or an oxidizing atmosphere. A method for manufacturing a semiconductor integrated circuit device. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the silicon oxide film is formed by a chemical vapor deposition method under reduced pressure or under normal pressure or higher than atmospheric pressure. A method for manufacturing a semiconductor integrated circuit device, wherein the method is deposited on a semiconductor substrate. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the gas for supplying silicon atoms is an ethylsilicate or silane-based gas, and the gas for supplying oxygen atoms is: Ozone, oxygen,
A method for manufacturing a semiconductor integrated circuit device, wherein the device is N ₂ O, NO or H ₂ O ₂ . 7. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the surface of the silicon oxide film is planarized by a chemical mechanical polishing method, a dry etching method, or a wet etching method. A method for manufacturing a semiconductor integrated circuit device. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein said first insulating film is a silicon oxide film, said second insulating film is a silicon nitride film, and said third insulating film is A method for manufacturing a semiconductor integrated circuit device, wherein the film is a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 4, wherein alcohol or tetraethoxysilane is added to said inert gas atmosphere or said oxidizing atmosphere. Production method.