JP2000068233A - Thin film formation method - Google Patents

Abstract

(57) [Problem] To provide a method for forming a metal silicide film having good characteristics. SOLUTION: The acceleration voltage is set slightly higher than 24 keV, or the dose is set to 5 × 10 ¹⁵ ions / minute so that the phosphorus concentration on the surface of the amorphous silicon film 4 becomes 5% or less.
Ion implantation is performed with a size smaller than cm ² . Next, a Cr film 6 is formed on the amorphous silicon film 4, and a Cr silicide film 6A is formed at the interface between the amorphous silicon film 4 and the Cr film 6. Thereby, the characteristics (sheet resistance value) of the Cr silicide film 6A formed on the surface of the amorphous silicon film 4 can be controlled to 1 × 10 ⁷ (Ω / □) or less to obtain good characteristics. By forming source / drain electrodes on the Cr silicide film 6A, a TFT having good element characteristics can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for forming a thin film, and more particularly, to a method for controlling characteristics of a metal silicide film.

[0002]

2. Description of the Related Art As a conventional method of forming a thin film, there is a method of forming a chromium (Cr) silicide film interposed at an interface between an amorphous silicon film and a source / drain electrode in an inverted staggered thin film transistor (hereinafter referred to as TFT). is there. In order to form this Cr silicide film, phosphorus (P) or boron (B) ions are implanted in advance to form an n-type impurity diffusion region in the amorphous silicon film, and then a Cr film is formed on the surface of the amorphous silicon film. Is formed. After that, only the Cr film is etched so that the Cr silicide film formed by the reaction of silicon and Cr on the surface of the amorphous silicon film remains on the amorphous silicon layer. Further, C formed on the surface of the n-type impurity diffusion region of the amorphous silicon film
A TFT can be formed by forming source / drain electrodes on the r-silicide film.

[0003]

However, in the above-described conventional forming method, the electrical characteristics such as the surface resistance of the Cr silicide film formed on the surface of the amorphous silicon film greatly change depending on the ion implantation conditions. It has been pointed out that. For this reason, the characteristics of the TFT including the Cr silicide film also depend on the ion implantation conditions.

Conventionally, the relationship between the ion implantation conditions and the surface sheet resistance of the metal silicide film has not been clearly grasped. To form a metal silicide film having a desired surface sheet resistance, it is necessary to use an ion implantation method. A time-consuming method has been adopted in which injection conditions are experimentally changed to obtain optimum conditions. In addition, the concentration distribution of the ion-implanted impurity such as phosphorus in the depth direction varies depending on the ion implantation conditions, but a method for accurately evaluating the impurity concentration distribution has not been established. The present invention has been made in view of the above circumstances, and has as its object to provide a method for forming a thin film capable of controlling electric characteristics.

[0005]

According to the first aspect of the present invention,
A method of forming a thin film, comprising: ion-implanting an impurity into a semiconductor layer; forming a metal film on the semiconductor layer; and forming a metal silicide film at an interface between the metal film and the semiconductor layer. Is characterized by being selected according to the relationship between the impurity concentration implanted on the surface of the semiconductor layer and the sheet resistance of the metal silicide film.

Therefore, according to the present invention, the sheet resistance value of the metal silicide film to be formed can be determined by selecting the ion implantation conditions in advance, and a metal silicide film having good characteristics can be formed. it can.

According to a second aspect of the present invention, in the method of forming a thin film according to the first aspect, the semiconductor layer is an amorphous silicon film for forming a channel region of a thin film transistor, and the metal film is made of Cr. The impurity is an n-type impurity, and the implanted impurity concentration is set to 5% or less.

Therefore, according to the second aspect of the present invention, a TFT having a metal silicide film having good characteristics can be formed.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for forming a thin film according to the present invention will be described in detail. The inventor of the present invention ion-implants phosphorus (P), which is an n-type impurity, into an amorphous silicon film under various implantation conditions, then forms a Cr film on the amorphous silicon film, and at the interface between the amorphous silicon film and the Cr film. As a result of measuring the sheet resistance of the Cr silicide film formed by the reaction between silicon and Cr, the ion implantation conditions and C
It has been discovered that there is a correlation between the sheet resistance of the r-silicide film.

FIG. 8 shows the result of ion implantation of phosphorus into the amorphous silicon film by changing the implantation conditions, and measuring the phosphorus concentration in the depth direction by AES (Auger spectroscopy). As an injection condition, the accelerating voltage is 24 keV
At a dose of 3 × 10 ¹⁵ ions / cm ² and an acceleration voltage of 2
Dose 5 × 10 ¹⁵ ions / cm ² at 4 keV, the dose at an acceleration voltage of 10keV is 5 × 10 ¹⁵ ions / cm ²
Was set. From this result, it can be seen that the phosphorus concentration distribution and the phosphorus concentration on the outermost surface greatly differ depending on the acceleration voltage of the implanted ions and the amount of implanted ions during ion implantation. Specifically, the phosphorus concentration on the surface of the amorphous silicon film increases as the dose increases at the same acceleration voltage of 24 keV, and the phosphorus concentration on the surface of the amorphous silicon film increases as the acceleration voltage decreases at the same dose. It turns out that it becomes.

Further, the phosphorus concentration on the surface of the amorphous silicon film obtained by the difference between the various ion implantation conditions and the C concentration formed on the surface of the amorphous silicon film.
By examining the relationship between the sheet resistance of r-silicide and the relationship, the relationship shown in the graph of FIG. 9 can be obtained. That is, as shown in the figure, a C film is formed by ion-implanting phosphorus into an amorphous silicon film and then forming a Cr film.
It can be seen that the sheet resistance of r-silicide increases as the phosphorus concentration on the surface of the amorphous silicon film increases.

Therefore, utilizing the relationship shown in FIG. 9, it is possible to determine the ion implantation conditions for determining the surface concentration of phosphorus, which can obtain a Cr silicide film having desired characteristics (sheet resistance value). .

The correlation between the above-described ion implantation conditions and the sheet resistance of the Cr silicide film also indicates the relationship between the implantation conditions of impurity ions other than phosphorus (eg, boron) and the sheet resistance of the Cr silicide film. Can be applied.
Further, the silicide film required to have desired characteristics is not limited to the Cr silicide film described above, and various metal silicide films such as a titanium (Ti) silicide film and a tungsten (W) silicide film may be used. Can be applied.

Next, a method for forming a Cr silicide film having a desired sheet resistance based on the above-described correlation will be described.
An embodiment shown in FIGS. 1 to 5 applied to a manufacturing process of a TFT will be described. First, as shown in FIG. 1, after a gate electrode 2 made of an aluminum-based alloy is patterned on a glass substrate 1, a gate insulating film 3 made of silicon nitride (SiN) is deposited. Thereafter, an amorphous silicon film 4 is deposited on the gate insulating film 3, and the amorphous silicon film 4 is patterned so as to remain in an island shape above the gate electrode 2 to form a TFT semiconductor layer. Further, a silicon nitride film is deposited on the amorphous silicon film 4, and the silicon nitride film is patterned on the gate electrode 2 in a self-aligned manner to form a blocking layer 5.

Next, as shown in FIG. 2, phosphorus (P) ions are implanted. At this time, the blocking layer 5 serves as a phosphorus ion implantation stopper, and ion implantation is performed only on the exposed amorphous silicon film 4. The n-type T
In FT, it is desired in terms of characteristics that the sheet resistance value of a Cr silicide film formed in a later step is 1 × 10 ⁷ (Ω / □) or less. Therefore, in order to reduce the sheet resistance of the formed Cr silicide to 1 × 10 ⁷ (Ω / □) or less, it is necessary from FIG. 9 that the phosphorus concentration on the surface of the amorphous silicon film 4 be 5% or less. I understand. Therefore,
As shown in FIG. 8, ion implantation conditions may be determined so that the phosphorus concentration on the surface of the amorphous silicon film 4 is 5% or less. As can be seen from FIG.
When ions are implanted at a dose of 5 × 10 ¹⁵ ions / cm ² at V, the phosphorus concentration on the surface becomes about 5%. Therefore, the phosphorus concentration on the surface of the amorphous silicon film 4 can be set to 5% or less by slightly increasing the acceleration voltage from 24 keV or reducing the dose to less than 5 × 10 ¹⁵ ions / cm ² . In the present embodiment, the ion implantation conditions are determined in this manner. Specific ion implantation conditions include, for example, an acceleration voltage of 25 keV and a dose of 5 × 10 ¹⁵ ions / cm ² ,
The dose is set to 4 × 10 ¹⁵ ions / cm ² at keV.

Thereafter, as shown in FIG. 3, a Cr film 6 is deposited on the entire surface and a process is performed at a predetermined temperature. Then, as shown in FIG. 4, by removing the Cr film 6 by etching, the amorphous silicon film 4 and the Cr film 6 are removed.
The Cr silicide film 6A formed at the interface with the amorphous silicon film 4 remains. Note that the above-described etching is performed under the condition that a selectivity can be obtained with respect to Cr silicide.

Next, after depositing, for example, an aluminum alloy film as a source / drain metal on the entire surface, a source electrode 7S and a drain electrode 7D as shown in FIG. 5 are formed using photolithography and etching. Then, the manufacture of the TFT is completed.

In the TFT formed in this embodiment, the Cr silicide film 6A is selected by selecting phosphorus ion implantation conditions.
Because the characteristics (sheet resistance value) of are properly set,
A TFT having desired element characteristics can be formed.

In the TFT of the above embodiment, C
An aluminum-based alloy film was newly formed on the r-silicide film 6A to pattern-form the source / drain electrodes 7A and 7B. However, as shown in FIG. The film 6 may be patterned and left as source / drain electrodes. Further, as shown in FIG. 7, after depositing an electrode material film such as an aluminum alloy on the Cr film 6, the electrode material film and the Cr film are patterned to form a source electrode 7S and a drain electrode 7D. You may do so.

Although the embodiments have been described above, the present invention is not limited to these embodiments, and various changes accompanying the gist of the configuration are possible. For example, in the above embodiment, the present invention is applied to a TFT, but the present invention can be applied to a case where a MOS transistor is formed on a silicon substrate (wafer) or a self-aligned silicide (salicide) technique. .

In the present invention, ion implantation conditions for phosphorus ion implantation are selected. However, Cr silicide having appropriate characteristics by selecting ion implantation conditions for other impurity ions (for example, boron or the like) is selected. A film can also be formed. Further, the silicide is not limited to Cr silicide, and it goes without saying that the present invention can be applied to formation of metal silicide such as tungsten silicide and titanium silicide.

As is apparent from the above description, according to the present invention, a thin film having good characteristics can be formed, and the characteristics of the metal silicide can be controlled by selecting the ion implantation conditions for the underlying film. Can be.

[Brief description of the drawings]

FIG. 1 is a process sectional view of an embodiment of a thin film forming method according to the present invention.

FIG. 2 is a process cross-sectional view of the embodiment.

FIG. 3 is a process sectional view of the embodiment.

FIG. 4 is a process sectional view of the embodiment.

FIG. 5 is a process sectional view of the embodiment.

FIG. 6 is a sectional view showing a modification of the embodiment.

FIG. 7 is a sectional view showing a modification of the embodiment.

FIG. 8 is a graph showing the relationship between the depth of an amorphous silicon film and the phosphorus concentration.

FIG. 9 is a graph showing the relationship between the phosphorus concentration on the surface of an amorphous silicon film and the sheet resistance of a Cr silicide film formed on the amorphous silicon film.

[Explanation of symbols]

 Reference Signs List 4 amorphous silicon film 6 Cr film 6A Cr silicide film 7S source electrode 7D drain electrode

Claims (2)

[Claims] 1. After ion-implanting an impurity into a semiconductor layer,
A method for forming a thin film in which a metal film is formed on the semiconductor layer and a metal silicide film is formed at an interface between the metal film and the semiconductor layer, wherein the ion implantation conditions include: A method for forming a thin film, wherein the method is selected according to a relationship between an impurity concentration and a sheet resistance value of the metal silicide film. 2. The semiconductor layer is an amorphous silicon film for forming a channel region of a thin film transistor, the metal film is made of Cr, the impurity is an n-type impurity, and the concentration of the implanted impurity is 5% or less. 2. The method for forming a thin film according to claim 1, wherein: