JP2000068229A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: Provided is a semiconductor device which does not damage a semiconductor substrate even when overetching is performed when forming a contact opening, and a method for manufacturing the same. SOLUTION: A convex portion 1 on a surface of a single crystal silicon substrate 11 is provided.
A conductive polycrystalline silicon layer 12a as a buffer layer is formed between 1a and conductive layer 25. When the opening 24a is formed in the interlayer insulating film 24 by dry etching, even if overetching is performed, damage is absorbed by the polycrystalline silicon layer 12a. Therefore, the occurrence of damage on the surface of single crystal silicon substrate 11 can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a MOS (Me
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including a transistor of the type (tal Oxide Semiconductor) and a method of manufacturing the same, and more particularly to a semiconductor having a contact structure in which an impurity region in a semiconductor substrate is electrically connected to a conductive layer buried in an interlayer insulating film. The present invention relates to an apparatus and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, CMOS (Metal Oxide Semicond.
In a semiconductor device having an (uctor) structure, in each MOS transistor portion, an impurity region (source / drain) formed in a single crystal silicon substrate and an upper aluminum wiring are connected by, for example, BPSG (Boro-Phospho-Silicate Glass) or the like. (Contact hole) in the interlayer insulating film formed by the process
Are electrically connected via a conductive layer made of, for example, tungsten (W) buried therein. Here, the formation of the opening in the interlayer insulating film is usually performed by RIE (Reactive Ion Etc).
hing: reactive ion etching), etc., and an etcher for an interlayer insulating film (oxide film) has a high selectivity to single crystal silicon (for example, 1: 1).
0-20) are used.

FIG. 4 shows a state of an etching step of one of the CMOS transistors, for example, a p-channel MOS transistor. Here, LOCOS (Loc
al Oxidation of Silicon) film 102 is formed on the active region of the n-type single crystal silicon substrate 101 on which the gate oxide film 1 is formed.
The polycrystalline silicon film 104a doped with impurities and the compound alloy (silicide) film 10 with a high melting point metal such as tungsten are formed on the gate oxide film 103.
4b, and an oxide film (Si) is formed on the side wall surface of the gate electrode 104.
A gate side wall (side wall) 105 made of O ₂ ) is formed, and ions are implanted into the single-crystal silicon substrate 101 using the gate electrode 104 and the gate side wall 105 as a mask to form an LDD (Lightly Doped Drain) region 1.
Then, a p-type impurity region 107 serving as a source / drain is formed in a self-aligned manner adjacent to the semiconductor substrate 06.
An interlayer insulating film 108 made of BPSG is formed by a (Chemical Vapor Deposition) method. In this state, dry etching is performed using the photoresist film 109 as a mask, and an opening 108a reaching the impurity region 107 is formed in the interlayer insulating film 108. Thereafter, the single-crystal silicon substrate 1 including this opening 108a
01 as a barrier metal by CVD on the surface of
A film and a tungsten layer are sequentially formed.
A conductive layer (plug layer) is formed by flattening by P (Chemical and Mechanical Polishing) or the like.

[0004]

However, in the above-mentioned interlayer insulating film 108 made of BPSG or the like, since the reflow process is performed for planarization, there is a variation in film thickness and the like. In order to stably form, over-etching is necessarily required. Therefore, at present, the surface of the single crystal silicon substrate 101 is etched to some extent (30 to 50 nm).

However, according to such a conventional method, as shown by reference numeral 110 in the figure, the single-crystal silicon substrate 101 is damaged at the opening 108a during this over-etching. In particular, in recent years, MOS
-In the field of semiconductor manufacturing such as LSI (Large Scale Integrated circuit), miniaturization of elements has been progressing in accordance with the scaling law, and the depth of junctions (junction) between source / drain regions has also increased. For this reason, the occurrence of damage to the single crystal silicon substrate 101 in each opening 108a leads to an increase in junction leak, and is a phenomenon that cannot be ignored. Such a phenomenon occurs regardless of the normal transistor,
(Dynamic Random Access Memory) has the same problem in the contact take-out part of the access transistor. Therefore, a structure that does not scrape the single crystal silicon substrate 101 by over-etching is required.

The present invention has been made in view of the above problems, and has as its object to provide a semiconductor device which does not damage a semiconductor substrate even if overetching is performed when forming a contact opening. It is to provide a manufacturing method thereof.

A semiconductor device according to the present invention comprises a semiconductor substrate having an impurity region on a surface, an interlayer insulating film formed on the semiconductor substrate, and an interlayer insulating film formed on the interlayer insulating film so as to face the impurity region in the semiconductor substrate. Opening, a conductive layer embedded in the opening and electrically connected to the impurity region, and a conductive buffer layer interposed between the conductive layer and the impurity region in the semiconductor substrate. ing.

According to a method of manufacturing a semiconductor device according to the present invention, a step of forming a polycrystalline silicon layer on a semiconductor substrate and an oxidation-resistant pattern having at least a pattern corresponding to an opening for extracting an electrode on the polycrystalline silicon layer are provided. Forming a film;
Performing a selective oxidation of the polycrystalline silicon layer using the oxidation resistant film as a mask, forming an oxide film, and removing the oxide film,
Forming an impurity region in the semiconductor substrate by introducing an impurity into the semiconductor substrate and the polycrystalline silicon layer and forming a conductive buffer layer on the impurity region; and forming an interlayer insulating film on the surface of the semiconductor substrate. Forming an opening reaching the buffer layer in the interlayer insulating film, and burying a conductive material in the opening to form a conductive layer electrically connected to the impurity region through the buffer layer And

In the semiconductor device according to the present invention, a buffer layer is interposed between the impurity region and the conductive layer in the semiconductor substrate, and the impurity region and the conductive layer are electrically connected via the conductive buffer layer. Has a connected structure, even when performing over-etching when forming the contact opening,
Damage is absorbed in the buffer layer.

In the method of manufacturing a semiconductor device according to the present invention,
When an opening is formed in an interlayer insulating film by dry etching or the like, even if overetching is performed, damage is absorbed by the buffer layer, and no damage is caused on the surface of the semiconductor substrate.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

First, the structure of an n-channel MOS transistor according to an embodiment of the present invention will be described with reference to FIG. This MOS transistor is formed on the surface of an n-type single crystal silicon substrate 11 and is insulated and separated from an adjacent element by a thick element isolation film 17 made of a silicon oxide film (SiO ₂ ).

The MOS transistor has a pair of n ⁺ -type impurity regions 23, 23 serving as source / drain regions formed on the surface of the single crystal silicon substrate 11, and a region (channel region) between these n ⁺ -type impurity regions 23, 23. ), And is constituted by a gate electrode 19 provided opposite to the gate electrode 19.

The gate electrode 19 is formed on the gate insulating film 18 formed of, for example, a silicon oxide film. In the present embodiment, the gate electrode 19 is formed on the gate insulating film 18 and has a conductive polycrystalline silicon film 19a to which impurities such as phosphorus are added and a compound alloy (silicide) film of a refractory metal. 19b. As the refractory metal silicide, in addition to tungsten silicide using tungsten (W) as the refractory metal, cobalt (Co), titanium (Ti), nickel (Ni), platinum (Pt), molybdenum (Mo), etc. Silicide formed by using the above may be used.

On both side surfaces of the gate electrode 19 on the gate insulating film 18, gate side walls (sidewall films) 20 made of, for example, silicon dioxide (SiO ₂ ) are formed.
A pair of n ⁺ -type impurity regions 2 serving as source / drain regions
Reference numerals 3 and 23 are formed in a self-aligned manner using the gate side walls 20, respectively.

[0016] n ⁺ in the surface of the single crystal silicon substrate 11 between the impurity regions 23 and 23, in order to suppress the decrease hot carrier effects an electric field near the drain, an impurity than the n ⁺ -type impurity regions 23 and 23 The low-concentration and shallow n ^-- type LDD (Lightly Doped Drain) regions 22 and 22 have n ⁺
Mold impurity regions 23 are formed adjacent to each other.

In this embodiment, the single-crystal silicon substrate 1
1 has a structure in which the surface of each of the n ⁺ -type impurity regions 23, 23 is cut away except for a central portion (contact portion). In other words, each of the n ⁺ -type impurity regions 23 has a convex portion 11a at the center (contact portion). On the surface of the single crystal silicon substrate 11, an interlayer insulating film 24 made of BPSG or the like is formed. An opening 24a is formed in the interlayer insulating film 24 so as to face the protrusion 11a, and a Ti as a barrier metal is formed in the opening 24a.
A conductive layer (plug layer) 25 is formed by burying a film or the like and a tungsten layer.

In this embodiment, the single-crystal silicon substrate 1
Between the protrusion 11a and the conductive layer 25 of the first surface, the polycrystalline silicon layer 12a as a buffer layer is formed, n ⁺
Type impurity region 23 and conductive layer 25 have a structure electrically connected through polycrystalline silicon 12a. That is, the interlayer insulating film 24 is formed by dry etching.
Opening 24a formed in the single crystal silicon substrate 11
Has not been reached. Therefore, as will be described in a manufacturing process described later, the damage caused by performing the over-etching required in the dry etching is absorbed by the polycrystalline silicon layer 12a, so that the damage occurs on the surface of the single-crystal silicon substrate 11. There is nothing to do.

Next, this MO will be described with reference to FIGS.
A method for manufacturing the S transistor will be described.

First, as shown in FIG. 1A, a polycrystalline silicon layer 12 is formed on an n-type single crystal silicon substrate 11 by, for example, a CVD method using monosilane gas (SiH ₄ ) over the entire surface. The thickness of the polycrystalline silicon layer 12 is larger than the conventional over-etching amount, for example, 50 nm to 100 nm, so that the single crystal silicon substrate 11 is not scraped off during opening by etching described later. Next, for example, by a CVD method,
An oxide film 13 is formed as a buffer layer of m to 15 nm. Subsequently, a silicon nitride film (Si ₃ N
₄ ), and a photoresist film 15 having a pattern corresponding to the opening is formed on the silicon nitride film 14.

Using the photoresist film 15 as a mask, the silicon nitride film 14 is selectively etched. FIG.
(B) shows the state at this stage. In this embodiment, the oxide film 16 is formed by selectively oxidizing the polycrystalline silicon layer 12 using the silicon nitride film 14 as a mask in this state, as shown in FIG. At this time, the polycrystalline silicon layer 12a immediately below the silicon nitride film 14 remains without being oxidized. Oxide film 16
May be grown to a minimum oxidized amount such that polycrystalline silicon does not remain in the active region of the transistor. In the polycrystalline silicon layer 12, silicon (Si) is consumed for oxidation at a ratio of 6: 4, and here, an oxide film is grown to have a thickness of 200 nm or more.

Next, as shown in FIG. 2B, after the silicon nitride film 14 is removed by phosphoric acid wet etching or dry etching, the oxide film 16 is removed by phosphoric acid wet etching. As a result, the protrusions 11 a are formed in the regions corresponding to the openings of the single crystal silicon substrate 11.
Is formed, and the polycrystalline silicon layer 12a remains on the convex portion 11a.

Thereafter, a well region forming step similar to the conventional one (the description thereof is omitted here), a LOCOS isolation step, a gate oxidation step, a gate electrode forming step, an LDD region forming step, a source / drain region forming step, etc. Is formed by a CMOS process including

That is, as shown in FIG. 3A, a thick element isolation film 17 made of a silicon oxide film is selectively formed by, for example, the LOCOS method. Next, gate oxidation is performed on the surface of the single crystal silicon substrate 11 by a thermal oxidation method to form a gate insulating film 18 made of, for example, a silicon oxide film.

Subsequently, a polycrystalline silicon film 19a having a thickness of, for example, 150 nm is formed on the entire surface of the gate insulating film 18 by a CVD method using a monosilane gas (SiH ₄ ). Subsequently, a refractory metal layer such as tungsten (W) is formed on the polycrystalline silicon film 19a to a thickness of, for example, 100 nm.
Then, a silicide film 19b is formed by performing a heat treatment.

Subsequently, a photoresist film (not shown) of an electrode pattern is applied and formed on the silicide film 19a, and anisotropic etching by, eg, RIE is performed using the photoresist film as a mask, thereby forming the silicide film 19a and the polycrystalline film. The silicon film 19b is processed to form the gate electrode 1
9 is formed. Next, using the element isolation film 13 and the gate electrode as a mask, an n-type impurity, for example, arsenic (As) is ion-implanted (LDD-implanted) to form n ⁻ -type LDD regions 22 and 2.
Form 2 Subsequently, a silicon oxide film (not shown) is deposited on the entire surface of the single crystal silicon substrate 11 by, for example, a plasma CVD method to a thickness of 150 nm, and then the silicon oxide film is anisotropically etched (etched back) to form a gate electrode 19. Wide gate side wall (side wall)
20 is formed.

After the gate side wall 20 is formed, ions of an n-type impurity such as arsenic 21 are implanted using the gate electrode 19, the gate side wall 20 and the element isolation film 13 as a mask, and are deeper than the n ⁻ -type LDD regions 22 and 22. High-concentration n ⁺ -type impurity regions 23 having a junction depth are formed in a self-aligned manner. At this time, in the present embodiment, the polycrystalline silicon layers 12a, 12a formed in the step of FIG.
Is also performed, the resistance of the polycrystalline silicon layers 12a, 12a is reduced, and becomes a buffer layer at the time of etching as described later.

Subsequently, a heat treatment is performed to activate the impurities implanted into n ⁺ -type impurity region 23.

Next, as shown in FIG. 3B, an interlayer insulating film 24 made of, for example, BPSG is formed on the entire surface of the single-crystal silicon substrate 11 by, for example, a CVD method, and subsequently, the interlayer insulating film 24 is made by dry etching. N ⁺ impurity region 2
2 in the regions opposed to the polysilicon layers 12a,
Openings (contact holes) 24a, 2 reaching 12a
4a is formed. Subsequently, a laminated film (TiN / Ti) composed of a thin titanium nitride film and a titanium (Ti) film is selectively formed on the inner wall and the bottom of the openings 24a, 24a, and then a tungsten layer is formed in the openings 24a, 24a. To form a conductive layer (plug layer) 25. Subsequently, although not shown, a metal film, for example, a titanium film is formed on the single crystal silicon substrate 11 including the openings 24a, 24a, and an aluminum-based alloy such as aluminum (Al) containing silicon is formed on the titanium film. By forming a film and patterning, a wiring layer electrically connected to the conductive layer 25 is formed.

As described above, in the present embodiment, conductive polycrystalline silicon layer 12a as a buffer layer is formed between convex portion 11a on the surface of single crystal silicon substrate 11 and conductive layer 25. When the opening 24a is formed in the interlayer insulating film 24 by dry etching, even if overetching is performed, damage is not caused on the polycrystalline silicon layer 1.
Absorbed by 2a. Therefore, no damage occurs on the surface of the single crystal silicon substrate 11. Therefore, even if the device is miniaturized at a high density, the junction leak does not increase.

Although the present invention has been described with reference to the embodiment, the present invention is not limited to the above-described embodiment, and can be variously modified. For example, in the above embodiment, the semiconductor device to which the present invention is applied has been described as a CMOS transistor. However, the present invention can be applied to any semiconductor device in which a contact opening is formed through an etching process. You can do it.

[0032]

As described above, according to the semiconductor device of the present invention, the conductive buffer layer is interposed between the impurity region and the conductive layer in the semiconductor substrate, so that the impurity region and the conductive The layer has a structure electrically connected through the buffer layer. Therefore, even if over-etching is performed when forming a contact opening in the interlayer insulating film, the damage is absorbed in the buffer layer and does not reach the surface of the semiconductor substrate. Even in this case, it is possible to suppress the occurrence of junction leak, and to achieve an effect that a stabilized semiconductor device can be realized.

In the method of manufacturing a semiconductor device according to the present invention, a conductive buffer layer is previously formed between the impurity region in the semiconductor substrate and the conductive layer. Even if over-etching is performed when forming the contact opening, the damage is absorbed by the buffer layer, so that damage on the surface of the semiconductor substrate can be prevented.

[Brief description of the drawings]

FIG. 1 shows an n-channel MOS according to an embodiment of the present invention.
FIG. 14 is a cross-sectional view for describing the manufacturing process of the transistor.

FIG. 2 is a sectional view illustrating each manufacturing step following FIG. 1;

FIG. 3 is a sectional view illustrating each manufacturing step following FIG. 2;

FIG. 4 is a cross-sectional view for explaining a conventional MOS transistor manufacturing process.

[Explanation of symbols]

11: single crystal silicon substrate, 12: polycrystalline silicon layer,
12a: polycrystalline silicon layer (buffer layer), 13: silicon oxide film, 14: silicon nitride film, 19: gate electrode, 2
2 ... n ^- -type LDD region, 23 ... n ⁺ -type impurity regions (source and drain regions), 24 ... interlayer insulation film, 25 ... conductive layer

Claims (7)

[Claims] A semiconductor substrate having an impurity region on a surface thereof; an interlayer insulating film formed on the semiconductor substrate; and an opening formed in the interlayer insulating film so as to face the impurity region in the semiconductor substrate. A conductive layer embedded in the opening and electrically connected to the impurity region; and a conductive buffer layer interposed between the conductive layer and the impurity region in the semiconductor substrate. A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein said buffer layer is a polycrystalline silicon layer into which impurities are introduced. 3. The semiconductor device according to claim 2, wherein said semiconductor substrate is formed of single crystal silicon, and said impurity region is a source / drain region of a MOS transistor. 4. The semiconductor device according to claim 3, wherein a projection is formed in a region of said single crystal silicon substrate facing said opening, and said buffer layer is formed on said projection. . 5. A step of forming a polycrystalline silicon layer on a semiconductor substrate; and a step of forming an oxidation resistant film having a pattern corresponding to at least an opening for extracting an electrode on the polycrystalline silicon layer; Performing a selective oxidation of the polycrystalline silicon layer using the oxidation-resistant film as a mask to form an oxide film; and introducing an impurity into the semiconductor substrate and the polycrystalline silicon layer after removing the oxide film. Forming an impurity region in the semiconductor substrate and forming a conductive buffer layer on the impurity region; forming an interlayer insulating film on the surface of the semiconductor substrate; Forming an opening reaching the layer; and burying a conductive material in the opening to form a conductive layer electrically connected to the impurity region via the buffer layer. The method of manufacturing a semiconductor device according to claim and. 6. The method according to claim 5, wherein the opening is formed by dry etching. 7. The method of manufacturing a semiconductor device according to claim 5, wherein said semiconductor substrate is formed of single crystal silicon, and said impurity region is formed as a source / drain region of a MOS transistor. .