JP2000066845A - Disk array device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To provide a disk array device capable of preventing generation of overhead at the time of writing, guaranteeing real-time performance, and preventing performance degradation at the time of failure recovery. SOLUTION: This is a disk array device constituted by a plurality of HDDs 15 to 19 in a parallel redundant configuration, each of which has a retry temporary buffer memory 21 and a rebuild buffer memory 22 having a ring buffer structure, a striping / ECC block 7, and It manages the operation status and the processing time slot, and manages each of the memories 21 and 21.
And a CPU unit 5 for controlling the read / write operation of each HDD and the recording / reproducing operation of each HDD via the HDD control units 10-14.
Retry and rebuild the data using the data from.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk array device suitable for a so-called video server system for recording and reproducing moving images and audio signals, for example.

[0002]

2. Description of the Related Art For example, a disk array device configured in parallel with a plurality of HDDs (hard disk drives) generally has a RAID (Redundant Array of Inexpensi).
ve Disks).

FIG. 9 shows the concept of a disk array device called RAID.

In FIG. 9, the disk array device converts the input data 100 into data strings D0 to D0 for each predetermined unit length by the disk array controller 101.
D15 (striping), and the data strings D0 to D15 for each of the predetermined unit lengths are distributed to and stored in the plurality of HDDs 111 to 118 for each of the predetermined unit lengths.
The predetermined unit length is called a striping width,
A data string of the striping width for the number of data storage HDDs is called an array blocking factor (hereinafter, referred to as ABF).

Simultaneously with the striping, when dividing the input data, the disk array controller 101 generates an error correction code for a data string spanning a plurality of HDDs 111 to 118 and stores the error correction code in the HDD 119. I do. As described above, in the disk array device of FIG. 9, by storing an error correction code and performing error correction using the error correction code later, higher performance and reliability than in the case of a single HDD can be obtained. Has been realized. Note that Pn (n is 0 to 15) in FIG.
The error correction code for the n-th data string is shown. In the example of FIG. 9, the HDDs are HDDs 111 to 118 and 11
Although the number of nine is nine, the number may be more or less.

FIG. 10 shows the structure of a general disk array device.

In FIG. 10, a general disk array device includes a data input / output interface unit 13.
1, data cache unit (cache memory) 132,
CPU (central processing unit) 133, striping / E
CC unit 134, data timing controller 151,
A plurality of dedicated buffer memory units 135 to 138 for absorbing the asynchronousness between the HDDs, a plurality of data stream controllers 139 to 142, and a plurality of SCSI protocol controllers (hereinafter, referred to as SPCs) 143 to 14
6. It is composed of a plurality of HDD units 147 to 150.

The input data is sent to a striping / ECC unit 134 via an input / output interface unit 131 and a data cache unit 132.

The striping / ECC unit 134 divides (strips) the input data. The striped data is stored in buffer memories 135 to 135
137 and SPCs 143 to 145, and a plurality of HDs.
D units 147 to 149 are stored. Further, the striping / ECC unit 134 generates an error correction code for a data string spanning a plurality of HDD units 147 to 149 when dividing (striping) the data, and sends the error correction code to the HDD unit via the buffer memory 138 and the SPC 146. Fifteen
Store to 0.

Reading and writing of data to and from the HDD units 147 to 150 are performed by the buffer memory units 135 to 138 and the SPC1.
The reading and writing of data in the buffer memory units 135 to 138 and the SPCs 143 to 146 are controlled by the corresponding data stream controllers 139 to 142, respectively. Also, the data stream controllers 139 to 142
The striping / ECC unit 134 generates the data reading and writing timings in.

Although the HDD units 147 to 150 in the disk array device operate simultaneously, the start timing and the end timing of data transfer from the respective HDD units do not always coincide. For this reason, although not shown, buffer memory units 135 to 138 for absorbing the difference in timing are provided in HDD units 147 to 1.
It may be provided immediately after the SPCs 143 to 146 that control the 50.

The data timing controller 151 includes:
Timing control of data reading / writing to the input / output interface unit 131 and the data cache unit 13
2 timing control and striping / EC
The timing of reading and writing data from and to the C unit 134 is controlled.

The CPU 133 is connected to a CPU bus via a CPU bus.
I / O interface 131, striping / E
CC unit 134, data stream controller 139-
142, and controls the operations of the SPCs 143 to 146.

FIG. 11 shows the structure of R
1 shows a schematic configuration of a video server system using an AID disk array device as a storage medium for storing moving images and audio.

The video server system shown in FIG. 11 has a disk array device (hereinafter, referred to as a storage medium) as a storage medium.
RAID 129), a plurality of input / output devices 1
21 to 124 can be accessed by time division multiplexing. Hereinafter, the input / output devices 121 to 124 will be described.
These are referred to as IOPs (Input Output Processors) 121 to 124. Each of the IOPs 121 to 124 inputs and outputs video and audio data, and receives control from a higher-level application. These IOPs 121-
In accordance with the time slot generated by the time slot generation unit 125, the RAID 124 can be accessed by time division multiplexing via a data path. The data path may be an internal bus or SCSI (Smal
l Computer System Interface), a network such as a fiber channel, a so-called SBX bus, and the like.

[0016]

By the way, generally, in order to transfer a large amount of data such as a moving image and a sound at one time,
Although it is said that a disk array device having a so-called RAID-3 configuration is suitable, the disk array device has the following problems and cannot satisfy the performance required as a storage medium for a video server system.

As a first problem, overhead occurs at the time of writing.

That is, in the disk array device, overhead may occur at the time of writing, and the data to be rewritten depends on the ABF (array blocking factor).
If the data and parity are not exactly within the boundary of the data, it is necessary to read the data and parity before rewriting, calculate a new parity, and write the new parity.

As a second problem, the HDD alone does not guarantee real-time performance.

That is, the HDD itself is premised on retrying reading and writing, and it is difficult to secure real-time performance. For example, even if reading fails for some reason during data reading, the error correction function of the disk array device can ensure a certain degree of real-time performance. If performed, real-time performance cannot be ensured. Even if the retry of the HDD alone is simply prohibited, writing to the HDD may fail due to, for example, a shortage of time. In such a case, the writing failed, but the HDD itself is not defective. Therefore, the next time data is read from that portion, the error sign is not returned from the HDD, so that the error is not returned. ,
Unrelated data is read out, and as a result, data cannot be restored.

As a third problem, there is no mechanism for preventing performance degradation at the time of failure recovery.

That is, a general computer disk array device does not have a mechanism for preventing performance degradation at the time of failure recovery, and cannot read / write to the disk array at the time of data reconstruction (rebuild) for failure recovery. However, in a video server system, particularly in a broadcast video server system, it is necessary to minimize the deterioration of functions at the time of failure recovery.

As described above, in the conventional disk array device, due to the first and second problems, there is no guarantee that reading and writing are completed within a certain time. That is, since continuous reading and writing of data is not interrupted, it is not possible to further guarantee the synchronization and real-time performance of the video / audio input / output device that performs time-division multiple access. Generally,
It is said that it is necessary to increase the amount of the cache memory (data cache unit 132) in order to avoid the first and second problems. However, even if the amount of the cache memory is increased, a hit is always made. Because there is no guarantee, 100
It does not guarantee% real-time performance.

Accordingly, the present invention has been made in view of such a situation, and a disk capable of preventing generation of overhead at the time of writing, guaranteeing real-time performance, and preventing performance degradation at the time of failure recovery. An object is to provide an array device.

[0025]

A disk array device according to the present invention is a disk array device having a plurality of disk drives configured in parallel and redundantly, and has a first ring buffer structure for temporarily storing input data. Buffer memory, a second buffer memory having a ring buffer structure for temporarily holding output data, and sequentially dividing data and supplying the divided data to a plurality of disk drives. A data dividing / combining means for managing the operation status and processing time slot of the disk drive, and a control means for controlling the reading / writing of the first and second buffer memories and the recording / reproducing operation of the disk drive; Reconstruct data using data from first and second buffer memories using slots It allows to solve the problems described above to perform.

Further, the disk array device of the present invention is a disk array device having a plurality of disk drives configured in parallel and redundantly. The data is divided, supplied to the plurality of disk drives sequentially, and supplied from the plurality of disk drives. Data combining means for combining the recorded data, at least a pair of first-in first-out memories temporarily storing data to be recorded on the disk drive, and temporarily storing data reproduced from the disk drive Control means for managing at least a pair of second first-in first-out memories, operating conditions and processing time slots of the disk drive, and controlling recording / reproducing operations of the disk drive and bank switching of the first and second first-in-first-out memories , Using an empty time slot, and using first and second destinations. Re by performing data reconstruction using data from first-out memory, for solving the above problems.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described with reference to the drawings.

First, the first embodiment will be described.

In the first embodiment of the present invention, the size of a logical block is set to "1 sector (usually 512 bytes) .times.HD".
The transfer rate is prevented from being lowered by optimizing to an integral multiple of the "number of D" and matching the ABF (array blocking factor) with the size of the rewrite data to eliminate the overhead at the time of writing. This eliminates the need for a data cache to alleviate overhead during writing in this embodiment.

In the first embodiment of the present invention, H
Retries and reassignments of the DD alone are prohibited to ensure that reading and writing are completed within a certain period of time, thereby enabling continuous reading and writing of continuous data to be performed without interruption and time division multiplexing by multiple channels. Is guaranteed. That is, in this embodiment, for example, the CPU manages a location where an error has occurred during writing, and
By reconstructing the data later, it is possible to maintain the reliability of the data.

Further, in the first embodiment of the present invention,
In order to avoid a drop in the performance of failure recovery, a temporary buffer memory for retry and a buffer memory for rebuild described later are provided so that the data flow during normal operation and the data flow during failure recovery are separated. This makes it possible to quickly recover data in an HDD in which an error has occurred during writing by using a time slot for the system or a vacant time slot. This also makes it possible to increase the operational efficiency of such operations.

Hereinafter, the configuration and operation of the disk array device according to the first embodiment of the present invention will be described with reference to an example in which the disk array device is used as a storage medium of a video server system as shown in FIG. .

FIG. 1 shows a schematic configuration of a disk array device according to a first embodiment of the present invention.

In FIG. 1, the input / output interface unit 2 includes the disk array device of this embodiment and the IOPs 121 to IOP 121 of the video server system shown in FIG.
124, the transmission / reception of command / status and input / output data is controlled. The data input to the input / output interface unit 2 is striped through a selection switch 4 or a temporary buffer memory 21 for retry and a selection switch 4 described later.
It is sent to the ECC unit 7.

The striping / ECC unit 7 divides (strips) the input data. The striped data is stored in the HDD control units 10 to
13 are stored in a plurality of HDD units 15 to 18. Further, the striping / ECC unit 7 has a plurality of HDD units 15 when dividing (striping) data.
An error correction code is generated for a data string spanning from # 18 to # 18. This error correction code is stored in the HDD unit 19 via the HDD control unit 14.

Retry temporary buffer memory 21
The rebuild buffer memory 22 is provided for efficiently performing retry and rebuild in the disk array device of the present embodiment. The retry temporary buffer memory 21 has a ring buffer structure, in which data from the input / output interface unit 2 is written. On the other hand, the rebuild buffer memory 22 also has a ring buffer structure, in which data read from the HDDs 15 to 18 and error-corrected by the error correction code from the HDD unit 19 is written. The data from the retry temporary buffer memory 21 and the data from the rebuild buffer memory 22 are sent to the selection switch 4. Although details will be described later, in the present embodiment, for example, when an error occurs in reading or writing in each of the HDDs 15 to 19, an empty time slot is used to transfer data from the retry temporary buffer memory 21 or the rebuild buffer memory 22. Data to reconstruct (error recovery operation or rebuild operation). Note that the retry temporary buffer memory 21 and the rebuild buffer memory 22 are not so-called cache memories (data cache units 132) as shown in FIG. That is, the data stored in the retry temporary buffer memory 21 is a copy of the data sent from the input / output interface unit 2 to the selection switch 4, and the data stored in the rebuild buffer memory 22 is striping / ECC. This is a copy of the data sent from the unit 7 to the input / output interface unit 2, and does not require complicated control such as a cache hit as in the case of a so-called cache memory.

The data timing controller 3 controls data read / write timing in the input / output interface unit 2 and the striping / ECC unit 7.
, A data read / write timing control in the retry temporary buffer memory 21, a data read / write timing control in the rebuild buffer memory 22, and a striping / ECC unit from the input / output interface unit 2. 7 sent from the retry temporary buffer memory 21 to the striping / ECC unit 7 and data sent to the rebuild buffer memory 22 to the striping / ECC unit 7
The selection switch 4 controls the switching timing when data to be sent to the switch is selected by the selection switch 4.

The reading and writing of data to and from each of the HDD units 15 to 19 is performed through each of the HDD control units 10 to 14. The timing of reading and writing of data to and from each of the HDDs 15 to 19 by these HDD control units 10 to 14 is as follows. The striping / ECC unit 7 occurs.

The CPU unit 5 controls the operations of the input / output interface unit 2, the data timing controller 3, the striping / ECC unit 7, and the HDD control units 10 to 14 through the CPU bus. Also, C
The PU unit 5 transmits and receives commands and statuses to and from the IOPs 121 to 124 in FIG. 11 through the CPU bus and the input / output interface unit 2. Further, although details will be described later, when a write error occurs in each of the HDDs 15 to 19, the CPU unit 5 manages the error location of the HDD and reconstructs the data later.

Next, FIG. 2 shows the HDD control unit 1.
1 to 14 show configurations.

In FIG. 2, FIFO (first-in first-out) memories 4 for input and output are provided.
Reference numerals 3 and 44 are provided for temporarily storing data supplied from the striping / ECC unit 7 and data to be sent to the striping / ECC unit 7 and for absorbing the asynchrony of the HDD.

The SPC 42 is connected to the HD through a SCSI bus.
Control D.

The SPC 42 and the data stream controller 41 are connected to the CPU 5 of FIG.
Is controlled by

The data stream controller 41
Controls the timing of reading and writing data from and to the input FIFO memory 43 and the output FIFO memory 44 and the timing of reading and writing data from and to the SPC 42 according to the timing control from the striping / ECC unit 7.

Next, an example of a recovery operation at the time of a write error using the retry temporary buffer memory 21 will be described with reference to FIG. 3 and the configuration of the video server system of FIG.

Here, the disk array device of the present embodiment is accessed by time division multiplexing by the IOPs 121 to 124 in accordance with the time slots generated by the time slot generator 125 of the video server system of FIG. In the example of FIG. 3, each time slot is represented as a time slot TS1, TS2, TS3,...
It is accessed by time division multiplexing by four of P121 to 124 and five of one for the system. In the example of FIG. 3, the IOPs 121 to 124 of FIG.
It is assumed that data has been written to the unit. Under such conditions, for example, it is assumed that writing to the HDD unit has failed in the time slot TS3.

At this time, the CPU section 5 controls the HDD control section so as not to retry the HDD alone, and manages the location on the HDD section where the time slot TS3 was to be written. Also at this time C
The PU unit 5 holds the input data, that is, the data of the time slot TS3 when the writing to the HDD unit fails, without clearing the retry temporary buffer memory 21 via the data timing controller 3. Thereafter, the process proceeds to the next time slot TS4, where normal data reading and writing are performed.

Next, when there is a vacant time slot without a read / write request from the IOP, the CPU 5
Via the data timing controller 3, the selection switch 4 is controlled to switch the data flow,
The data from the retry temporary buffer memory 21 is sent to the striping / ECC unit 7, and the HDD control unit is further controlled to write (retry) again to the corresponding HDD unit. In the example of FIG.
A retry is performed in the system time slot TS7 as an empty time slot without a read / write request from P. Thereafter, the process proceeds to the next time slot TS8, where normal data reading and writing are performed.

Next, an example of a rebuild operation using the rebuild buffer memory 22 will be described with reference to FIG. 4 and the configuration of the video server system of FIG.

Here, when there is a vacant time slot without a read / write request from the IOP, the CPU unit 5
Reads the rebuild data from the HDD unit via the HDD control unit,
The controller 7 controls the C section 7 to correct errors in the rebuilding data read from the HDD section, and controls the data timing controller 3 to hold the rebuilding data after the error correction in the rebuilding buffer memory 22. In the example of FIG. 4, the rebuilding data is read from the HDD in the system time slot TS <b> 2 as an empty time slot without a read / write request from the IOP, and stored in the rebuilding buffer memory 22. Thereafter, the process proceeds to the next time slot TS4, where normal data reading and writing are performed.

Next, when there is a next vacant time slot for which there is no read / write request from the IOP, the CPU 5
Controls the data timing controller 3 to read out the rebuilding data held in the rebuilding buffer memory 22, and controls the selection switch 4 via the data timing controller 3 to switch the data flow. At the same time, the rebuilding data from the rebuilding buffer memory 22 is striped / ECC
The data is sent to the unit 7 to add the parity, and then the HDD control unit is controlled to write the rebuild data to the corresponding HDD unit. In the example of FIG. 4, the rebuild data is written to the HDD unit in the system time slot TS7 as the next vacant time slot without a read / write request from the IOP. Thereafter, the process proceeds to the next time slot TS8, where normal data reading and writing are performed.

In the present embodiment, the reason why the rebuild is performed in two time slots in this manner is that the seek time of the HDD is extremely longer than the actual read / write time of the HDD. If a rebuild operation is performed within one time slot, the amount of data that can be rebuilt at one time is reduced to about one tenth, which is extremely inefficient.

As described above, in the first embodiment of the present invention, the provision of the retry temporary buffer memory 21 and the rebuild buffer memory 22 allows the data flow during normal operation and the data flow during recovery from a failure. The flow can be separated. As a result, it is possible to prevent the failure recovery work from affecting reading and writing in a normal disk array device.

In the first embodiment, the data of the HDD can be efficiently reconstructed as described above.

Next, a second embodiment of the present invention will be described.

In the second embodiment of the present invention, the size of a logical block is optimally set to an integral multiple of “1 sector (usually 512 bytes) × the number of HDDs” as in the first embodiment. ABF (array blocking factor)
And the size of the rewrite data, thereby eliminating the overhead at the time of writing, thereby preventing a decrease in the transfer rate. As a result, in the second embodiment, the need for a data cache for reducing overhead during writing is eliminated.

Further, in the second embodiment of the present invention, similarly to the above-described first embodiment, retry and reassignment of the HDD alone are prohibited, and reading and writing are completed within a certain time. This guarantees continuous reading and writing of continuous data and time-division multiplexing with a plurality of channels.
That is, also in the second embodiment, the CPU manages the location where an error has occurred at the time of writing, and reconstructs the data later, thereby maintaining the reliability of the data.

Further, in the second embodiment of the present invention,
In order to avoid the performance degradation of the failure recovery, a plurality of sets of buffers for each HDD are prepared, and the data flow at the time of normal operation and the data flow at the time of the recovery from the failure are switched using a multiplexer. I use them properly. As a result, the write error H occurs.
Data restoration to DD can be quickly recovered by using a time slot for the system or a vacant time slot. For example, when the data is restored by replacing an HDD, the operation efficiency is improved. Is possible.

FIG. 5 shows a schematic configuration of a disk array device according to the second embodiment of the present invention. It should be noted that also in the second embodiment, the disk array device
A case where the storage medium is used as a storage medium of a video server system as shown in FIG. 1 will be described as an example. Hereinafter, in the second embodiment, a description will be given focusing on portions different from the above-described first embodiment.

In FIG. 1, the input / output interface unit 52 includes the disk array device of this embodiment and the IOPs 121 to 1 of the video server system shown in FIG.
24, the transmission / reception of command / status and input / output data is controlled. The data input to the input / output interface 52 is striping / ECC
It is sent to the unit 57.

The striping / ECC unit 57 divides (strips) the input data as in the case of the first embodiment. The striped data is stored in the plurality of HDD units 65 to 68 via the HDD control units 60 to 63. The striping / ECC unit 57 includes a plurality of HDD units 65.
An error correction code is generated for a data string spanning through # 68. This error correction code is stored in the HDD unit 69 via the HDD control unit 64.

The data timing controller 53 controls data read / write timing in the input / output interface unit 52 and performs striping / ECC.
The timing of reading and writing data in the unit 57 is controlled.

The reading and writing of data from and to the HDD units 65 to 69 are performed through the HDD control units 60 to 64. The timing of reading and writing of data to and from the HDDs 65 to 69 in the HDD control units 60 to 64 is as follows. The striping / ECC unit 57 occurs.

The CPU section 55 is provided with an input / output interface section 52, a data timing controller 53, a striping / ECC section 57,
The operation of the control units 60 to 64 is controlled.
Further, the CPU unit 55 is connected to the IOPs 121 to 1 of FIG.
24, a command and a status are transmitted and received. Further, when a write error occurs in the HDD unit, the CPU unit 55 manages an error location in the HDD unit and reconstructs data later.

Next, FIG. 6 shows the HDD control unit 6.
The configuration of 0 to 64 is shown.

Referring to FIG. 6, in the case of the present embodiment,
The HDD control units 60 to 64 are provided with an input FIFO.
O memory set of two or more (input FI in the example of FIG. 6)
FO memory 77-79), output FIFO
(In the example of FIG. 6, one set of the output FIFO memories 80 and 81). The reason for providing two or more sets of input FIFOs and two sets of output FIFOs in this way is to perform rebuilding efficiently as described later. That is, the input / output FIFOs 77 to 81 correspond to the striping / EC of FIG.
The data supplied from the C unit 57, the striping
This is for absorbing the data to be sent to the CC unit 57 and the asynchronousness of the HDD.

The selection switch 71 is used for striping and E
Input FIFO 77 to 7
8, and the selection switch 72 is a switch for switching any of the data in the output FIFOs 80 and 81 to the striping / ECC unit 75 and supplying the data.

The SPC 76 is connected to the H through the SCSI bus.
Control DD.

The SPC 76 and the data stream controller 75 are connected to the CPU 5 of FIG.
Is controlled by

The data stream controller 75
Are input FIFO memories 77 to 7 according to the timing control from the striping / ECC unit 57.
9 and the timing of reading and writing data from and to the output FIFO memories 80 and 81,
FO memory 77 to 79 and output FIFO memory 8
0, 81 bank switching control (selection switches 71, 7
2), and controls the timing of reading and writing data from and to the SPC 76.

According to the present embodiment, the configuration as shown in FIG. 5 and FIG. 6 described above makes it possible to increase the memory size compared to the cache memory of the data cache unit 132 of the conventional configuration shown in FIG. The speed is only 1 / the number of HDDs for storing data, the cost of the memory itself is low, and the circuit configuration can be simplified.

Next, an example of a write error recovery (system retry) operation in the configuration of the second embodiment will be described with reference to FIG. 7 and the configuration of the video server system of FIG.

In the second embodiment, similarly to the first embodiment, the time slots TS1, TS2, T2
S3,... Correspond to IOPs 121 to 124 in FIG.
And one for the system is accessed in time division multiplex. In the example of FIG. 7, each IOP 12 of FIG.
It is assumed that writing of data from 1-124 to the HDD unit of FIG. 5 is performed in the normal state, for example, through the input FIFO 77. Under such conditions, for example, it is assumed that writing to the HDD unit has failed in the time slot TS3.

At this time, the CPU 55 controls, via the HDD controller, not to retry the HDD alone, and manages the location on the HDD where the time slot TS3 was supposed to be written. At this time, the CPU 55 does not clear the data in the input FIFO 77 in the HDD control
Time slot TS3 when writing to the unit fails
Of data. Next, the CPU unit 55 controls the data stream controller 75 to start the SP from the next time slot TS4 via the input FIFO 78.
Data is sent to C76, and control is performed so that writing to the HDD unit is performed.

Thereafter, when there is a vacant time slot without a read / write request from the IOP, the CPU 55
Controls the data stream controller 75 to send data from the input FIFO 77 to the SPC 76,
The writing (retry) is performed again in the DD section. In the example of FIG. 7, a retry is performed in the system time slot TS7 as a vacant time slot without a read / write request from the IOP. After that, the CPU 55
Controls the data stream controller 75, sends data from the next time slot TS8 to the SPC 76 via the input FIFO 77, and controls writing to the HDD unit.

Next, an example of a rebuild operation in the second embodiment will be described with reference to FIG. 8 and the configuration of the video server system in FIG.

Here, reading of data from each of the IOPs 121 to 124 is performed in the normal state, for example, by using the output FIF.
It is assumed that the processing is performed through O80.

Under these conditions, when there is a vacant time slot for which there is no read / write request from the IOP, the CPU 55 causes the rebuild data to be read from the HDD via the SPC 76, 75, and the output FIFO 80 holds the rebuild data read from the HDD unit. In the example of FIG. 8, rebuild data is read from the HDD unit in the system time slot TS2 as an empty time slot without a read / write request from the IOP, and is held in the output FIFO 80.

Next, the CPU unit 55 controls the data stream controller 75 to execute the next time slot TS3.
Thereafter, control is performed so that data read from the HDD unit is transmitted to the IOP via the output FIFO 81.

Next, when there is a next vacant time slot without a read / write request from the IOP, the CPU 5
5 controls the data stream controller 75,
Reads the rebuild data from the output FIFO 80 and strips the rebuild data.
7 to add parity, and then control the data stream controller 75 to write the rebuilt data through the input FIFO 79 and further to the HDD unit via the SPC 76. In the example of FIG.
As the next vacant time slot without a read / write request from the OP, the system time slot TS7
The rebuild data already stored in the output FIFO 80 is read, and further written to the HDD unit through the input FIFO 79.

After that, the CPU 55 controls the data stream controller 75 to execute the next time slot TS.
From 8, control is performed so that the data read from the HDD unit is sent to the IOP via the output FIFO 80.

In the second embodiment, as in the first embodiment, the reason why rebuilding is performed in two time slots in this manner is as follows.
The seek time of D is extremely long with respect to the actual read / write time of the HDD, and when a rebuild operation is performed in one time slot, the amount of data that can be rebuilt at one time is reduced to about 1/10. This is because the efficiency becomes very low.

In the second embodiment, by preparing a plurality of sets of input and output FIFOs, the data flow during normal operation and the data flow during failure recovery can be separated. Like that. As a result, it is possible to prevent the failure recovery work from affecting reading and writing in a normal disk array device.

In the second embodiment, the data in the HDD can be efficiently reconstructed as described above.

That is, according to each of the embodiments of the present invention described above, by applying the disk array device to the video server system, the following (1) large capacity (2) high transfer Achieving a rate (3) High reliability (4) Good random access (5) Access to the same material from multiple channels simultaneously (6) No loss of data continuity (7) Efficient recovery at the time of failure recovery (8) It is possible to satisfy each performance such as the performance does not decrease at the time of failure recovery.

[0086]

As is apparent from the above description, in the disk array device of the present invention, the first and second buffer memories having a ring buffer structure for input data and output data, and the data are divided into a plurality of buffers. Data combining means for sequentially supplying data to a plurality of disk drives and combining data supplied from a plurality of disk drives, managing the operation status and processing time slots of the disk drives, reading / writing each buffer memory, and recording / reproducing the disk drives Having control means for controlling the operation, using empty time slots and reconstructing data using data from the first and second buffer memories, thereby preventing the occurrence of overhead during writing, In addition, real-time performance can be guaranteed, and it is possible to prevent performance degradation at the time of failure recovery.

Further, the disk array device of the present invention comprises a data dividing / combining means for dividing data, sequentially supplying the divided data to a plurality of disk drives, and combining the data supplied from the plurality of disk drives; A set of at least two sets of first and second first-in first-out memories for reproduction data, a bank for managing the operation status and processing time slot of the disk drive, and recording and reproducing operations of the disk drive and the first and second first-in first-out memories; Control means for performing switching control, and by using an empty time slot and reconstructing data by using data from the first and second first-in first-out memories, it is possible to prevent occurrence of overhead at the time of writing, , Real-time performance can be guaranteed, and performance degradation at the time of failure recovery can be prevented.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a schematic configuration of a disk array device according to a first embodiment of the present invention applicable to a video server system.

FIG. 2 shows H in the disk array device according to the first embodiment.
FIG. 3 is a block circuit diagram illustrating a schematic configuration of a DD control unit.

FIG. 3 is a diagram used to explain a recovery (retry) operation when a write error to an HDD occurs in the disk array device according to the first embodiment;

FIG. 4 is a diagram used for explaining a rebuild operation in the disk array device according to the first embodiment;

FIG. 5 is a block circuit diagram showing a schematic configuration of a disk array device according to a second embodiment of the present invention applicable to a video server system.

FIG. 6 shows H in the disk array device according to the second embodiment.
FIG. 3 is a block circuit diagram illustrating a schematic configuration of a DD control unit.

FIG. 7 is a diagram used to explain a recovery (retry) operation when a write error to an HDD occurs in the disk array device according to the second embodiment;

FIG. 8 is a diagram used for explaining a rebuild operation in the disk array device according to the second embodiment;

FIG. 9 is a diagram used to explain the concept of a disk array device.

FIG. 10 is a block circuit diagram showing a schematic configuration of a conventional general disk array device.

FIG. 11 is a block circuit diagram showing a schematic configuration of a video server system.

[Explanation of symbols]

2,52 input / output interface unit, 3,53 data timing controller, 4,71,72 selection switch, 5,55 CPU unit, 7,57 striping / ECC unit, 10-14, 60-64 HDD
Control part, 15-9,65-69 HDD part,
21 Temporary buffer memory for retry, 22
Buffer memory for rebuild, 43,77-79 Input FIFO, 44,80,81 Output FIFO, 41,75 Data stream controller, 42,76 SPC

Continued on the front page (72) Inventor Hiroyuki Fujita 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Satoshi Yoneya 6-35, 7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation Inside the company (72) Masakazu Yoshimoto 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation (72) Insider Satoshi Katsuo 6-35-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation (72) Inventor Jun Yoshikawa 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Sonny Corporation (72) Inventor Tomohisa Shiga 6-35-35 Kita-Shinagawa, Shinagawa-ku Tokyo ) Inventor Masaki Hirose 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation (72) Inventor Koichi Sato 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo F-term in Sony Corporation (reference) 5B065 BA01 CA30 CE12 EA03 5D044 BC01 CC04 CC09 DE94 GK11 HH07 HL01 HL11 5D066 AA02 BA06

Claims (8)

[Claims] 1. A disk array device comprising a plurality of disk drives configured in a parallel redundant configuration, a first buffer memory having a ring buffer structure for temporarily holding input data, and temporarily storing output data. A second buffer memory having a ring buffer structure for holding the data; a data dividing / combining means for dividing data and sequentially supplying the divided data to the plurality of disk drives; and combining data supplied from the plurality of disk drives; Control means for controlling the operation status and the processing time slot, and controlling the read / write of the first and second buffer memories and the recording / reproducing operation of the disk drive; Characterized in that the data is reconstructed using the data from the second buffer memory. Sukuarei apparatus. 2. The theoretical block size is calculated by multiplying a sector size ×
2. The disk array device according to claim 1, wherein the disk array device is optimized to an integral multiple of the number of disk drives. 3. The disk array device according to claim 1, wherein said control means prohibits retry and reassignment of the disk drive alone. 4. The disk array device according to claim 1, further comprising an input / output interface means of a server having a plurality of input / output means, the input / output interface means being time-division multiplexed access by said plurality of input / output devices. 5. A disk array device comprising a plurality of disk drives configured in a parallel redundant manner, dividing data and sequentially supplying the divided data to the plurality of disk drives, and combining the data supplied from the plurality of disk drives. Division / coupling means; at least a pair of first-in first-out memories temporarily storing data to be recorded in the disk drive; and at least two first-time memories temporarily storing data reproduced from the disk drive. A set of second first-in first-out memories, and control means for managing the operation status and processing time slot of the disk drive, and controlling the recording / reproducing operation of the disk drive and the bank switching of the first and second first-in first-out memories. Using the first time slot and the second time slot using empty time slots. Disk array device and performing data reconstruction using data from out memory. 6. The theoretical block size is calculated as: sector size ×
6. The disk array device according to claim 5, wherein optimization is performed to an integral multiple of the number of disk drives. 7. The disk array device according to claim 5, wherein said control means prohibits retry and reassignment of the disk drive alone. 8. The disk array device according to claim 5, further comprising an input / output interface unit of a server having a plurality of input / output units, the input / output interface unit being time-division multiplexed accessed by said plurality of input / output devices.