JP2000066760A - Circuit for saving power consumption - Google Patents

Abstract

PROBLEM TO BE SOLVED: To save power consumption at the time of power supply and to make a power source device small-sized by setting the frequency of a clock for driving a clock synchronizing semiconductor device to be lower than that at the time of a normal operation for a prescribed period at the time of supplying power by means of an output from a reset circuit. SOLUTION: A power consumption saving circuit is provided with a high speed clock oscillator 1 for a normal operation and a low speed clock oscillator 2 for saving power consumption. Then, a clock signal SDRAM CLK 6 to be supplied to a synchronous DRAM(SDRAM) 4 is changed-over to the side of a low speed clock for a prescribed time in a clock change-over circuit 3 by a power-on reset signal generated by the reset circuit 5 at the time of power supply. In this case, a clock enable signal CKE is naturally made to be active. Thus, SDRAM 4 is operated by the low speed clock signal for the prescribed time after power supply so that the power consumption of SDRAM 4 at the time of power supply is saved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a power consumption reducing circuit, and more particularly to a power consumption reducing circuit suitable for use in a synchronous semiconductor memory device.

[0002]

2. Description of the Related Art A clock synchronous dynamic random access memory (synchronous DRAM, hereinafter referred to as "SDR").
In order to reduce power consumption during operation, there is known a conventional memory device that uses, for example, an “AM” to reduce power consumption by operating a clock enable signal (CKE) of an SDRAM.

For example, Japanese Unexamined Patent Publication No. 9-180438 discloses that an SDRAM is used while an SDRAM is in an active state.
Control is performed so that the clock enable signal (CKE) is maintained in an inactive state except during the access period to the AM, and when the next access request to the SDRAM comes, the clock enable signal (CKE) is activated again. A memory control circuit that performs such control has been proposed. In this device, the power consumption of the SDRAM is reduced by partially setting the SDRAM in a power down mode during a normal operation. For example, Japanese Patent Application Laid-Open No. 8-87445 discloses that the refresh operation is not performed by fixing the clock enable (CKE) terminal of the SDRAM of a part of the banks to a fixed level so that the power down mode is not performed. There has been proposed a memory system in which power consumption is reduced.

[0004]

However, in the conventional memory control system proposed in Japanese Patent Application Laid-Open No. 9-180438, the power down function cannot be used when the power is turned on. Have a point.

That is, in the SDRAM, it is necessary to keep the clock enable signal (CKE) in an active state (for example, high level) and supply a clock in a power-on sequence at the time of power-on. ) As inactive and S
The DRAM cannot be put into the power down mode.
This will be described below with reference to the timing chart shown in FIG.

FIG. 7 shows a conventional SDRAM (for example, NEC
FIG. 11 is a timing chart showing an example of the operation of a power-on sequence of a μPD416421 manufactured by the company. 7, CLK is a clock signal, CKE is a clock enable signal, CS #, RAS #, CAS #, WE # are chip select, row address strobe, column address strobe, write enable, A10, A11, and AD are address signals, DQM is a data mask signal, DQ is output data, and the hatched portions in the figure are "undefined"
Indicates the state (Don't Care). In the SDRAM, a pause period (for example, 100 μs) is provided for a predetermined period after the power is turned on to stabilize the internal circuit, the bank is precharged by the precharge command, and after the precharge is completed, the mode register is set (register write command in the figure). Is performed.

It should be noted that, in FIG. 7, the clock enable signal CKE needs to be at a high level at times T0 to T1 (cycles between them are omitted), T2,. Clock C
LK needs to be supplied to the SDRAM. That is, in the first few clock cycles of the power-on reset sequence at power-on, the clock enable signal (CKE) is set inactive and the SDRAM is turned on.
Cannot be in power down mode.

When a large amount of SDRAMs are mounted on a storage device, when the power is turned on, all the SDRAMs are in a normal power consumption mode. Therefore, the power consumption of the storage device may exceed the power consumption during normal operation. is there. As a result, in order to cope with power consumption at the time of turning on the power, a power supply unit having a larger capacity is required, which makes it difficult to reduce the size of the device.

Recently, as the number of storage elements included in a storage device increases with the increase in the capacity of the storage device, the power consumption at the time of turning on the power determines the maximum power consumption value of the storage device. It has come to have a big influence on the design of the device, such as the increase in size and the price of the device.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and an object of the present invention is to provide a circuit for reducing power consumption of a clock synchronous semiconductor memory device when power is turned on.

[0011]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention relates to a clock synchronous semiconductor device, such as an SDRAM, which operates at a power-on by setting the operating clock frequency lower than the frequency during normal operation. Power consumption.

According to the present invention, the frequency of a clock signal supplied to a semiconductor device during a normal operation for a predetermined period during which a clock signal needs to be supplied at the time of startup before the semiconductor device starts a normal operation is provided. Means for controlling so as to supply a low-frequency clock signal is provided, and power consumption is reduced without stopping the clock at the time of starting.

[0013]

Embodiments of the present invention will be described. In a preferred embodiment of the present invention, referring to FIG. 1, a high-speed clock oscillator (1) for normal operation and a low-speed clock oscillator (2) for reducing power consumption
The clock switching circuit (3) uses the power-on reset signal generated by the reset circuit (5) at power-on to cause the clock switching circuit (3) to change the clock signal SDRAM CLK (6) to be supplied to the SDRAM (4) to a low-speed clock. Side for a predetermined time. In the embodiment of the present invention, it goes without saying that the clock enable signal (CKE) is active during this predetermined period when the power is turned on.

As described above, in the embodiment of the present invention, the SDRAM (4) operates with the low-speed clock signal for a certain time after the power is turned on.
4 can be reduced. Hereinafter, a detailed description will be given in accordance with embodiments.

[0015]

FIG. 2 is a diagram showing the configuration of an embodiment of the present invention. Referring to FIG. 2, the clock switching circuit 3 includes:
An input signal from the high-speed clock oscillator 1 and an input signal from the low-speed clock oscillator 2 are selected based on the logical value of the power-on reset signal 8, and the selected signals are output to a plurality of SDRAs.
Clock SDRAM CLK6 to M (# 1 to #n) 4
Output as

In one embodiment of the present invention, the high-speed clock oscillator 1 and the low-speed clock oscillator 2 can be constituted by, for example, crystal oscillation circuits, and are provided with a multiplying circuit or a dividing circuit as required. You.

The plurality of SDRAMs (# 1 to #n) 4 are SDRAM CLs output from the clock switching circuit 3.
It operates using K6 as an operation clock.

When the power is turned on, the reset circuit 5 detects that the power supply voltage has become equal to or higher than a predetermined constant value,
From that point, a signal of logic 0 is output for a predetermined time Y [ms]. The reset circuit 5 includes a comparator that compares power supply potential with a predetermined reference potential and detects power-on, and a known circuit that generates a one-shot pulse signal for a predetermined time based on a detection result of the comparator. In FIG. 1, it is composed of an integrated circuit (IC). The signal from the reset circuit 5 is inverted by an inverter 7 to output a power-on reset signal 8, which is input to the clock switching circuit 3.

The clock switching circuit 3 selects and outputs an input signal from the low-speed clock oscillator 2 while the power-on reset signal 8 is at logic 1 and outputs the low-speed clock to the SDRAM C.
It is supplied to the SDRAM 4 as LK6.

FIGS. 3A and 3B are signal waveform diagrams for explaining the operation of the embodiment of the present invention. FIG. 3A shows the power supply voltage when the power is turned on, and FIG. , FIG.
(C) is a diagram showing a signal waveform of the power-on reset signal 8, respectively. When the power supply voltage V changes from the low level to the high level when the power is turned on, the output signal of the reset circuit 5 is at the low level for Y [ms]. At this time, the power-on reset signal 8 is at a high level for Y [ms]. The power-on reset signal 8 is used as a reset (initialization) signal at power-on in another circuit (not shown). In addition, this Y when power is turned on
During [ms], the clock enable signal (CKE) terminal of the SDRAM 4 is kept active.

FIG. 4 is a diagram for explaining one embodiment of the present invention. In the clock switching circuit 3, the value of the power-on reset signal 8, which is a selection signal, and the input signal from the high-speed clock oscillator 1 are shown. 5 is a truth table illustrating an example of a relationship between selected states of an input signal from a low-speed clock oscillator 2. The clock switching circuit 3 is composed of a selector circuit that operates the truth table. When the power-on reset 8 is logic 0, the SDRAM CLK6 becomes the output signal of the high-speed clock oscillator 1, and when the power-on reset 8 is logic 1, the SDRAM CLK6 becomes the output signal of the low-speed clock oscillator 2. In the clock switching circuit 3, the switching from the low-speed clock to the high-speed clock is performed when the power-on reset signal 8 changes from logic 1 to logic 0, and this switching time (Y [m in FIG.
At [s], the SDRAM 4 has not yet started the normal operation, so that there is no problem even if the clock phase / timing adjustment is not performed.

As an example, the selector circuit constituting the clock switching circuit 3 may be constituted by two three-state buffers in which the outputs of the high-speed clock oscillator 1 and the low-speed clock oscillator 2 are input and the outputs are connected in a wired manner. In this case, the power-on reset signal 8 and its inverted signal are supplied to the output enable control terminals of the two three-state buffers, respectively, and the low-speed clock oscillator 2 is input when the power-on reset signal 8 is active. Only the state buffer is in the output enable state.

Next, the operation of one embodiment of the present invention will be described. When the power is turned on, as shown in FIG. At this time, the clock switching circuit 3
The value of the low-speed clock oscillator 2 is output as the DRAM CLK6, and the SDRAM 4 operates with the low-speed clock.

Then, after Y [ms] from the power-on time, the power-on reset signal 8 becomes logic 0, and at this time, the clock switching circuit 3 sets the SDRAM CLK6
And outputs the value of the high-speed clock oscillator 1. SDRA
M4 operates with a high-speed clock.

Next, a second embodiment of the present invention will be described. FIG. 5 is a diagram showing the configuration of the second embodiment of the present invention. Referring to FIG. 5, in the second embodiment of the present invention, a PLL (phase locked loop) circuit 9 is provided between the clock switching circuit 3 and the SDRAM 4. The PLL (phase locked loop) circuit 9 includes, for example, a phase difference detection circuit that detects a phase difference between an output of a voltage controlled oscillator (VCO) and an input signal, a charge pump, and a loop filter. Is VC
O is supplied as a control voltage that determines the oscillation frequency of O, and VC
The oscillation output of O is fed back to the phase difference detection circuit. The PLL circuit 9 further has a control terminal for inputting a PLL through signal 10. When the PLL through signal 10 is activated, the PLL circuit 9 does not perform a phase synchronization operation. , And is bypassed to a path for outputting the input signal to the output terminal as it is. For example, an MPC990 (PLL clock driver) manufactured by Motorola is referred to as a PLL circuit having a PLL through function of this type.

That is, the PLL circuit 9 inputs the power-on reset 8 as the PLL through signal 10, and when the PLL through signal 10 is logic 1, the PLL 9 is in the PLL through mode.

The SDRAM clock becomes faster,
When the number of SDRAMs for distributing the DRAM clock increases, a synchronous circuit such as a PLL circuit or a DLL (Delay Locked Loop) is required to supply a stable clock signal. The operating frequency band of the PLL circuit is limited, and when using a clock with a frequency outside this limit, it is necessary to set the PLL circuit to the PLL through mode.

In the second embodiment of the present invention, when the clock from the low-speed clock oscillator 2 is used, the PLL through signal 10 of the PLL 9 is set to logic 1 and the low-speed clock oscillator 2 is set to the PLL through mode. It can operate even when the frequency is out of the operation range of the PLL circuit 9. That is, an apparatus using a PLL circuit for clock distribution to the SDRAM 4 can operate with a low-speed clock outside the PLL operation range.

Next, a third embodiment of the present invention will be described. FIG. 6 is a diagram showing the configuration of the third embodiment of the present invention. Referring to FIG. 6, a third embodiment of the present invention is the same as that shown in FIG. 1 except that SDRAM 4 shown in FIG. 1 is replaced by a logic (logic) integrated circuit 4 '. The same applies. As described above, the present invention is not limited to the clock synchronous semiconductor memory device, but can be applied to a logic circuit driven by a clock. The logic integrated circuit 4 'supplies a clock for several cycles at the time of power-on, and then starts a predetermined reset sequence. In the third embodiment of the present invention, the initial clock cycle at power-on is driven by the clock from the low-speed clock oscillator 2 to reduce power consumption.

In the above embodiment, the power-on reset signal output from the reset circuit 5 is a low active signal (active state at logic 0), and a signal obtained by inverting this signal with an inverter 7 is used as a power-on reset signal. Although the configuration in which the switching signal is input as the selection signal of the switching circuit 3 has been described as an example, the logical value of the output from the reset circuit 5 is not limited to the above configuration, and the power-on reset signal from the reset circuit 5 is set to High active (Active state with logic 1), the inverter is not required, and the logic for selecting the clock switching circuit 3 is not limited to the logic of the truth table shown in FIG. It is.

In the present invention, it is needless to say that the clock switching circuit 3 may be provided inside the SDRAM or the logic integrated circuit.

Further, in the present invention, the configurations of the high-speed clock oscillator 1, the low-speed clock oscillator 2, and the clock switching circuit 3 for supplying a clock during normal operation are, for example,
It is composed of a high-speed clock oscillator 1 that supplies a clock during normal operation, a frequency dividing circuit, and a selector. When a power-on reset signal is active at power-on, the selector divides the output of the high-speed clock oscillator 1 by the frequency dividing circuit. A configuration may be adopted in which the output of the high-speed clock oscillator 1 is output as it is when the power-on reset signal becomes inactive. For example, a clock of 100 MHz is supplied during normal operation, and 50 MHz or 25 MHz obtained by dividing the frequency by 2 or 4 when the power is turned on.
This configuration can be applied, for example, when driving is performed by using. If the frequency of the clock output from the low-speed clock oscillator 2 is lower than the frequency of the clock output from the high-speed clock oscillator 1, any frequency within the allowable operation range of the SDRAM or the like is set, and For the reduction, a low-speed clock within the operable range of the device is used.

[0033]

As described above, according to the present invention,
The following effects are obtained.

A first effect of the present invention is that power consumption at the time of turning on the power can be reduced, so that the power supply device can be downsized.

The reason is that, in the present invention, the operating clock frequency of the SDRAM when the power is turned on is set low.

A second effect of the present invention is that an increase in the circuit scale can be suppressed and reduced, so that the size and cost of the device can be reduced.

The reason is that, in the present invention, the power-on reset signal is used for switching the clock.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of one embodiment of the present invention.

FIG. 3 is a signal waveform diagram for explaining the operation of one embodiment of the present invention.

FIG. 4 is a diagram for explaining the operation of the embodiment of the present invention, and is a truth table for explaining the operation of the clock switching circuit.

FIG. 5 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 7 is a timing chart showing an example of a power-on reset sequence of the SDRAM.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 High-speed clock oscillator 2 Low-speed clock oscillator 3 Clock switching circuit 4 Synchronous DRAM 4 'Logic integrated circuit 5 Reset circuit 6 Clock to synchronous DRAM 7 Inverter 8 Power-on reset signal 9 PLL 10 PLL through signal

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[Procedure amendment]

[Submission date] July 19, 1999 (1999.7.1)
9)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction contents]

[0011]

In order to achieve the above object, the present invention detects a power-on and outputs a power-on reset signal.
Output from the reset circuit to
A clock that drives a clock synchronous semiconductor device for a fixed period
Switching the frequency of the, as set lower to than in normal operation
A control means is provided to reduce power consumption at power-on.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction contents]

According to the present invention, power-on is detected for the semiconductor device during a predetermined period during which the supply of a clock signal is required at the time of startup before the semiconductor device starts normal operation.
Reset circuit that outputs a power-on reset signal
By means of these outputs, there is provided means for switching control so as to supply a clock signal having a frequency lower than the frequency of the clock signal supplied during normal operation , so as to reduce power consumption without stopping the clock at the time of starting. Things.

Claims (11)

[Claims] 1. A power consumption reducing circuit, comprising: means for switching when power is turned on so that the frequency of a clock for driving a clock synchronous semiconductor device is set lower than in normal operation. 2. The switching control according to claim 1, wherein said clock frequency is made lower than that in a normal operation by an output from a reset circuit which outputs a power-on reset signal upon detecting power-on. Power consumption reduction circuit. 3. A first circuit for generating a clock signal during a normal operation.
Clock generating means, and second clock generating means for generating a clock lower in speed than the first clock generating means. A clock for driving the clock-synchronous semiconductor device according to (1), which is supplied from the second clock generating means, and thereafter, is controlled to switch to an output from the first clock generating means. Power reduction circuit. 4. A power consumption reduction circuit comprising: a switching control means for setting a frequency of a clock for driving a clock synchronous semiconductor memory device at power-on so as to be set lower than that in a normal operation. 5. The switching control so that the clock frequency is made lower than that in a normal operation by an output from a reset circuit which detects power-on and outputs a power-on reset signal. Power consumption reduction circuit. 6. A first circuit for generating a clock signal during a normal operation.
Clock generating means, and second clock generating means for generating a clock lower in speed than the first clock generating means. Means for supplying a clock for driving the clock synchronous semiconductor memory device from the second clock generation means, and thereafter switching the output to the output from the first clock generation means. Power consumption reduction circuit. 7. A first clock generating means for generating and outputting a clock signal to be supplied to a clock synchronous semiconductor memory device during a normal operation; and a clock signal lower in speed than the clock signal output from said first clock generating means. And a reset which receives an output of the first clock generating means and an output of the second clock generating means, monitors a power supply potential, and generates a power-on reset signal. The power-on reset signal output from the circuit as a selection signal,
A clock switching circuit for selectively outputting one of the output of the first clock generating means and the output of the second clock generating means, wherein the clock switching circuit activates the power-on reset signal. A power supply reducing circuit for supplying an output of the second clock generating means as a clock signal to the synchronous semiconductor memory device. 8. A PL between an output of the clock switching circuit and a clock input terminal of the clock synchronous semiconductor memory device.
An L circuit, the power-on reset signal is also input to a control terminal of the PLL circuit as a PLL through control signal, and the second circuit selected by the clock switching circuit when the power-on reset signal is activated. 8. The power consumption reducing circuit according to claim 7, wherein an output from a clock generating means is supplied as a clock signal to said synchronous semiconductor memory device through said PLL circuit. 9. A frequency lower than a frequency of a clock signal supplied to a semiconductor device during a normal operation for a predetermined period during which a clock signal is required to be supplied at a start-up time before the semiconductor device starts a normal operation. A power consumption reducing circuit, comprising: means for controlling so as to supply a clock signal, and reducing power consumption without stopping the clock at the time of the start-up. 10. The power consumption reducing circuit according to claim 9, wherein said semiconductor device comprises a clock synchronous semiconductor memory device. 11. The power consumption reduction circuit according to claim 9, wherein said semiconductor device comprises a semiconductor logic integrated circuit device.