JP2000060114A - Dc-to-dc converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve efficiency and enlarge the control range of an output voltage by shortening the rise time of a gate control voltage waveform of an FET of the last stage of a DC/DC converter output circuit, and reducing the loss of an FET for output. SOLUTION: A converter using a positive side DC/DC converter output circuit 36' is used in an amplifier circuit. The output circuit 36' is provided with a gate voltage waveform rise speed-up circuit 40, whose input signal is a switching signal outputted from an IC 32 for a DC/DC converter. That is, this speed-up circuit is provided with an FET Q5, and the differential waveform of a voltage waveform of a switching signal outputted from the IC 32 for the DC/DC converter is inputted to the gate of the FET Q5. The drain voltage waveform of the FET Q5 and the drain voltage waveform of an FET Q1 are combined, and a gate control voltage waveform of an FET Q4 of the last stage of the positive side DC/DC converter output circuit 36' can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a DC-DC converter, and more particularly, to a DC-DC converter suitable for use in an amplifier circuit used for power amplification of an audio signal or the like.
A converter, particularly a DC-DC converter for improving the efficiency of the final stage FET of the output circuit and expanding the control range of the output voltage.
It relates to a DC converter.

[0002]

2. Description of the Related Art Conventionally, among amplifier circuits for amplifying an audio signal, an amplifier circuit having a circuit configuration shown in FIG. 1 is known as an amplifier circuit for which high efficiency is achieved by using a DC-DC converter. ing.

This amplifier circuit inputs a signal (audio input signal) output from a signal source 10 to a power amplifier 12, amplifies an input signal in a voltage amplifier circuit 14 of the power amplifier 12, and outputs a signal to an output stage of the power amplifier 12. By driving the + side power transistor 16 and the − side power transistor 18 which are transistors, necessary power is supplied to the speaker 20 which is a load.

The power supply voltage + B generated by the power supply 22 for driving the + power transistor 16 is supplied by a + power supply DC-DC converter 24 connected between the power supply 22 and the + power transistor 16. Be lowered. That is, the + -side power transistor 16 is driven by lowering the power supply voltage + B by the + -side power supply DC-DC converter 24.

Similarly, a power supply voltage B generated by the power supply 26 for driving the negative power transistor 18 is supplied to a DC power supply DC-DC converter 28 connected between the power supply 26 and the negative power transistor 18. Is reduced by That is, the power supply voltage -B is reduced by the DC power supply 28 for the negative side power supply to drive the negative side power transistor 18.

That is, in the conventional amplifier circuit shown in FIG. 1, the power supply voltage + B and the power supply voltage -B are respectively used by using the + side power supply DC-DC converter 24 and the-side power supply DC-DC converter 28. By driving the power amplifier 12 while reducing the power loss, the loss due to heat generation in the power amplifier 12 is reduced while achieving high efficiency.

Here, the DC-DC converter 24 for the + side power supply and the DC-DC converter 28 for the − side power supply have an ON / OFF ratio variable according to the output of the power amplifier 12 (control input by the control voltage). It switches.

FIG. 2 is a block diagram of a conventional DC-DC converter which is used as the DC-DC converter 24 for the + side power supply, of the converters for the + and-power supplies. The conventional DC-DC converter includes a DC-DC converter control signal generation circuit 3 to which an output from the power amplifier 12 is supplied as an input signal.
0 and the DC-DC converter IC 32 to which the output signal of the DC-DC converter control signal generation circuit 30 is input.
And a DC-DC converter output circuit 34 to which an output signal of the DC-DC converter IC 32 is input. The output of the DC-DC converter output circuit 34 is used as an output signal of the DC-DC converter. It is taken out and supplied to the power amplifier 12, and DC-DC
Negative feedback (NF: negative feedback) is provided to the converter control signal generation circuit 30.

FIG. 3 shows voltage waveforms at various parts of the conventional DC-DC converter (FIG. 2). Referring to FIG. 3, the conventional DC-DC converter (FIG. 2) Will be described.

First, at a point A, a voltage waveform of an output from the power amplifier 12 is given as a voltage waveform of an input signal to the DC-DC converter control signal generation circuit 30, and the waveform is, for example, It is a sine wave.

The DC-DC converter control signal generation circuit 30 rectifies and inverts the input signal having the waveform shown at point A, shifts DC, and outputs it to point C. D
The C-DC converter IC 32 receives the signal of the waveform at the point C and generates a switching signal as shown at the point D. Further, the DC-DC converter output circuit 34 outputs
The switching signal at the point is input, and an output signal having a voltage waveform for driving the power amplifier 12 shown at the point E is generated.

The DC-DC converter output circuit 34
Is output to the DC-DC converter control signal generation circuit 30 as described above, with negative feedback (NF:
Negative feedback).

In FIG. 4, a large amplitude signal having a frequency of 1 kHz is output from a signal source 10 and input to an amplifier 12 of an amplifier circuit (FIG. 1) using a conventional DC-DC converter (FIG. 2). FIG. 4 shows voltage waveforms at various points in the amplifier circuit shown in FIG. 1 at this time, and the operation of the amplifier circuit shown in FIG.

That is, in the + side circuit, the + side power supply D
The C-DC converter 24 variably switches the on / off ratio by a switching signal (voltage waveform at point D in FIG. 3) according to the output (control input by the control voltage) of the power amplifier 12, so that the power supply voltage + B ( A) is reduced to a voltage (B) necessary and sufficient to extract necessary power from the power amplifier 12.

On the negative side, a DC power supply for the negative side
The DC converter 28 switches the ON / OFF ratio variably by a switching signal according to the output (control input by the control voltage) of the power amplifier 12, and the power supply voltage −B (E) is changed from the power amplifier 12 to the required power. The voltage (D) required and sufficient to take out is reduced.

That is, according to this amplifier circuit, as shown in FIG. 4, the output voltage (B) of the DC-DC converter 24 for the + power supply and the output voltage (D) of the DC-DC converter 28 for the-power supply. Is changed following the output voltage (C) of the power amplifier 12, so that loss due to heat of the power transistor in the power amplifier 12 can be greatly reduced regardless of the magnitude of the output of the power amplifier 12. it can.

Also, a DC-DC converter 2 for the + side power supply
Since the DC-DC converter 4 and the-side power supply DC-DC converter 28 perform the switching drive as described above, the loss here is also small, and the efficiency of the whole amplifier circuit is extremely high.

However, the DC-D converter 24 used as the DC-DC converter 24 for the + power supply and the DC-DC converter 28 for the-power supply in the amplifier circuit described above.
The C converter has a problem that it is very difficult to control the output voltage from a low voltage to a high voltage with high accuracy and high efficiency.

That is, in the conventional DC-DC converter, the fall of the gate control voltage waveform of the FET Q4 at the last stage of the output circuit 34 is fast, but the rise at the gate of the FET Q4 is slow. This causes a problem that the efficiency is deteriorated due to an increase in the allowable loss of Q4 and a duty control range (variable range) of the DC-DC converter is narrowed. The above phenomenon will be described in detail below.

FIG. 5 is a detailed circuit diagram of a + side circuit portion (hereinafter referred to as a "+ side DC-DC converter output circuit") 36 of the conventional DC-DC converter output circuit 34 in the DC-DC converter. FIG. 6 shows voltage waveforms at various parts of the conventional + side DC-DC converter output circuit 36 (FIG. 5), and FIG. 5 is referred to FIG. 5 and FIG. Conventional + side DC-D
The operation of the C converter output circuit 36 will be described.

The negative circuit portion of the conventional DC-DC converter output circuit 34 in the DC-DC converter is configured in the same manner as the positive DC-DC converter output circuit, and a description thereof will be omitted.

First, at the point A, the voltage waveform of the input signal to the + side DC-DC converter output circuit 36 is
A voltage waveform of a switching signal output from the DC-DC converter IC 32 is given, and the voltage waveform is a square wave that rises instantly and falls instantaneously.

This square wave voltage waveform is used as the gate control voltage waveform of the FET Q1.
As the drain voltage waveform of Q1, the voltage waveform shown at point B is obtained.

The voltage waveform shown at point B falls instantaneously, but rises slightly late.

At the point C, the transistor Q
2, the voltage waveform at the base of Q3 is shown,
At point C ', a voltage waveform at the emitters of the transistors Q2 and Q3 is shown.

The voltage waveform at the emitters of the transistors Q2 and Q3 at the point C 'is the gate control voltage waveform of the FET Q4. DC-D shown
Fall time (delay time) of fall of the drain voltage waveform of FET Q4, which is an output signal in C converter
Was going to get bigger.

[0027]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the conventional DC-DC converter, and an object thereof is to provide a DC-DC converter.
By increasing the rise of the gate control voltage waveform of the final stage FET of the converter output circuit and reducing the loss of the output FET, the efficiency of the DC-DC converter is improved, and the output voltage control range is widened. DC
-To provide a DC converter.

[0028]

In order to achieve the above object, the present invention relates to a DC-DC converter output circuit of a DC-DC converter, which is located at the last stage of the DC-DC converter output circuit and is connected to the outside. This increases the speed of at least one of the rise and fall of the gate control voltage waveform supplied to the output FET that outputs the drain voltage waveform signal as the output signal, thereby reducing the loss of the output FET and thereby reducing the DC. -To improve the efficiency of the DC converter and expand the duty variable width of the gate control voltage waveform of the output FET to widen the control range of the output voltage.

That is, according to the first aspect of the present invention, a DC-DC converter control signal generation circuit for rectifying an input signal and then shifting and outputting a DC signal;
A DC-DC converter circuit that generates a switching signal based on an output signal of a DC converter control signal generation circuit, and a DC-DC converter output circuit that generates and outputs an output signal for outputting to the outside based on the switching signal Wherein the DC-DC converter output circuit includes an output FET that is located at the last stage and outputs a drain voltage waveform signal as an output signal to the outside, and an output FET that outputs the output FET according to the switching signal. A drive FET for generating a voltage waveform for generating a gate control voltage waveform; and the gate control voltage waveform speed-up circuit, wherein the gate control voltage waveform speed-up circuit generates a differential waveform of the switching signal. By combining with the drain output voltage waveform of the drive FET, At least one of the rising or falling edge of the gate control voltage waveform is obtained as to speed.

According to a second aspect of the present invention, in the first aspect of the present invention, the voltage waveform of the output signal of the DC-DC converter circuit is a square wave. is there.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a DC-DC converter according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 7 is a detailed circuit diagram of a + side DC-DC converter output circuit 36 'as an example of an embodiment of the DC-DC converter according to the present invention.

Note that the + side DC− according to the present invention shown in FIG.
The DC converter output circuit 36 'is the same as the conventional D shown in FIG.
In the C-DC converter, it is assumed to be used in place of the conventional + side DC-DC converter output circuit 36 (FIG. 5). Further, the DC-DC converter using the + side DC-DC converter output circuit 36 '(FIG. 7) according to the present invention is similar to the conventional DC-DC converter shown in FIG.
It shall be used for the amplifier circuit shown in FIG.

Further, in the + side DC-DC converter output circuit 36 'shown in FIG. 7, the conventional DC-D converter shown in FIG.
Components that are the same as or correspond to those of the C-converter output circuit 36 will be denoted by the same reference numerals as those used in FIG. 5, and detailed description thereof will be omitted.

That is, the + side DC-DC converter output circuit 36 'shown in FIG. 7 is a conventional DC-DC converter shown in FIG.
Compared with the converter output circuit 34, the gate voltage waveform rise speed-up circuit 40 having a switching signal output from the DC-DC converter IC 32 as an input signal.
In that it has

That is, the gate voltage waveform rising speed-up circuit 40 is provided with an FET Q5, and the gate of the FET Q5 is provided with a DC-DC converter I
The differential waveform of the voltage waveform of the switching signal output from C32 (the voltage waveform is a square wave that rises instantly and falls instantaneously) is input, and the drain voltage waveform of the FET Q5 and the , FET Q
Thus, the gate control voltage waveform of the final-stage FET Q4 of the + side DC-DC converter output circuit 36 'is obtained by combining the drain voltage waveform of FIG.

FIG. 8 shows that the duty is 40.
% DC-DC converter output circuit 36 '
The operation of the + side DC-DC converter output circuit 36 ′ will be described with reference to FIGS. 7 and 8.

First, at point A, the voltage waveform of the switching signal output from the DC-DC converter IC 32 is given as the voltage waveform of the input signal to the + side DC-DC converter control signal generation circuit 36 '. And the voltage waveform is a square wave that rises instantaneously and falls instantaneously.

Then, as a voltage waveform shown at the point G, a differential waveform of the voltage waveform shown at the point A is obtained by the gate voltage waveform rise speeding-up circuit 40.

In the FET Q5, the voltage waveform shown at the point G is inputted as a gate control voltage waveform, and the voltage waveform shown at the point H is outputted as a drain voltage waveform. The waveform shown at point H has a slow fall,
The rise is instantaneous.

Here, the voltage waveform shown at point A is the FET Q
1 is used as the gate control voltage waveform of the FET Q1
Outputs the voltage waveform shown at point B as the drain voltage waveform, similarly to the conventional + side DC-DC converter output circuit 36.

At the point C, the transistors Q2, Q3
The voltage waveform at the base of the transistor Q2 is shown at point C ', and the voltage waveform at the emitter of the transistors Q2 and Q3 is shown at point C'.

The voltage waveform at the emitter of the transistors Q2 and Q3 at the point C 'is the gate control voltage waveform of the FET Q4. The voltage waveform at the point C' is the drain voltage waveform of the FET Q5 shown at the point H. Of the conventional + side DC-DC converter output circuit 3
In comparison with the case of No. 4, the falling and the rising are extremely fast.

For this reason, the drain voltage waveform of the FET Q4, which is an output signal in the DC-DC converter shown at the point D, also has a very small falling delay time (delay time).

Accordingly, the + side DC-DC converter output circuit 3 having the gate voltage waveform rising speed-up circuit 40
6 ′, the output F
By reducing the loss of ET, the efficiency of the DC-DC converter can be improved, and the control range of the output voltage of the DC-DC converter can be widened.

[0046]

Since the present invention is configured as described above, the rise of the gate control voltage waveform of the FET at the last stage of the DC-DC converter output circuit can be made faster, and the DC-DC converter of the DC-DC converter can be made faster. It is possible to achieve an excellent effect that the efficiency can be improved and the control range of the output voltage of the DC-DC converter can be widened.

[Brief description of the drawings]

FIG. 1 is a block diagram of a conventional amplifier circuit.

FIG. 2 is a block diagram of a conventional DC-DC converter.

FIG. 3 is a voltage waveform diagram of each part of a conventional DC-DC converter (FIG. 2).

FIG. 4 is a voltage waveform diagram of each part of the conventional amplifier circuit (FIG. 1) when a large amplitude signal having a frequency of 1 kHz is input.

FIG. 5 is a detailed circuit diagram of a conventional + side DC-DC converter output circuit.

FIG. 6 is a voltage waveform diagram of each part of a conventional + side DC-DC converter output circuit (FIG. 5).

FIG. 7 is a detailed circuit diagram of an output circuit of a + side DC-DC converter according to the present invention.

8 is a voltage waveform diagram of each part of a + side DC-DC converter output circuit (FIG. 7) according to the present invention.

[Explanation of symbols]

Reference Signs List 10 signal source 12 power amplifier 14 voltage amplifying circuit 16, 18 power transistor 20 speaker 22 power supply (+ B) 24 + side power supply DC-DC converter 26 power supply (-B) 28-side power supply DC-DC converter 30 DC-DC Converter control signal generation circuit 32 DC-DC converter IC 34 DC-DC converter output circuit 36, 36 '+ side DC-DC converter output circuit 40 Gate voltage waveform rising speed-up circuit Q1, Q4, Q5 FET Q2, Q3 Transistor

Claims (2)

[Claims] 1. A DC-DC converter control signal generation circuit that rectifies an input signal and then shifts and outputs DC, and a DC that generates a switching signal based on an output signal of the DC-DC converter control signal generation circuit. A DC-DC converter circuit, and a DC-DC converter output circuit that generates and outputs an output signal for outputting to the outside based on the switching signal, wherein the DC-DC converter output circuit includes: An output FET that is located at the last stage and outputs a drain voltage waveform signal as an output signal to the outside, and a drive FET that generates a voltage waveform for generating a gate control voltage waveform of the output FET according to the switching signal. The gate control voltage waveform accelerating circuit, and the gate control voltage waveform accelerating circuit The path speeds up at least one of the rise and fall of the gate control voltage waveform by generating a differential waveform of the switching signal and combining the waveform with the drain output voltage waveform of the drive FET. converter. 2. The DC-DC converter according to claim 1, wherein a voltage waveform of an output signal of the DC-DC converter circuit is a square wave.