JP2000058824A - MOS transistor for low voltage operation circuit and manufacturing method thereof - Google Patents

Abstract

(57) [Problem] A conventional technology for driving a transistor with a low power supply voltage wastes current consumption by setting all the transistors in the same well region to an operation mode, and fluctuates when a source potential is changed. As a result, the transistor characteristics also fluctuated. According to the present invention, an auxiliary electrode is provided above a gate electrode of a transistor formed on a substrate, an arbitrary voltage is applied to change a threshold, a transistor characteristic is changed, and a power supply is operated at a low voltage. MO for low voltage operation circuit that operates at high speed
In the case of an N-channel transistor, the threshold is increased by setting the potential of the auxiliary electrode 5 to GND or lower when not driven, the potential of the auxiliary electrode 5 is raised to the power supply potential when driven, and the threshold is lowered. Then, the potential of the auxiliary electrode 5 is raised to the power supply potential when not driven, and the potential of the auxiliary electrode 5 is set to GND when driven.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor for a low-voltage operation circuit which is arranged on an integrated circuit formed on a semiconductor substrate and is driven at a low power supply voltage.

[0002]

2. Description of the Related Art Generally, transistors constituting an integrated circuit are driven by a power supply voltage of about 3V. However, with the realization of a reduction in wiring width and a reduction in power consumption due to high integration, further reduction in power supply voltage is being studied. In particular, there is a problem that an operation margin is reduced due to a reduction in power supply voltage.

For example, in a memory cell, a CMOS cell can operate even at a power supply voltage of about 1 V. However, in a high-resistance polysilicon load type cell or a polysilicon PMOS load type cell, the power supply is equivalent to the threshold voltage of a transistor constituting the memory cell. When the voltage is reduced, there is a problem that the device does not operate normally or the operation speed is reduced.

For this reason, various methods for operating a transistor formed on a semiconductor substrate at a low voltage have been considered. For example, (1) changing the substrate bias voltage applied to the semiconductor substrate to change the threshold voltage of the transistor; Control the voltage,
There are known a method of lowering the operating voltage, a method of (2) changing the source potential of the transistor, and lowering the source potential only when the transistor is operated.

[0005]

However, in the prior art (1) method of changing the substrate bias voltage, in order to change the potential applied to the well region, all the transistors arranged in the same well region are operated in the operation mode. I needed to.

For this reason, it is not possible to select and use only necessary transistors, resulting in unnecessary current consumption. Although it is possible to suppress this by dividing the well region into multiple parts, the area of the separation region for separating the well region is required, resulting in an increase in chip area.

In the method of (2) changing the source potential of the transistor, it is necessary to separately provide a transistor for changing the source potential. Moreover, since a high driving force is required, a transistor occupying a relatively large area has been formed. Further, there is a drawback that the source potential varies depending on the operation state of the transistor, and as a result, the transistor characteristics also vary.

Therefore, the present invention provides a MOS transistor for a low-voltage operation circuit which has a small element area on a substrate, has an auxiliary electrode for changing the threshold value of the transistor before operation, and enables high-speed operation by low-voltage driving. The purpose is to do.

[0009]

According to the present invention, there is provided a semiconductor device comprising: a plurality of transistors arranged in an integrated circuit formed on a semiconductor substrate; A low-voltage operation in which a substrate and the gate electrode are insulated from each other and an auxiliary electrode capable of applying a desired voltage is provided, and a voltage is applied to the auxiliary electrode to switch a transistor operation characteristic to a low-voltage operation or a high-voltage operation. A circuit MOS transistor is provided.

An MO for a low-voltage operation circuit having the above configuration
The S-transistor has an auxiliary electrode provided above the gate of the transistor, and before operation of the transistor, applies an arbitrary voltage to the auxiliary electrode to change the potential of the gate electrode. , The operating characteristics are changed, and high-speed operation is performed at a low voltage.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows the configuration of a MOS transistor for a low-voltage operation circuit according to a first embodiment of the present invention.

FIG. 1 (a) is a diagram showing one MOS transistor taken out of a large number of transistors formed on a semiconductor substrate, and showing the structure thereof.
FIG. 2 is a diagram showing a cross-sectional configuration thereof.

In this embodiment, a MOS transistor 2 formed on a semiconductor substrate 1 is formed, and a gate electrode 3
Is formed, and an auxiliary electrode 7 made of metal is formed with an insulating layer 6 interposed so as to cover the source 4 and the drain 5. The auxiliary electrode 7 includes an auxiliary electrode control unit 8 for selecting an auxiliary electrode 7 (transistor) for applying an auxiliary voltage.
And a power supply unit 9 for applying an arbitrary applied voltage that is variable within a range of about 0 to 3.3 V.

In accordance with an instruction from an instruction circuit 10 provided in a processing circuit (not shown) such as an MPU, the auxiliary electrode control section 8 controls selection of a transistor to which a voltage is applied, timing, and the like.

Referring to FIG. 2, M thus configured
The function of the OS transistor will be described.

FIG. 2 shows a gate voltage-drain current characteristic of the transistor 2 provided with the auxiliary electrode 7.
The characteristics when a voltage is applied are compared with the characteristics when no voltage is applied (equivalent to a transistor without an auxiliary electrode).

The auxiliary electrode 7 provided on the gate electrode 3 of the transistor to be operated is selected by the auxiliary electrode control unit 8, and an arbitrary voltage generated by the power supply unit 9 is applied. By this application, the potential of the auxiliary electrode 7 is changed,
The threshold characteristics of this transistor are changed.

When the MOS transistor 2 is an Nch MOS transistor, the threshold can be lowered by increasing the potential of the auxiliary electrode 7.

As the structure, for example, when the gate oxide film thickness is 80 Å, the gate length is 0.3 μm, and the gate width is 5 μm, the sheet resistance doped with phosphorus (P) is 100 ΩΩ and 0.1 μm. An auxiliary electrode 7 made of polysilicon having a thickness of 2 μm is formed.
Alternatively, when the distance from the drain 5 is 0.2 μm,
By applying 3 V to the auxiliary electrode, the threshold value can be reduced by 0.15 V as compared with the application of 0 V.

The MOS transistor 2 has a PchM
In the case of the OS transistor, the threshold voltage was increased by 0.1 V by applying 0 V to the auxiliary electrode 7 in the same structure in which the gate electrode 3 and the auxiliary electrode 7 were formed as compared with the case where 3 V was applied. This has the effect of improving the operating speed degradation when the power supply voltage is reduced from 3V to 2V by 20% or more.

For example, in a CMOS circuit, an NchMO
The threshold value is controlled by adding signals of opposite phases to the gate electrodes of the auxiliary electrodes provided in the S transistor and the PchMOS transistor.

FIG. 3 shows a modification of the present embodiment.

In implementing the embodiments described above, individually controlling a large number of transistors in an integrated circuit involves:
It becomes difficult in control management. It is desirable to control a plurality of transistors divided to some extent collectively in order to simplify the circuit.

Therefore, the integrated circuit is placed in the first state under the condition that the operating time periods of many transistors formed coincide with each other.
, An n-th block, and a common power supply line is connected to each of the auxiliary electrodes for each of the blocks.
The control is performed by controlling the auxiliary electrode control unit 8 according to 0.

As described above, in this embodiment, the auxiliary electrode 7 is provided above the gate electrode 3 of the transistor formed on the semiconductor substrate, and an arbitrary voltage is applied to the auxiliary electrode 7 before the operation of the transistor. Thus, the potential of the gate electrode 3 is changed before the operation to lower the threshold value of the transistor viewed from the gate electrode 3 side, thereby changing the operation characteristics and enabling high-speed operation.

In the integrated circuit, auxiliary electrodes of a plurality of transistors belonging to a specific circuit in which the driving time zones of the transistors coincide with each other can be simultaneously wired to have the same potential.

Next, a second embodiment will be described.

In the above-described first embodiment, the auxiliary electrode is provided so as to cover the entire gate electrode of the MOS transistor. However, in this embodiment, the auxiliary electrode is not provided above the gate electrode, but is provided between both side wall surfaces and the source / drain. Only the auxiliary electrode is provided,
The parasitic capacitance between the auxiliary electrode and the gate electrode is reduced as compared with the first embodiment.

FIG. 3A is a diagram showing one MOS transistor taken out from a large number of transistors formed on the semiconductor substrate 1 and showing its structure. FIG. 3B is a sectional view showing the structure. FIG.

This transistor has a configuration example in which auxiliary electrodes 12a and 12b are formed with an insulating layer 11 interposed between the source 4 and the drain 5 and both side walls of the gate electrode 3. The auxiliary electrodes 12a and 12b are not provided above the gate electrode 3, but are formed so as to be integrated at one end 3a. Further, similarly to the first embodiment, the control device includes an auxiliary electrode control unit 8, a power supply unit 9, an instruction circuit 10, and the like.

According to the configuration of the present embodiment, the parasitic capacitance between the auxiliary electrode 12 and the gate electrode 3 is reduced as compared with the configuration of the first embodiment, so that higher-speed operation can be performed.

Further, after forming a conductive film such as polysilicon which is to be an auxiliary electrode as shown in FIG. 1, the auxiliary electrode is formed as shown in FIG. Is formed so as to form an auxiliary electrode 12a and 12b, and the mask is removed after the etching process to form integrally connected auxiliary electrodes 12a and 12b.

As described above, in the present embodiment, the auxiliary electrode with reduced parasitic capacitance between the gate electrode and the gate electrode is provided between both side walls of the gate of the transistor formed on the substrate and the sort / drain. Before the operation, an arbitrary voltage is applied to the auxiliary electrode to change the potential of the gate electrode to lower the threshold value of the transistor viewed from the gate electrode side, thereby changing the operation characteristics and enabling high-speed operation.

[0035]

As described above in detail, according to the present invention, the element area occupying the substrate is small, the auxiliary electrode for changing the threshold value of the transistor before the operation is provided, and the high speed operation at a low voltage is enabled. A MOS transistor for a voltage operation circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a MOS transistor for a low-voltage operation circuit according to a first embodiment of the present invention.

FIG. 2 is a characteristic diagram of gate voltage-drain current for explaining the operation of the transistor according to the first embodiment.

FIG. 3 is a diagram showing a configuration of a MOS transistor for a low-voltage operation circuit according to a second embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor substrate 2 MOS transistor 3 gate electrode 4 source 5 drain 6 insulating layer 7 auxiliary electrode 8 auxiliary electrode control unit 9 power supply unit 10 instruction circuit

Claims (7)

[Claims] 1. A plurality of transistors arranged in an integrated circuit formed on a semiconductor substrate, wherein a region adjacent to a gate electrode of the transistor is insulated from the semiconductor substrate and the gate electrode, and a desired voltage is applied. A low-voltage operating circuit comprising a possible auxiliary electrode, a voltage applied to the auxiliary electrode, a threshold value of a transistor being changed, and a circuit for switching operation characteristics between low-voltage operation and high-voltage operation. MOS transistor. 2. The semiconductor device according to claim 1, wherein the auxiliary electrode is made of a conductor including metal and polysilicon, and is disposed on both side walls and an upper surface of the gate electrode with an insulating film interposed above the gate electrode. 2. The MOS transistor for a low-voltage operation circuit according to claim 1, wherein: 3. The method according to claim 1, wherein the auxiliary electrode is made of a conductor containing metal or polysilicon, and is disposed only on both side walls of the gate electrode with an insulating film interposed above the gate electrode. The MOS transistor for a low voltage operation circuit according to claim 1. 4. The MOS transistor for a low-voltage operation circuit, wherein a power supply for generating an arbitrary voltage to be applied to the auxiliary electrode, and the auxiliary electrode of the transistor immediately before the operation is generated by selecting a voltage generated by the power supply. 2. The MOS transistor for a low-voltage operation circuit according to claim 1, further comprising: an auxiliary electrode control unit for applying a voltage. 5. An integrated circuit formed on the semiconductor substrate is divided into groups of transistors operating simultaneously, and auxiliary electrodes formed in these transistor groups are connected by a common wiring, and 5. The MOS transistor for a low voltage operation circuit according to claim 4, wherein an arbitrary voltage is simultaneously applied from the power supply by the unit. 6. When the transistor is an Nch MOS transistor, the potential of the auxiliary electrode is set to a ground potential or lower when not driven, and the transistor threshold value is increased. When the transistor is driven, the potential of the auxiliary electrode is set to 2. The MOS for a low-voltage operation circuit according to claim 1, wherein the threshold voltage is applied to an arbitrary voltage of the power supply to lower the threshold value.
Transistor. 7. When the transistor is a Pch MOS transistor, the potential of the auxiliary electrode is applied to an arbitrary voltage of the power supply to reduce the threshold value of the transistor when not driven, and to reduce the threshold of the transistor when driven. 2. The MOS transistor for a low-voltage operation circuit according to claim 1, wherein the threshold value is made higher by setting the potential of the MOS transistor as a ground potential.