JP2000058768A - Ferroelectric memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the reliability of a ferroelectric memory device wherein ferroelectric capacitors, each made by putting a ferroelectric film between a lower electrode and an upper electrode, are disposed on memory cells. SOLUTION: In an active region, memory cell transistors using a word line WL as the gate are installed. On an element isolation region, ferroelectric capacitors, each constituted of a lower electrode, a ferroelectric film and an upper electrode TE, are installed. Storage interconnections 20 for connecting the upper electrodes TE and one of impurity diffusion layers of the memory cell transistors are formed and bit lines BL connected to the other impurity diffusion layer are formed. In a top view, a contact CE for connecting the storage interconnection and the upper electrode 18 are formed near the corner of the upper electrode TE. Due to this structure, even if foreign matters enter the ferroelectric film from the upper electrode 18 or there is damage or other trouble in formation of the contacts, the influence by those factors is reduced, thereby improving the characteristics of the ferroelectric capacitors.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a ferroelectric memory device, and more particularly to a measure for improving reliability.

[0002]

2. Description of the Related Art In recent years, portable terminal devices and IC cards have become widespread, and demands for low voltage, low power consumption, and high speed operation have increased for nonvolatile memory devices as semiconductor devices mounted on electronic devices. As a non-volatile memory device that can realize low voltage, low power consumption, and high-speed operation, a ferroelectric memory device is receiving attention. This ferroelectric memory device has a capacitor in which a ferroelectric film is sandwiched between two electrodes, and stores non-volatile data depending on whether the polarization direction of the ferroelectric film in the capacitor is positive or negative. is there. Therefore, data rewriting only requires the application of an electric field for reversing the polarization direction of the ferroelectric film, so that low voltage, low power consumption, and high speed operation can be easily achieved.

FIG. 4 is a plan view showing a state in which a memory cell array of a conventional ferroelectric memory device is viewed downward from a layer in which bit lines are formed. FIG. 5 is a vertical sectional view taken along a line VV in FIG.

As shown in FIG. 5, on a Si substrate 51,
An active region OD surrounded by the LOCOS film 52 is provided. In the active region OD, an impurity diffusion layer 53 serving as a source region and a drain region, and a gate 54 formed of a polysilicon film are formed. A first interlayer insulating film 55 is formed on the Si substrate 51, and a LOCOS film 52 is formed on the first interlayer insulating film 55.
Is formed by a lower electrode 56 made of platinum or iridium-based metal, a ferroelectric film 57 made of ferroelectric material, and an upper electrode 58 made of platinum or iridium-based metal. A cell capacitor is provided. Further, a second interlayer insulating film 59 is formed on the first interlayer insulating film 55, and a storage wiring 60 made of aluminum containing copper is formed on the second interlayer insulating film 59. ing.

In FIG. 4, the gate 54 extends in the row direction of the memory cell array as word lines WL0 to WL3, and the lower electrode 56 extends in the row direction of the memory cell array as a cell plate line. Further, bit line groups BL0, / BL0, extending in the column direction of the memory cell array.
BL1, / BL1, DBL, and / DBL are provided, and one bit line DBL is shown by a broken line in FIG. The upper electrode 58 shown in FIG.
This corresponds to a data storage node in M, and is indicated by TE in FIG. Further, the storage wiring 60 and the upper electrode 58 are connected by a contact CE. Further, the storage wiring 60 and the impurity diffusion layer 53 of the memory cell transistor are formed.
Between the bit lines BL0, BL0,
/ BL0, BL1, / BL1, DBL, / DBL and impurity diffusion layer 53 are connected by contact CW2, respectively. The storage line 60 and the bit line groups BL0, / BL0, BL1, / BL1, DBL, / D
BL forms a first wiring layer.

[0006] Such a ferroelectric memory device is manufactured by the following steps. OD on the semiconductor substrate 51
The LOCOS film 52 surrounding the active region (region for forming the impurity diffusion layer 53 such as the gate 54 and source / drain) of the transistor indicated by. Next, word lines WL0 to WL3, which are made of, for example, polysilicon and form the gate 54 of the transistor, are formed. next,
After the first interlayer insulating film 55 is formed, the cell plate lines CP0 to CP3 constituting the lower electrode 56 of the ferroelectric capacitor of the memory cell are formed of, for example, a material containing platinum or iridium. Further, a ferroelectric film is deposited on the upper surfaces of the cell plate lines CP0 to CP3, and then a material film containing platinum or an iridium-based material is deposited. These two films are sequentially patterned to form the DRA constituting the upper electrode 58 of the ferroelectric capacitor of the memory cell.
A data storage node TE and a ferroelectric film 57 referred to as M are formed. Next, after the second interlayer insulating film 59 is formed, the contact CE between the upper electrode 58 and the storage wiring 20 and the contact CW between the storage wiring 20 and the impurity diffusion layer 53 of the memory cell transistor are formed.
1 is formed. Next, the bit line groups BL0, / BL0,
BL1, / BL1, DBL, / DBL and upper electrode TE
And impurity diffusion layer (drain) of memory cell transistor
A first wiring layer is formed of a metal film containing, for example, aluminum or copper as a connection line with the wiring 53. Thus, a memory cell array as shown in FIG. 1 is configured.

As described above, the polarity of the polarization state in the two ferroelectric films 57 is changed according to the difference in the level relationship between the bit line voltage supplied through the impurity diffusion layer 53 and the cell plate line voltage. By alternately changing and holding,
In this conventional example, the contact CE between the upper electrode 58 and the storage wiring 60 is connected to the upper electrode 58 (T
E) is arranged at the center.

[0008]

Incidentally, in the above-mentioned conventional ferroelectric memory device, characteristics such as retention (data retention) characteristics of the ferroelectric capacitor may be degraded. It is considered that one of the causes is, for example, intrusion of foreign matter from the upper electrode 58 into the ferroelectric film 57 and damage during the formation of the contact CE. That is, in the structure of the conventional ferroelectric memory device shown in FIGS. 4 and 5, the contact CE between the upper electrode 58 and the storage wiring 60 is connected to the upper electrode 58 (TE).
As a result, if a foreign substance enters the upper electrode from the contact CE or is damaged during the formation of the contact CE, the region of the ferroelectric film 57 immediately below the contact CE is likely to be deteriorated. It was guessed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to adjust a position of a contact between an upper electrode and a storage wiring in an upper layer when viewed in a plan view, thereby providing a ferroelectric capacitor. It is an object of the present invention to provide a highly reliable ferroelectric memory device without deterioration of the characteristics.

[0010]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention takes measures to provide a position of a contact in a plan view at a peripheral portion of an upper electrode of a memory cell.

A ferroelectric memory device according to the present invention comprises a ferroelectric capacitor including an upper electrode, a lower electrode, and a ferroelectric film interposed between the upper electrode and the lower electrode; a first impurity diffusion layer; A memory cell transistor having a second impurity diffusion layer and a gate for controlling supply of a voltage to the upper electrode of the ferroelectric capacitor; and a memory cell transistor formed above the memory cell transistor and the ferroelectric capacitor. An interlayer insulating film, a first wiring layer formed on the interlayer insulating film, and a contact connecting the first wiring layer and an upper electrode of the ferroelectric capacitor. When viewed two-dimensionally, it is formed at a position offset from a position near the center of the upper electrode so as not to interfere with one line passing through the center position of the upper electrode.

Thus, even if foreign matter enters the upper electrode from above via the contact or the upper electrode is damaged during the formation of the contact, the position of the contact is shifted from the center of the upper electrode. The central part, which has a significant effect on the properties of the bodily membrane, is not so affected. Therefore, deterioration of the characteristics of the ferroelectric capacitor can be suppressed.

In the case where the upper electrode has a rectangular planar shape, the contact passes through a center position of the upper electrode and a line parallel to one side of the upper electrode in a plan view. It may be formed at a position offset to one of the sides from a position near the center of the upper electrode so as not to interfere with the upper electrode.

When the upper electrode has a rectangular planar shape, the contacts pass through a center position of the upper electrode and are parallel to two sides of the upper electrode in plan view. It is more preferable that the upper electrode is formed at a position offset to one of the corners from a position near the center of the upper electrode so as not to interfere with the two orthogonal lines.

The ferroelectric memory device may further include a bit line connected to the impurity diffusion layer of the memory cell transistor, and a cell plate line forming the lower electrode. When the bit line and the cell plate line are connected between the impurity diffusion layer of the cell transistor and the cell plate line, and the bit line and the cell plate line are orthogonal to each other, the contact is made to the upper electrode. It can be formed at a position offset to the side of the impurity diffusion layer.

The ferroelectric memory device may further include a bit line connected to the impurity diffusion layer of the memory cell transistor, and a cell plate line forming the lower electrode. The bit line and the cell plate line are connected between the impurity diffusion layer of the cell transistor and the cell plate line, and the bit line and the cell plate line are arranged orthogonal to each other. Is formed to a position protruding from the longitudinal side of the bit line,
The contact can be formed at a position offset with respect to the upper electrode on a side facing the bit line.

In the above ferroelectric memory device,
By giving the lower electrode and the ferroelectric capacitor substantially the same shape, and giving the upper electrode a narrower shape than the ferroelectric capacitor, the vicinity of the end of the ferroelectric capacitor with large processing damage can be reduced. Without using
The characteristics can be improved.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 shows a memory cell array of a ferroelectric memory device according to a first embodiment of the present invention in a downward direction from a layer in which bit lines are formed. It is a top view showing the state where it was seen. FIG.
FIG. 2 is a vertical sectional view taken along a line II.

As shown in FIG. 2, on a Si substrate 11,
An active region OD surrounded by the LOCOS film 12 is provided. In the active region OD, an impurity diffusion layer 13 serving as a source region and a drain region, and a gate 14 formed of a polysilicon film are formed. Further, a first interlayer insulating film 15 is formed on the Si substrate 11, and the LOCOS film 12 is formed on the first interlayer insulating film 15.
Is formed by a lower electrode 16 made of platinum or an iridium-based metal, a ferroelectric film 17 made of a ferroelectric material described later, and an upper electrode 18 made of a platinum or iridium-based metal. A configured memory cell capacitor is provided. A second interlayer insulating film 19 is formed on the first interlayer insulating film 15, and a storage wiring 20 made of aluminum containing copper is formed on the second interlayer insulating film 19. ing.

In FIG. 1, the gate 14 extends in the row direction of the memory cell array as word lines WL0 to WL3, and the lower electrode 16 extends in the row direction of the memory cell array as a cell plate line. Further, bit line groups BL0, / BL0, extending in the column direction of the memory cell array.
BL1, / BL1, DBL, and / DBL are provided, and one bit line DBL is shown by a broken line in FIG. The upper electrode 18 shown in FIG.
This corresponds to a data storage node referred to as M, and is indicated by a letter TE in FIG. Further, the storage wiring 20 and the upper electrode 18 are connected by a contact CE. Further, the storage wiring 20 and the impurity diffusion layer 1 of the memory cell transistor are formed.
3 between the bit line group BL and the contact CW1.
0, / BL0, BL1, / BL1, DBL, / DBL and impurity diffusion layer 13 are connected by contact CW2, respectively. The storage line 20 and the bit line groups BL0, / BL0, BL1, / BL1, DBL,
/ DBL constitutes a first wiring layer.

As described above, the polarity of the two ferroelectric films 17 is switched between positive and negative depending on the difference in the level relationship between the voltage of the bit line supplied through the impurity diffusion layer 13 and the voltage of the cell plate line. By changing and maintaining it,
The configuration is such that data of 1 "and" 0 "can be held.

The method of manufacturing the ferroelectric memory device according to this embodiment is the same as the conventional method. Semiconductor substrate 11
A LOCOS film 12 surrounding the active region of the transistor (the region where the impurity diffusion layer 13 such as the gate 14 and the source / drain is to be formed) indicated by OD is formed on the substrate.
Next, word lines WL0 to WL3, which are made of, for example, polysilicon and form the gate 14 of the transistor, are formed. Next, after the first interlayer insulating film 15 is formed, the cell plate lines CP0 to CP3 constituting the lower electrode 16 of the ferroelectric capacitor of the memory cell are formed using a material containing, for example, platinum or iridium. . Further, a ferroelectric film is deposited on the upper surfaces of the cell plate lines CP0 to CP3, and then a material film containing platinum or an iridium-based material is deposited. These two films are sequentially patterned,
A data storage node T in a DRAM constituting the upper electrode 18 of a ferroelectric capacitor of a memory cell
E and a ferroelectric film 17 are formed. Next, after the second interlayer insulating film 19 is formed, the contact CE between the upper electrode 18 and the storage wiring 20 or the storage wiring 20
A contact CW1 between the gate electrode and impurity diffusion layer 13 of the memory cell transistor is formed. Next, the bit line groups BL0, BL0,
As a connection line between / BL0, BL1, / BL1, DBL, / DBL and the upper electrode TE and the impurity diffusion layer (drain) 13 of the memory cell transistor, the first wiring layer is made of a metal film containing aluminum or copper, for example. It is formed. Thus, a memory cell array as shown in FIG. 1 is configured.

The feature of this embodiment is that the upper electrode 1
8 is different from the conventional structure in the position of the contact CE connecting the 8 (TE) and the storage wiring 20. That is, in the structure of the conventional ferroelectric memory device, the contact CE is formed substantially at the center of the upper electrode 58 in plan view, as shown in FIG. On the other hand, in the ferroelectric memory device according to the present embodiment, as shown in FIGS. 1 and 2, the contact CE is moved from the position near the center of the upper electrode 18 (TE) in the conventional ferroelectric memory device. It is formed shifted to the impurity diffusion layer 13 side of the memory cell transistor.

The position of the upper electrode 18 in the direction along the cell plate line CP is offset from the position in the conventional ferroelectric memory device toward the bit line BL. That is, at the position where the upper electrode 18 and the bit line BP intersect, the upper electrode 18 is offset so that one of the four sides of the upper electrode 18 orthogonal to the cell plate line CP protrudes from the bit line. I have. As a result, the contact CE is formed near the corner of the upper electrode 18. However, in the structure of the present embodiment, the upper electrode 18 and the ferroelectric film 17 are patterned into the same shape.
8 and the ferroelectric film 17 have the same shape and position. The same applies to the following.

With this configuration, even if foreign matter enters the ferroelectric film 17 from the upper electrode 18 or damage occurs during the formation of the contact, the influence is not affected by the influence of the upper electrode 18 on which the ferroelectric capacitor is formed. , And deterioration of the characteristics of the ferroelectric capacitor as a whole is suppressed.

Further, bit line groups BL0, / BL0, B
There is also an effect that the number of disconnections and short-circuits with adjacent wirings during the processing of L1, / BL1, DBL, and / DBL are reduced, and the yield is improved.

That is, according to the configuration of the present embodiment, the retention (data retention) characteristic is greatly improved by improving the polarization value in the characteristics of the ferroelectric capacitor. And the use of the device using this ferroelectric memory device will be greatly expanded.

Further, although not shown in the drawings, the ferroelectricity is formed by using a manufacturing process in which a second wiring layer is formed above a first wiring layer such as the storage wiring 20 via an interlayer insulating film. In the case of manufacturing a ferroelectric memory device, the upper electrode 1 of the ferroelectric capacitor is
8 (or the lower electrode 16). This has the effect of preventing the deterioration of the characteristics of the ferroelectric capacitor due to the annealing step or the like which is performed before the manufacturing process of the second wiring layer, and the effect of reducing the stress on the ferroelectric capacitor due to the second wiring step. There is.

In particular, when the second wiring layer is made of a wiring material containing aluminum or copper, the following effects can be obtained. The second wiring layer is used as a backing wiring for reducing the resistance value of a word line (for example, WL0, WL1) formed of, for example, polysilicon on the circuit, and is also a lower electrode 16 of a ferroelectric capacitor. It can also be used as a backing wiring for reducing the resistance value of the cell plate line (for example, CP0, CP1). Therefore, a high-speed operation can be performed by reducing the resistance value, and even when the word line is disconnected due to the manufacturing process, many connection points between the word line and the second wiring layer as the backing wiring are obtained. Therefore, there is also an effect that an electrical failure hardly occurs.

The upper electrode 18 and the storage wiring 20
In the contact portion CE, an overlap margin in consideration of a mask shift between the contact portion CE and the storage wiring 20 and the like is set as a minimum size of a process design rule.

Dummy bit lines DBL and / DBL are arranged at the ends of the memory cell array so that the ferroelectric capacitors at the ends of the memory cell array are not used for the operation of the circuit. This is because the memory cell at the end of the memory cell array and the other memory cells have the same structure, but since the memory cell at the end of the memory cell array is adjacent to a region where no memory cell exists, This is because the memory cell exhibits characteristics different from those of the other memory cells, and the characteristics of the present embodiment may not be improved.

In the present embodiment, the upper electrode 18 is provided so as to extend between the bit line BL and the storage wiring 20, but the present invention is not limited to such an embodiment. One side (end) of the upper electrode exists below the bit line, for example, as in the conventional ferroelectric memory device shown in FIG.
In the direction where the contact is along the cell plate line,
Even when the contact is located almost at the center of the upper electrode, foreign matter can enter by setting the position of the contact in the direction orthogonal to the cell plate line to the impurity diffusion layer side or the opposite direction. And the effect of minimizing the deterioration of the characteristics of the ferroelectric capacitor due to the formation of damage or damage.

(Second Embodiment) FIG. 3 is a plan view showing a state in which a memory cell array according to a second embodiment is viewed downward from a layer on which bit lines are formed.

The feature of this embodiment is that the upper electrode 1
This is the point that the position of the contact CE connecting the 8 (TE) and the storage wiring 20 is changed from the conventional structure. That is, in the structure of the conventional ferroelectric memory device, the upper electrode 18 is formed so as to be shifted toward the bit line BL in the direction along the cell plate line CP from the position in the conventional ferroelectric memory device. I have. However, as in the first embodiment, the contact CE is not shifted from the position near the center of the upper electrode 18 (TE) in the direction of the impurity diffusion layer 13 in the conventional ferroelectric memory device. As a result, the contact CE is formed near one side of the upper electrode 18. Even with this configuration, the upper electrode 1
Even if foreign matter enters the ferroelectric film 17 from the substrate 8 or damages at the time of contact formation, the influence is exerted only on the end portion of the upper electrode 18 where the ferroelectric capacitor is formed. Deterioration of characteristics of the entire body capacitor is suppressed.

Further, bit line groups BL0, / BL0, B
There is also an effect that the number of disconnections and short-circuits with adjacent wirings during the processing of L1, / BL1, DBL, and / DBL are reduced, and the yield is improved.

That is, according to the configuration of this embodiment,
With respect to the characteristics of the ferroelectric capacitor, the retention (data retention) characteristics are improved by improving the polarization value and the like, and the use of the device using the ferroelectric memory device is greatly expanded.

In the present embodiment, the process of forming the second wiring layer above the storage wiring 20 via the third interlayer insulating film is performed in the same manner as described in the first embodiment. It can be used.

In each of the above embodiments, the ferroelectric material constituting the ferroelectric film is KNO ₃ , PbLa.
₂ O ₃ —ZrO ₂ —TiO ₂ , PbTiO ₃ —PbZr
O _{3 and the} like, and any of them may be used.

Further, the position of the contact of the present invention is not limited to the position in each of the above embodiments, but may be near any one of the four sides of the upper electrode or any of the four corners. If formed at one corner of the ferroelectric capacitor, the effect of suppressing deterioration of the characteristics of the ferroelectric capacitor due to intrusion of foreign matter and damage at the time of forming a contact can be exhibited.

(Other Embodiments) In each of the above embodiments, the upper electrode 18 and the ferroelectric film 17 are patterned into the same shape, and the lower electrode 16 has a structure wider than the ferroelectric film 17. However, as another embodiment, as shown in FIG. 6, the ferroelectric film 17 and the lower electrode 16 are patterned into the same shape, and the upper electrode 18 has a narrower shape than the ferroelectric film 17. It may be.

The structure of the memory cell portion shown in FIG. 6 is formed by the following procedure. First, after a first interlayer insulating film 15 is formed, a lower electrode layer made of a platinum or iridium-based material for forming a lower electrode 16 (cell plate lines CPO to CP3) of a ferroelectric capacitor of a memory cell is formed. A ferroelectric film layer for forming a ferroelectric film 17;
An upper electrode layer made of a platinum or iridium-based material for forming the upper electrode 18 is sequentially deposited. Next, the upper electrode layer is patterned into a predetermined shape,
8 is formed. Thereafter, the ferroelectric film layer and the lower electrode layer are patterned so as to have the same shape as each other and to have a shape wider than the upper electrode 18.
7 and the lower electrode 16 are formed.

Alternatively, after sequentially depositing a lower electrode layer, a ferroelectric film layer, and an upper electrode layer, the three laminated films are first patterned into the shapes of the ferroelectric film 17 and the lower electrode 16, and then the upper electrode layer is formed. By patterning only the electrode layer into a narrower shape, the lower electrode 16 and the ferroelectric film 1 are patterned.
7 and the upper electrode 18 may be formed.

According to the above-described method, a structure of a ferroelectric capacitor in which the ferroelectric film 17 and the lower electrode 16 have the same shape and the upper electrode 18 has a narrower shape than the ferroelectric film 17 is realized. be able to.

According to the ferroelectric memory device shown in FIG.
Since the pattern width of the upper electrode 18 is smaller than that of the ferroelectric film 17, even if damage during processing remains in a region near the side surface of the ferroelectric film 17, it is not affected. Deterioration of characteristics due to damage remaining in the region near the side surface can be improved. Therefore, a remarkable effect can be exerted in a configuration in which the formation position of the contact to the upper electrode 18 is offset from the center position as in the present invention.

[0045]

According to the ferroelectric memory device of the present invention,
A contact connecting the first wiring layer and the upper electrode of the ferroelectric capacitor is provided at a position offset from a position near the center of the upper electrode so as not to interfere with one line passing through the center position of the upper electrode. Therefore, it is possible to suppress the deterioration of the ferroelectric film due to the invasion of foreign substances and the damage to the upper electrode during the formation of the contact, and to improve the characteristics such as the retention of the ferroelectric capacitor.

[Brief description of the drawings]

FIG. 1 is a plan view of a ferroelectric memory device according to a first embodiment of the present invention as viewed downward from a first wiring layer.

FIG. 2 is a sectional view taken along line II-II in FIG.

FIG. 3 is a plan view of a ferroelectric memory device according to a second embodiment of the present invention as viewed downward from a first wiring layer.

FIG. 4 is a plan view of a conventional ferroelectric memory device viewed downward from a first wiring layer.

FIG. 5 is a sectional view taken along line VV in FIG. 4;

FIG. 6 is a cross-sectional view illustrating a structure of a memory cell unit of a ferroelectric memory device according to another embodiment.

[Explanation of symbols]

 Reference Signs List 11 Si substrate 12 LOCOS film 13 Impurity diffusion layer 14 Gate 15 First interlayer insulating film 16 Lower electrode 17 Ferroelectric film 18 Upper electrode 19 Second interlayer insulating film 20 Storage wiring OD Active region WL Word line CP Cell plate line TE upper electrode CE contact CW contact BL bit line DBL dummy bit line

Claims (6)

[Claims] An upper electrode, a lower electrode, and the upper electrode;
A ferroelectric capacitor composed of a ferroelectric film interposed between the lower electrodes, a first impurity diffusion layer, a second impurity diffusion layer, and a gate, the ferroelectric capacitor being connected to the upper electrode of the ferroelectric capacitor; A memory cell transistor for controlling the supply of voltage, an interlayer insulating film formed above the memory cell transistor and the ferroelectric capacitor, a first wiring layer formed on the interlayer insulating film, A contact for connecting the first wiring layer and an upper electrode of the ferroelectric capacitor, wherein the contact does not interfere with one line passing through a center position of the upper electrode when viewed in a plan view. A ferroelectric memory device formed at a position offset from a position near the center of the upper electrode. 2. The ferroelectric memory device according to claim 1, wherein the upper electrode has a rectangular planar shape, and the contact passes through a center position of the upper electrode when viewed in plan. A ferroelectric memory device which is formed at a position offset from one of the centers of the upper electrode to any one side so as not to interfere with a line parallel to one side of the upper electrode. . 3. The ferroelectric memory device according to claim 1, wherein the upper electrode has a rectangular planar shape, and the contact passes through a center position of the upper electrode as viewed in plan. The upper electrode is formed at a position offset to one of the corners from a position near the center of the upper electrode so as not to interfere with two lines orthogonal to each other and parallel to the two sides of the upper electrode. Ferroelectric memory device. 4. The ferroelectric memory device according to claim 1, wherein a bit line connected to an impurity diffusion layer of said memory cell transistor, and a cell plate forming said lower electrode The ferroelectric capacitor is connected between an impurity diffusion layer of the memory cell transistor and a cell plate line, and the bit line and the cell plate line are arranged so as to be orthogonal to each other. The ferroelectric memory device, wherein the contact is formed at a position offset from the upper electrode toward the impurity diffusion layer. 5. The ferroelectric memory device according to claim 1, wherein a bit line connected to an impurity diffusion layer of said memory cell transistor, and a cell plate forming said lower electrode The ferroelectric capacitor is connected between an impurity diffusion layer of the memory cell transistor and a cell plate line, and the bit line and the cell plate line are arranged so as to be orthogonal to each other. The upper electrode is formed at a position crossing the bit line up to a position protruding from a side in the longitudinal direction of the bit line. The contact is located on a side of the upper electrode facing the bit line. A ferroelectric memory device formed at a position offset from the ferroelectric memory. 6. The ferroelectric memory device according to claim 1, wherein said lower electrode and said ferroelectric capacitor have substantially the same shape, and said upper electrode is A ferroelectric memory device having a shape narrower than a dielectric capacitor.