JP2000058638A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Problem] To prevent disconnection or increase in resistance due to insufficient embedding in a groove, and to prevent increase in wiring resistance due to dishing in CMP processing. SOLUTION: In a semiconductor device in which a wiring layer laminated via an interlayer insulating film is connected by a plug penetrating the interlayer insulating film, after forming a plug reaching the upper surface of the interlayer insulating film, the wiring layer is formed on the interlayer insulating film. By forming a groove in which a wiring layer is formed, and forming a wiring layer in the groove,
The plug connected to the upper surface of the wiring layer reaches, and the side surface of the plug is connected to the wiring layer. [Effect] In a part having a small wiring width, instead of the wiring layer,
The wiring layer is formed by partially extending the plug to prevent disconnection or increase in resistance due to insufficient embedding, and the plug reaching the upper surface of the wiring layer is excessively polished by the copper film during the CMP process. And dishing can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a technique effective when applied to a semiconductor device having a plug for connecting stacked wiring layers.

[0002]

2. Description of the Related Art In a semiconductor device, various elements formed on a main surface of a semiconductor substrate such as single crystal silicon are connected to each other by a wiring layer formed in an upper layer via an interlayer insulating film to form a predetermined circuit. The number of the elements formed in the semiconductor device has increased due to the development of microfabrication technology, and by configuring a more complicated circuit, the number of wirings necessary for connecting the elements and forming a circuit has also increased. As the wiring layer, a multilayer wiring in which a plurality of wiring layers are formed with an interlayer insulating film interposed therebetween is used.

FIG. 1 shows an example of a method for manufacturing such a multilayer wiring.
This will be described with reference to FIGS.

First, a main surface of a semiconductor substrate 1 is separated into element forming regions by a field insulating film 2, and a diffusion layer such as a source region and a drain region 3 is formed in each element forming region. A gate electrode 5 made of polycrystalline silicon is formed on the main surface of the semiconductor substrate 1 with a gate insulating film 4 interposed therebetween, and a wiring layer 6 is formed on the field insulating film 2 in the same layer as the gate electrode 5. ing.

The side surfaces of the gate electrode 5 and the wiring layer 6 are covered with sidewalls 7, and the upper surfaces of the source region, the drain region 3, the gate electrode 5 and the wiring layer 6 react with a refractory metal such as titanium to form silicide. Salicide treatment has been performed.

[0006] The semiconductor substrate 1 and each formed element are covered with an interlayer insulating film 8.
-TEOS (plasma CVD using TEOS) silicon oxide film (200 nm), SOG silicon oxide film (200 nm), P-TEOS silicon oxide film (80
0 nm) is sequentially deposited, and then 50 nm is
Polishing is performed to about 0 nm (amount of polishing on the large-area wiring layer) to flatten the device steps caused by the gate electrode 5 and the like.
-A silicon oxide film (200 nm) is deposited by TEOS. An opening for exposing the source region, the drain region 3 and the connection region of the wiring layer 6 is formed in the interlayer insulating film 8 by photolithography and dry etching. This state is shown in FIG.

Next, after purifying the connection region by removing the natural oxide film or the like with argon plasma, a barrier film 9a on which titanium (10 nm) or titanium nitride (50 nm) is deposited by sputtering, a tungsten film by CVD. 9
b (300 nm) is sequentially deposited and a plug 9 processed by CMP is formed in the opening of the interlayer insulating film 8, and then a barrier film 10 a made of titanium nitride (30 nm) by sputtering and containing 0.5% of copper by sputtering. Aluminum alloy film 10b, titanium (10
nm) and an anti-reflection film 10c on which titanium nitride (75 nm) is deposited, and patterning is performed by dry etching using a photolithographic mask to form a first metal wiring layer 10. This state is shown in FIG.
Shown in

Next, the metal wiring layer 10 is covered with an interlayer insulating film 11, and the interlayer insulating film 11 is made of a silicon oxide film (200 nm) of P-TEOS and a silicon oxide film (3
00 nm), silicon oxide film by P-TEOS (1500
nm) are sequentially deposited, and then 120
Polishing by about 0 nm (amount of polishing on the large-area wiring layer) to flatten the element steps caused by the wiring layer 10,
An interlayer insulating film 11 on which a silicon oxide film (200 nm) is deposited by EOS is formed, and an opening for exposing the connection region of the wiring layer 10 is formed in the interlayer insulating film 11 by photolithography and dry etching. 9
The second-layer plug 12 and the metal wiring layer 13 are formed by the same process as that of the wiring layer 10. This state is shown in FIG.
Shown in

By repeating such a process, a multilayer wiring structure having a desired number of layers can be obtained.
However, with the progress of miniaturization, this conventional wiring layer structure makes it difficult to pattern the wiring layer. In addition, with respect to the formation of an insulating film after the processing of the wiring layer, insulation is required when filling in a fine gap is prioritized. Because problems such as deterioration of the film quality or complicating the planarization of the insulating film occur,
Attention has been paid to a multilayer wiring layer structure by a buried damascene method in which a groove for a wiring layer is provided in an insulating film and the groove is filled with metal.

An example of a method of manufacturing a multilayer wiring layer by such a damascene method will be described with reference to FIGS.

First, the main surface of the semiconductor substrate 1 is separated into each element formation region by a field insulating film 2, and a diffusion layer such as a source region and a drain region 3 is formed in each element formation region. A gate electrode 5 made of polycrystalline silicon is formed on the main surface of the semiconductor substrate 1 with a gate insulating film 4 interposed therebetween, and a wiring layer 6 is formed on the field insulating film 2 in the same layer as the gate electrode 5. ing.

The side surfaces of the gate electrode 5 and the wiring layer 6 are covered with sidewalls 7, and the upper surfaces of the source region, the drain region 3, the gate electrode 5 and the wiring layer 6 react with a refractory metal such as titanium to be silicided. Salicide treatment has been performed.

The semiconductor substrate 1 and each element formed on the main surface of the semiconductor substrate 1 are covered with an interlayer insulating film 8.
The interlayer insulating film 8 is formed of a silicon oxide film (20
0 nm), silicon oxide film by SOG (200 nm), P
After a silicon oxide film (800 nm) is sequentially deposited by -TEOS, it is polished by a CMP technique to a thickness of about 500 nm (amount of polishing on a large-area wiring layer) to flatten an element step caused by the gate electrode 5 and the like. -A silicon oxide film (200 nm) is deposited by TEOS. An opening for exposing the source region, the drain region 3 and the connection region of the wiring layer 6 is formed in the interlayer insulating film 8 by photolithography and dry etching.

Subsequently, after purifying such as removal of the natural oxide film in the connection region by argon plasma, a barrier film 9a on which titanium (10 nm) and titanium nitride (50 nm) are deposited by sputtering, a tungsten film by CVD 9b (300 nm) is sequentially deposited, and a plug 9 processed by CMP is formed in the opening of the interlayer insulating film 8.
This state is shown in FIG.

Next, a silicon oxide film (2
00 nm), silicon oxide film by SOG (200 nm),
A trench is formed by photolithography and dry etching from which a wiring layer forming region of the interlayer insulating film 11 in which a silicon oxide film (200 nm) is sequentially deposited by P-TEOS is removed. This state is shown in FIG.

Then, after purifying the surface of the plug 9 exposed by the groove by removing the natural oxide film or the like with argon plasma, a barrier film 14a on which titanium nitride (50 nm) is deposited and a copper film 14b (800 nm) are deposited. Are sequentially deposited by sputtering, and 45 are deposited in a hydrogen atmosphere in the same vacuum system.
A heat treatment is performed at 0 ° C. for 30 minutes to reflow the copper film 14b. This state is shown in FIG.

Next, the metal outside the groove is removed by polishing by the CMP technique, and the damascene wiring layer 14 is formed. This state is shown in FIG.

Next, a silicon oxide film (3
00 nm), silicon oxide film by SOG (300 nm),
An opening for exposing the connection region of the wiring layer 14 is formed by photolithography and dry etching in the interlayer insulating film 15 on which a silicon oxide film (300 nm) of P-TEOS is sequentially deposited. The plug 16 and the damascene wiring layer 17 of the second layer are formed by the same process. This state is shown in FIG.

By repeating such a process, a multilayer wiring structure having a desired number of layers can be obtained. Such damascene wiring layers are described in, for example, pages 248 to 251 of “ULSI Process Technology” published by Baifukan,
Alternatively, it is described in “Nikkei Micro Device”, December 1997, pp. 212-217.

[0020]

The inventor of the present invention has proposed that the minimum dimension of the wiring layer is 0.4 μm in the damascene wiring layer technology.
As a result of studying the structure of m × 0.4 μm and the plug having a diameter of 0.4 μm, it was confirmed that the following problems occurred.

That is, in the portion having the minimum wiring width, the step coverage of the groove having a high aspect ratio is not sufficient by the sputtering of copper, and the reflow embedding technique of the copper film becomes insufficient. There is a problem in that the filling is not performed sufficiently and a disconnection occurs to cause a conduction failure, or a void 14c occurs as shown in FIG. 9 to increase the resistance of this portion. When the resistance is partially increased as described above, there is a possibility that the wire may be disconnected with time due to heat generation when current flows.

As a method for solving such a problem, a method of forming a copper film by CVD with good step coverage is conceivable, but it has not yet reached a practical stage. In addition, as shown in FIG. 10, it is possible to cope with the problem by increasing the minimum wiring layer width to about 0.8 μm. However, since the minimum circuit unit area increases, the chip area increases, and the yield decreases and the cost increases. Will be a factor.

Further, in order to form an interlayer insulating film before forming a wiring layer, when a plug is connected to a plug of an adjacent layer, a stacked via (syacked vi) is directly connected.
a) cannot be performed, and is performed via a wiring layer of the same size. For this reason, the chip area increases due to the mask alignment error.

In addition, since the CMP rate of the copper film is high,
In a wiring layer in which a copper film extends continuously and has a large wiring width, polishing proceeds at a central portion of the copper film, and dishing in which a hollow is formed in the central portion of the copper film occurs as shown in FIG. Due to this dishing, there is a problem that the thickness of the copper film is partially reduced, and the actual wiring resistance becomes higher than a designed value. For example, in a wiring layer having a wiring width of 5 μm or more, this recess extends to a depth of 0.2 μm.

If the design wiring thickness is increased in anticipation of a decrease in order to eliminate the increase in the wiring resistance due to the decrease in the film thickness, the aspect ratio of the wiring layer becomes high. As a result, the problem of poor embedding becomes more serious.

An object of the present invention is to provide a technique capable of preventing disconnection or high resistance due to insufficient embedding in a groove.

Another object of the present invention is to provide a technique capable of preventing an increase in wiring resistance due to dishing caused by CMP processing.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0029]

Means for Solving the Problems Among the inventions disclosed in the present application, the outline of typical inventions will be briefly described.
It is as follows.

In a semiconductor device in which wiring layers stacked via an interlayer insulating film are connected by plugs penetrating the interlayer insulating film, the connected plugs reach the upper surface of the wiring layer, and the side surfaces of the plugs Are connected to the wiring layer.

In a method of manufacturing a semiconductor device in which wiring layers stacked via an interlayer insulating film are connected by plugs penetrating the interlayer insulating film, a step of forming the interlayer insulating film; Providing an opening in which a plug is formed in the film; forming a plug in the opening up to the upper surface of the wiring; forming a groove in which a wiring layer is formed in the interlayer insulating film; Forming a wiring layer and connecting the wiring layer on the side surface of the plug.

According to the above-described means, in a portion where the wiring width of the wiring layer is small, the wiring layer can be formed by a configuration in which the plug is partially extended instead of the wiring layer. With this configuration, it is possible to prevent disconnection or increase in resistance due to insufficient embedding in a groove having a high aspect ratio.

Further, since the plug and the plug in the adjacent layer can be directly connected, the margin for mask alignment can be reduced, and the chip area can be prevented from increasing.

Furthermore, since the plug reaches the upper surface of the wiring layer, it is possible to prevent the copper film from being excessively polished at the time of the CMP process by this plug, and to prevent the occurrence of dishing.

Hereinafter, embodiments of the present invention will be described.

In all the drawings for describing the embodiments, those having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

[0037]

(Embodiment 1) FIG. 12 is a perspective view showing a main part of a semiconductor device according to an embodiment of the present invention.

The main surface of the semiconductor substrate 1 is separated into each element formation region by a field insulating film 2, and a diffusion layer such as a source region and a drain region 3 is formed in each element formation region. A gate electrode 5 made of polycrystalline silicon is formed on the main surface of the semiconductor substrate 1 with a gate insulating film 4 interposed therebetween, and a wiring layer 6 is formed in the same layer as the gate electrode 5.
Are formed on the field insulating film 2.

The side surfaces of the gate electrode 5 and the wiring layer 6 are covered with the sidewalls 7, and the upper surfaces of the source region, the drain region 3, the gate electrode 5 and the wiring layer 6 are reacted with a refractory metal such as titanium to be silicided. Salicide treatment has been performed.

The source region, the drain region 3 or the wiring layer 6 of each element formed on the main surface of the semiconductor substrate 1 is connected to one end of a plug 21 penetrating through the interlayer insulating film 20, and the other end of the plug 21 is connected to the interlayer insulating film. It is connected to the laminated damascene wiring layer 22 via the film 20. The interlayer insulating film 20 is made of P
After sequentially depositing a silicon oxide film (200 nm) by -TEOS, a silicon oxide film (200 nm) by SOG, and a silicon oxide film (800 nm) by P-TEOS,
About 500nm (polishing amount on large area wiring layer) by technology
Polishing is performed to flatten an element step caused by the gate electrode 5 and the like, and furthermore, a silicon oxide film (800 n
m) has been deposited.

The plug 21 is made of titanium (1) formed by sputtering.
0 nm), a barrier film 21a on which titanium nitride (50 nm) is deposited, and a tungsten film 21b (300
nm) are sequentially deposited and processed by CMP.

The damascene wiring layer 22 is made of titanium nitride (50
nm) and a copper film 22b (80
0 nm) is sequentially deposited by sputtering, heat-treated at 450 ° C. for 30 minutes in a hydrogen atmosphere in the same vacuum system, and the copper film 22 b is reflowed and polished by CMP to form a plug up to the upper surface of the wiring layer 22. In the present embodiment where the other end of the wiring 21 reaches the other end and the side surface of the other end of the plug 21 is connected to the damascene wiring layer 22, the plug 21 is replaced by the plug 21 instead of the damascene wiring layer 22 in the narrow wiring width of the wiring layer.
The wiring layer can be formed by a configuration in which is partially extended. With this configuration, it is possible to prevent disconnection or increase in resistance due to insufficient embedding in a groove having a high aspect ratio.

Further, in the experiment of the present inventor, dishing is more conspicuous when the continuous portion of the wiring is longer, specifically when the wiring width exceeds 5 μm. This is presumably because in a portion where the wiring layer and another material such as an interlayer insulating film are adjacent to each other, excessive polishing of the copper film is suppressed due to wear resistance of the other material.

In the present embodiment, the plug 21 made of tungsten, which is a more wear-resistant material than copper, reaches the upper surface of the wiring layer 22, and the plug 21 divides a continuous portion of the wiring. It will be. Therefore, the excessive polishing of the copper film 22b during the CMP processing can be suppressed by the plug 21, and the occurrence of dishing can be prevented.

Next, a method of manufacturing a semiconductor device according to the present embodiment will be described for each step with reference to FIGS.

First, the main surface of the semiconductor substrate 1 is separated into each element formation region by a field insulating film 2, and a diffusion layer such as a source region and a drain region 3 is formed in each element formation region. A gate electrode 5 made of polycrystalline silicon is formed on the main surface of the semiconductor substrate 1 with a gate insulating film 4 interposed therebetween, and a wiring layer 6 is formed on the field insulating film 2 in the same layer as the gate electrode 5. ing.

The side surfaces of the gate electrode 5 and the wiring layer 6 are covered with sidewalls 7, and the upper surfaces of the source and drain regions 3, the gate electrode 5 and the wiring layer 6 are reacted with a refractory metal such as titanium to form a silicide. Salicide treatment is performed.

The semiconductor substrate 1 and each element formed on the main surface of the semiconductor substrate 1 are covered with an interlayer insulating film 20. The interlayer insulating film 20 is formed of a silicon oxide film (200 nm) of P-TEOS and an oxide of SOG. Silicon film (200n
m), a silicon oxide film (800 nm) is sequentially deposited by P-TEOS, and then polished by a CMP technique to about 500 nm (amount of polishing on a large-area wiring layer) to flatten the element steps caused by the gate electrode 5 and the like. And P-TEOS
A silicon oxide film (800 nm) is deposited. An opening exposing the connection region of the source region, the drain region 3 and the wiring layer 6 is formed in the interlayer insulating film 20 by photolithography and dry etching.

Subsequently, after purifying such as removal of the natural oxide film in the connection region by argon plasma, a barrier film 21a on which titanium (10 nm) and titanium nitride (50 nm) are deposited by sputtering, a tungsten film by CVD Plugs 21 b (300 nm) are sequentially deposited and processed by CMP to form plugs 21 in the openings of the interlayer insulating film 20. This state is shown in FIG.

Next, a groove (600 nm in depth) in which the wiring layer forming region of the interlayer insulating film 20 has been removed is formed by photolithography and dry etching. At this time, since it is not necessary to form a groove for the plug 21, the plug 21 is deleted from the mask data. This state is shown in FIG.
Shown in

Next, natural oxidation of the surface (upper surface and side surface) of the plug 21 exposed by the groove is performed by argon plasma (Ar / H ₂ , Ar / NF ₃ , Ar / BCl ₃ or the like is used depending on the material of the plug). After performing purification such as film removal, the barrier film 2 on which titanium nitride (50 nm) is deposited
2a and a copper film 22b (800 nm) are sequentially deposited by sputtering, and 450 ° C. in a hydrogen atmosphere in the same vacuum system.
A heat treatment is performed for 30 minutes to reflow the copper film 22b. This state is shown in FIG.

Next, the metal outside the groove is removed by polishing by the CMP technique, and the damascene wiring layer 22 is formed. FIG. 16 shows this state.

The state shown in FIG. 16 is the state shown in FIG. 12 described above, and thereafter, a silicon oxide film (300 nm) of P-TEOS and a silicon oxide film (300
nm), silicon oxide film by P-TEOS (300 nm)
Are formed successively, an opening for exposing the connection region of the plug 21 and the wiring layer 22 is formed by photolithography and dry etching, and a process similar to that of the plug 21 and the wiring layer 22 described above is performed. The second-layer plug 24 and the damascene wiring layer 25 can be formed. This state is shown in FIG. By repeating such a process, a multilayer wiring structure having a desired number of layers can be obtained.

In this embodiment, the plug 21 is connected to the wiring layer 2
2, the plug 21 can be directly connected to the plug 24 in the adjacent layer, so that the margin for mask alignment can be reduced and the chip area can be prevented from increasing.

FIG. 18 is a plan view of the state shown in FIG. 17 and shows the arrangement of the plug 24 and the wiring layers 22 and 25.

In this embodiment, the plug is arranged at an appropriate position to suppress excessive polishing of the copper film.
A plug is provided within 5 μm from the interlayer insulating film or another plug, and a continuous portion of the wiring is reduced to 5 μm or less to prevent dishing. In other words, by displacing the position of the wiring 22 as shown in FIG. Plug 24
Is adjusted, and in addition, in the portion where the wiring 22 to be connected is not arranged, and there is no need to provide a plug,
Dummy plugs 26 are formed to prevent dishing over a wider area.

(Embodiment 2) FIG. 19 is a longitudinal sectional view showing a main part of a semiconductor device according to another embodiment of the present invention.

The main surface of the semiconductor substrate 1 is separated into each element formation region by a field insulating film 2, and a diffusion layer such as a source region and a drain region 3 is formed in each element formation region. A gate electrode 5 made of polycrystalline silicon is formed on the main surface of the semiconductor substrate 1 with a gate insulating film 4 interposed therebetween, and a wiring layer 6 is formed in the same layer as the gate electrode 5.
Are formed on the field insulating film 2.

The side surfaces of the gate electrode 5 and the wiring layer 6 are covered with sidewalls 7, and the upper surfaces of the source region, the drain region 3, the gate electrode 5 and the wiring layer 6 react with a refractory metal such as titanium to be silicified. Salicide treatment has been performed.

The source region, drain region 3 or wiring layer 6 of each element formed on the main surface of the semiconductor substrate 1 is connected to one end of a plug 30 penetrating through the interlayer insulating film 20, and the other end of the plug 30 is connected to the interlayer insulating film. It is connected to the laminated damascene wiring layer 31 via the film 20. The interlayer insulating film 20 is made of P
After sequentially depositing a silicon oxide film (200 nm) by -TEOS, a silicon oxide film (200 nm) by SOG, and a silicon oxide film (800 nm) by P-TEOS,
About 500nm (polishing amount on large area wiring layer) by technology
Polishing is performed to flatten an element step caused by the gate electrode 5 and the like, and furthermore, a silicon oxide film (800 n
m) has been deposited.

In this embodiment, the plug 30 is formed of a barrier film 30a on which tungsten (60 nm) is deposited by sputtering, and a tungsten film 30b (300
nm) are sequentially deposited and processed by CMP.

The first damascene wiring layer 31 mainly used for local wiring is made of tungsten (50 n) formed by sputtering.
m), a barrier film 31a on which a film is deposited, and a tungsten film 31b (800 nm) formed by CVD are sequentially formed and polished by a CMP technique.

The damascene wiring layer 31 is connected to one end of a plug 32 penetrating the interlayer insulating film 23, and the other end of the plug 32 is connected to the laminated damascene wiring layer 33 via the interlayer insulating film 23. The interlayer insulating film 23 is made of P-TEO
A silicon oxide film of S (300 nm), a silicon oxide film of SOG (300 nm), and a silicon oxide film of P-TEOS (300 nm) are sequentially deposited.

The plug 32 of the second layer includes a barrier film 32a on which tungsten (60 nm) is deposited by sputtering,
The tungsten film 32b is formed by CVD, and the second damascene wiring layer 33 is formed of titanium (10n) by sputtering.
m), barrier film 3 on which titanium nitride (50 nm) is deposited
3a, an aluminum alloy film 33b (300 nm) is sequentially deposited by sputtering or CVD, and is formed by processing by CMP.

The other ends of the plugs 30 and 32 reach the upper surface of the damascene wiring layer 33, and the other side surface of the plug 30 is connected to the damascene wiring layer 33.

In the semiconductor device of this embodiment, the plug 3
Tungsten barrier film 32 by sputtering 0, 32
a and the tungsten film 32b formed by CVD, the resistance of the plug can be made lower than that of titanium / titanium nitride / tungsten described above.

The first layers of the damascene wiring layers 31 and 33 are tungsten by sputtering and tungsten by CVD, and the second layer is titanium and titanium nitride by sputtering and an aluminum alloy by sputtering or CVD. Although the wiring resistance is increased as compared with the wiring layer of the above-described embodiment, the reliability of the process is increased because the wiring layer is formed of a conventionally used material.

The method of manufacturing the semiconductor device of the present embodiment is the same as the method of manufacturing the semiconductor device of the above-described embodiment.

(Embodiment 3) FIG. 20 is a longitudinal sectional view showing a main part of a semiconductor device according to another embodiment of the present invention.

The main surface of the semiconductor substrate 1 is separated into each element formation region by a field insulating film 2, and a diffusion layer such as a source region and a drain region 3 is formed in each element formation region. A gate electrode 5 made of polycrystalline silicon is formed on the main surface of the semiconductor substrate 1 with a gate insulating film 4 interposed therebetween, and a wiring layer 6 is formed in the same layer as the gate electrode 5.
Are formed on the field insulating film 2.

The side surfaces of the gate electrode 5 and the wiring layer 6 are covered with sidewalls 7, and the upper surfaces of the source region, the drain region 3, the gate electrode 5 and the wiring layer 6 are reacted with a refractory metal such as titanium to form silicide. Salicide treatment has been performed.

The source region, drain region 3 or wiring layer 6 of each element formed on the main surface of the semiconductor substrate 1 is connected to one end of a plug 21 penetrating through the interlayer insulating film 40, and the other end of the plug 21 is connected to the interlayer insulating film. It is connected to the laminated damascene wiring layer 22 via the film 40.

The interlayer insulating film 40 of the present embodiment is formed by a PT
After sequentially depositing a silicon oxide film (200 nm) by EOS, a silicon oxide film (200 nm) by SOG, and a silicon oxide film (900 nm) by P-TEOS, about 500 nm (polishing amount on a large-area wiring layer) by CMP technology. After polishing to flatten the element steps caused by the gate electrode 5 and the like, the silicon nitride film 40a (1
00 nm) and a silicon oxide film (600
nm).

The plug 21 is made of titanium (1
0 nm), a barrier film 21a on which titanium nitride (50 nm) is deposited, and a tungsten film 21b (300
nm) are sequentially deposited and processed by CMP.

The damascene wiring layer 22 is made of titanium nitride (50
nm) and a copper film 22b (80
0 nm) is sequentially deposited by sputtering, heat-treated at 450 ° C. for 30 minutes in a hydrogen atmosphere in the same vacuum system, and the copper film 22 b is reflowed and polished by CMP to form a plug up to the upper surface of the wiring layer 22. The other end of the plug 21 is reached, the other end of the plug 21 is connected to the damascene wiring layer 22, and the damascene wiring layer 22 is connected to one end of the plug 24 that penetrates the interlayer insulating film 41. Damascene wiring layer 25 laminated via interlayer insulating film 41
It is connected to the.

The interlayer insulating film 41 of the present embodiment is made of PC
VD silicon nitride film 41a (100 nm), SOG silicon oxide film (200 nm), P-TEOS silicon oxide film (600 nm), P-CVD silicon nitride film 41b (100 nm), P-TEOS silicon oxide film (100 nm) (500 nm).

The silicon nitride films 40a, 41a and 41b can function as etching stoppers for the damascene wiring layer 22, the plug 24 and the damascene wiring layer 25, respectively, by performing etching with a high selectivity with respect to the silicon oxide film. .

Therefore, when the grooves for the damascene wiring layers 22 and 25 are formed, even if the etching progresses depending on the wiring width, the depth of the grooves, that is, the damascene wiring layers 22 and 25,
25 can be made uniform. Also, plug 2
When forming the opening for 4, the two-step etching is performed, and the over-etching of the silicon oxide film in the vicinity of the lower wiring layer 22 connected to the plug 24 or the plug 21 can be reduced.

The silicon nitride films 40a, 41a, 41b
Although has a higher dielectric constant than that of a silicon oxide film, it is considered that it has no significant effect because the film thickness is relatively thin.

Thereafter, an opening for exposing the connection region of the plug 21 and the wiring layer 22 is formed by photolithography and dry etching, and the plug 24 of the second layer is formed by the same process as the plug 21 and the wiring layer 22 described above.
And a damascene wiring layer 25 is formed.

The method of manufacturing the semiconductor device of the present embodiment is the same as the method of manufacturing the semiconductor device of the above-described embodiment.

As described above, the invention made by the present inventor
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention.

For example, the plug or the wiring layer is not limited to those described above, and the present invention can be carried out using other methods such as plating and other materials.

[0084]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the present invention, it is possible to prevent the copper film from being excessively polished at the time of the CMP process by the plug reaching the upper surface of the wiring layer, thereby preventing the occurrence of dishing. This has the effect.

(2) According to the present invention, the above effect (1) has an effect that an increase in wiring resistance due to a partial decrease in film thickness due to dishing can be prevented.

(3) According to the present invention, the wiring layer can be formed flat due to the above effect (1), so that the upper wiring layer laminated on this wiring layer can be easily flattened. effective.

(4) According to the present invention, in a portion where the wiring width of the wiring layer is small, there is an effect that the wiring layer can be formed by a configuration in which the plug is partially extended.

(5) According to the present invention, according to the effect (4), there is an effect that it is possible to prevent disconnection or increase in resistance due to insufficient embedding in a groove having a high aspect ratio.

(6) According to the present invention, there is an effect that plugs in adjacent layers can be directly connected.

(7) According to the present invention, the above-mentioned effect (6) has an effect that an error in mask alignment is reduced and an increase in chip area can be prevented.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing the formation of a wiring layer of a conventional semiconductor device for each process.

FIG. 2 is a longitudinal sectional view showing the formation of a wiring layer of a conventional semiconductor device for each process.

FIG. 3 is a longitudinal sectional view showing the formation of a wiring layer of a conventional semiconductor device for each process.

FIG. 4 is a longitudinal sectional view showing a damascene wiring layer formation of a conventional semiconductor device for each process.

FIG. 5 is a longitudinal sectional view showing the formation of a damascene wiring layer of a conventional semiconductor device for each process.

FIG. 6 is a longitudinal sectional view showing the formation of a damascene wiring layer of a conventional semiconductor device for each process.

FIG. 7 is a longitudinal sectional view showing, for each step, the formation of a damascene wiring layer of a conventional semiconductor device.

FIG. 8 is a longitudinal sectional view showing the formation of a damascene wiring layer of a conventional semiconductor device for each process.

FIG. 9 is a longitudinal sectional view showing a problem of a conventional damascene wiring layer.

FIG. 10 is a longitudinal sectional view showing a problem of a conventional damascene wiring layer.

FIG. 11 is a longitudinal sectional view showing a problem of a conventional damascene wiring layer.

FIG. 12 is a perspective view illustrating a main part of a semiconductor device according to an embodiment of the present invention;

FIG. 13 is a longitudinal sectional view showing, for each step, formation of a wiring layer of the semiconductor device according to the embodiment of the present invention;

FIG. 14 is a longitudinal sectional view showing, for each step, formation of a wiring layer of the semiconductor device according to the embodiment of the present invention;

FIG. 15 is a longitudinal sectional view showing, for each step, formation of a wiring layer of the semiconductor device according to the embodiment of the present invention;

FIG. 16 is a longitudinal sectional view showing, for each step, formation of a wiring layer of the semiconductor device according to the embodiment of the present invention;

FIG. 17 is a longitudinal sectional view showing, for each step, formation of a wiring layer of the semiconductor device according to the embodiment of the present invention;

FIG. 18 is a plan view illustrating a main part of a semiconductor device according to an embodiment of the present invention;

FIG. 19 is a longitudinal sectional view showing a main part of a semiconductor device according to another embodiment of the present invention.

FIG. 20 is a longitudinal sectional view illustrating a main part of a semiconductor device according to another embodiment of the present invention;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Field insulating film, 3 ... Source region, drain region, 4 ... Gate insulating film, 5 ... Gate electrode, 6 ... Wiring layer, 7 ... Side wall, 8, 11, 1
5, 20, 23, 40, 41 ... interlayer insulating film, 9, 12,
16, 21, 24, 30, 32... Plugs, 9a, 21
a, 30a, 32a ... barrier film, 9b, 21b, 30
b, 32b: tungsten film, 10, 13, wiring layer, 1
0a: barrier film, 10b: aluminum alloy film, 10c
... Anti-reflection film, 14, 17, 22, 25, 31, 33 ...
Damascene wiring layer, 14a, 22a, 31a, 33a ... barrier film, 14b, 22b ... copper film, 14c ... void, 26
... Dummy plug, 31b, 33b ... Tungsten film, 4
0a, 41a, 41b: silicon nitride films.

Claims (10)

[Claims] 1. A semiconductor device in which a wiring layer laminated via an interlayer insulating film is connected by a plug penetrating the interlayer insulating film, wherein the connected plug reaches the upper surface of the wiring layer, and the plug A side surface of the semiconductor device is connected to the wiring layer. 2. The semiconductor device according to claim 1, wherein said wiring layer is a wiring layer formed by a damascene method. 3. The wiring layer is mainly composed of copper,
3. The semiconductor device according to claim 1, wherein the plug is made of a material that is more wear-resistant than copper. 4. The position of the plug is adjusted by shifting the position of the wiring layer, so that a continuous portion of the wiring layer is shifted by 5 mm.
The thickness is set to be equal to or less than μm.
The semiconductor device according to claim 1. 5. By arranging a dummy plug,
The semiconductor device according to claim 1, wherein a continuous portion of the wiring layer has a thickness of 5 μm or less. 6. A method for manufacturing a semiconductor device in which wiring layers stacked via an interlayer insulating film are connected by a plug penetrating the interlayer insulating film, wherein: a step of forming the interlayer insulating film; Providing an opening in which a plug is formed in the film; forming a plug reaching the upper surface of the interlayer insulating film in the opening; forming a groove in the interlayer insulating film in which a wiring layer is formed; Forming a wiring layer therein and connecting the wiring layer to a side surface of the plug. 7. The method according to claim 6, wherein the wiring layer is a wiring layer formed by a damascene method. 8. The wiring layer is mainly composed of copper,
The method according to claim 6, wherein the plug is made of a material that is more wear-resistant than copper. 9. The position of the plug is adjusted by shifting the position of the wiring layer, so that a continuous portion of the wiring layer is shifted by 5 mm.
The thickness is set to be equal to or less than μm.
13. The method for manufacturing a semiconductor device according to claim 1. 10. The method of manufacturing a semiconductor device according to claim 6, wherein a continuous portion of the wiring layer is reduced to 5 μm or less by arranging a dummy plug. .